CY7C403-15PC Cypress Semiconductor Corporation., CY7C403-15PC Datasheet

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CY7C403-15PC

Manufacturer Part Number
CY7C403-15PC
Description
64 x 4 Cascadable FIFO, 64 x 5 Cascadable FIFO
Manufacturer
Cypress Semiconductor Corporation.
Datasheet

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Part Number
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Part Number:
CY7C403-15PC
Manufacturer:
TI
Quantity:
6 221
Features
Functional Description
The CY7C401 and CY7C403 are asynchronous first-in
first-out (FIFOs) organized as 64 four-bit words. The CY7C402
and CY7C404 are similar FIFOs organized as 64 five-bit
Selection Guide
Logic Block Diagram
Cypress Semiconductor Corporation
Operating Frequency (MHz)
Maximum Operating
Current (mA)
• 64 x 4 (CY7C401 and CY7C403)
• Processed with high-speed CMOS for optimum
• 25-MHz data rates
• 50-ns bubble-through time—25 MHz
• Expandable in word width and/or length
• 5-volt power supply 10% tolerance, both commercial
• Independent asynchronous inputs and outputs
• TTL-compatible interface
• Output enable function available on CY7C403 and
• Capable of withstanding greater than 2001V electro-
• Pin compatible with MMI 67401A/67402A
64 x 5 (CY7C402 and CY7C404)
High-speed first-in first-out memory (FIFO)
speed/power
and military
CY7C404
static discharge
(DI 4 )
DI 0
DI 1
DI 2
DI 3
MR
SI
IR
CONTROL
MASTER
DATAIN
RESET
INPUT
LOGIC
WRITE MULTIPLEXER
READ MULTIPLEXER
WRITE POINTER
READ POINTER
MEMORY
ARRAY
Commercial
Military
3901 North First Street
CONTROL
OUTPUT
ENABLE
OUTPUT
DATAIN
LOGIC
C401–1
OE
DO 0
DO 1
DO 2
DO 3
(DO 4 )
SO
OR
7C401/2–5
(CY7C401) NC
(CY7C403) OE
words. Both the CY7C403 and CY7C404 have an output en-
able (OE) function.
The devices accept 4- or 5-bit words at the data input (DI
DI
words stack up at the output (DO
were entered. A read command on the shift out (SO) input
causes the next to last word to move to the output and all data
shifts down once in the stack. The input ready (IR) signal acts
as a flag to indicate when the input is ready to accept new data
(HIGH), to indicate when the FIFO is full (LOW), and to provide
a signal for a cascading. The output ready (OR) signal is a flag
to indicate the output contains valid data (HIGH), to indicate
the FIFO is empty (LOW), and to provide a signal for cascad-
ing.
Parallel expansion for wider words is accomplished by logical-
ly ANDing the IR and OR signals to form composite signals.
Serial expansion is accomplished by tying the data inputs of
one device to the data outputs of the previous device. The IR
pin of the receiving device is connected to the SO pin of the
sending device, and the OR pin of the sending device is con-
nected to the SI pin of the receiving device.
Reading and writing operations are completely asynchronous,
allowing the FIFO to be used as a buffer between two digital
machines of widely differing operating frequencies. The
25-MHz operation makes these FIFOs ideal for high-speed
communication and controller applications.
75
5
n
Pin Configurations
) under the control of the shift in (SI) input. The stored
GND
DI
DI
DI
DI
DI
DI
DI
NC
SI
IR
SI
0
1
2
0
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
San Jose
64 x 4 Cascadable FIFO
64 x 5 Cascadable FIFO
CY7C401
CY7C403
910111213
3 2 1
CY7C401
CY7C403
7C40X–10
DIP
LCC
20
10
75
90
C401–2
16
15
14
13
12
11
10
19
9
C401–3
18
17
16
15
14
V CC
SO
OR
DO
DO
DO
DO
MR
NC
OR
DO
DO
DO
0
1
2
3
CY7C401/CY7C403
CY7C402/CY7C404
0
1
2
March 1986 – Revised April 1995
(CY7C402) NC
(CY7C404) OE
CA 95134
7C40X–15
0
DI
DI
DI
DI
15
75
90
GND
DI
DI
DI
SI
– DO
DI
DI
0
1
2
3
IR
SI
0
1
2
3
4
4
5
6
7
8
1
2
3
4
5
6
7
8
9
910111213
3 2 1
CY7C402
CY7C404
n
CY7C402
CY7C404
LCC
) in the order they
DIP
20
408-943-2600
19
C401–5
7C40X–25
C401–4
18
17
16
15
14
18
17
16
15
14
13
12
11
10
OR
DO
DO
DO
DO
25
75
90
V CC
SO
OR
DO
DO
DO
DO
DO
MR
0
1
2
3
0
1
2
3
4
0

Related parts for CY7C403-15PC

CY7C403-15PC Summary of contents

Page 1

... Commercial Current (mA) Military Cypress Semiconductor Corporation Cascadable FIFO Cascadable FIFO words. Both the CY7C403 and CY7C404 have an output en- able (OE) function. The devices accept 4- or 5-bit words at the data input ( under the control of the shift in (SI) input. The stored n words stack up at the output (DO were entered ...

Page 2

... Latch-Up Current ..................................................... >200 mA Operating Range Range Commercial [1] Military Test Conditions V = Min –4 Min 8 GND [3] GND 5.5V OUT CC CC Output Disabled (CY7C403 and CY7C404) [ Max GND CC OUT V = Max OUT Test Conditions MHz 4. CY7C401/CY7C403 CY7C402/CY7C404 Ambient Temperature + 10% – +125 C 5V 10% [2] 7C40X–10, 15, 25 Min ...

Page 3

... Min. Max. Min. Max. Min. Max. Note Note 9 0 Note 200 Note 10 5 Note Note 11 50 — Note 12 — ) conditions exist. BT –500 mV and V +500 mV levels on the output CY7C401/CY7C403 CY7C402/CY7C404 ALL INPUT PULSES 90% 90% 10 7C40X–10 7C40X–15 7C40X–25 Min. Max 21/ 28/ ...

Page 4

... When this violation occurs, the operation of the FIFO is unpre- dictable. It must then be reset, and all data is lost. Application of the 7C403–25/7C404– MHz Application of the CY7C403 or CY7C404 Cypress CMOS FIFOs requires knowledge of characteristics that are not easily specified in a datasheet, but which are necessary for reliable operation under all conditions will specify them here ...

Page 5

... SHIFT OUT t PHSO OUTPUT READY t HSO DATA OUT Bubble Through, Data Out To Data In Diagram SHIFT OUT SHIFT IN INPUT READY DATA IN I PLSI t DLIR I/f I PLSO t DLOR SIR 5 CY7C401/CY7C403 CY7C402/CY7C404 I DHIR O t DHOR t SOR t PIR t HIR C401–9 C401–10 C401–11 ...

Page 6

... Master Reset Timing Diagram MASTER RESET INPUT READY OUTPUT READY SHIFT IN DATA OUT Output Enable Timing Diagram OUTPUT ENABLE DATA OUT SOR t PMR t DIR t DOR t DSI t LZMR t t HZOE OOE NOTE 10 6 CY7C401/CY7C403 CY7C402/CY7C404 t POR C401–12 C401–13 C401–14 ...

Page 7

... AMBIENT TEMPERATURE ( C) NORMALIZED I vs. FREQUENCY 1.1 1.0 0.9 0.8 0.7 0.0 400 600 800 1000 CY7C401/CY7C403 CY7C402/CY7C404 OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE =5. = 125 0.0 1.0 2.0 3.0 OUTPUT VOLTAGE (V) OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE ...

Page 8

... FIFOs are expandable in depth and width. However, in forming wider words two external gates are required to generate composite input and output ready flags. This need is due to the variation of delays of the FIFOs. [18] 128 x 4 Application [19] 192 x 12 Application CY7C401/CY7C403 CY7C402/CY7C404 OR OUTPUT READY SO SHIFT OUT DATA OUT C401–16 SHIFT OUT COMPOSITE OUTPUT READY C401–17 MR ...

Page 9

... Molded DIP D4 18-Lead (300-Mil) CerDIP L61 20-Pin Square Leadless Chip Carrier D4 18-Lead (300-Mil) CerDIP P3 18-Lead (300-Mil) Molded DIP D4 18-Lead (300-Mil) CerDIP L61 20-Pin Square Leadless Chip Carrier 9 CY7C401/CY7C403 CY7C402/CY7C404 Operating Range Commercial Commercial Military Commercial Military Commercial Military Operating Range Commercial ...

Page 10

... Ordering Code 10 CY7C403–10DC CY7C403–10PC CY7C403–10DMB CY7C403–10LMB 15 CY7C403–15DC CY7C403–15PC CY7C403–15DMB CY7C403–15LMB 25 CY7C403–25DC CY7C403–25PC CY7C403–25DMB CY7C403–25LMB Speed Package (MHz) Ordering Code 10 CY7C404–10DC CY7C404–10PC CY7C404–10DMB CY7C404–10LMB 15 CY7C404–15DC CY7C404– ...

Page 11

... MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics Parameters Subgroups Max CY7C401/CY7C403 CY7C402/CY7C404 Switching Characteristics Parameters Subgroups 10 10, 11 PHSI 10, 11 PLSI 10, 11 SSI 10, 11 HSI 10, 11 DLIR 10, 11 DHIR 10, 11 PHSO 10, 11 PLSO 10, 11 DLOR 10, 11 DHOR 10, 11 SOR 10, 11 HSO 10 10, 11 SIR ...

Page 12

... Package Diagrams 16-Lead (300-Mil) CerDIP D2 MIL-STD-1835 D- 2 Config.A 20-Pin Square Leadless Chip Carrier L61 MIL-STD-1835 C–2A CY7C401/CY7C403 CY7C402/CY7C404 18-Lead (300-Mil) CerDIP D4 MIL-STD-1835 D-8 Config.A 12 ...

Page 13

... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. 16-Lead (300-Mil) Molded DIP P1 18-Lead (300-Mil) Molded DIP P3 CY7C401/CY7C403 CY7C402/CY7C404 ...

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