PIC16C73-10/SP Microchip Technology Inc., PIC16C73-10/SP Datasheet
PIC16C73-10/SP
Related parts for PIC16C73-10/SP
PIC16C73-10/SP Summary of contents
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... CMOS Microcontrollers with A/D Converter Devices included in this data sheet: • PIC16C72 • PIC16C74A • PIC16C73 • PIC16C76 • PIC16C73A • PIC16C77 • PIC16C74 PIC16C7X Microcontroller Core Features: • High-performance RISC CPU • Only 35 single word instructions to learn • All single cycle instructions except for program branches which are two cycle • ...
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... RA5/SS/AN4 OSC1/CLKIN 9 20 OSC2/CLKOUT 10 19 RC0/T1OSO/T1CKI 11 18 RC1/T1OSI/CCP2 12 17 RC2/CCP1 13 16 RC3/SCK/SCL 14 15 PIC16C73 PIC16C73A PIC16C76 DS30390E-page 2 RB7 MCLR/V RB6 RA0/AN0 RB5 RA1/AN1 RB4 RA2/AN2 RB3 RA3/AN3/V REF RB2 RA4/T0CKI RB1 RA5/SS/AN4 RB0/INT V V OSC1/CLKIN DD V OSC2/CLKOUT SS RC7 RC0/T1OSO/T1CKI RC6 ...
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... Pin Diagrams (Cont.’d) MQFP RC7/RX/DT RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7 RB0/INT PLCC RA4/T0CKI 7 RA5/SS/AN4 8 RE0/RD/AN5 9 RE1/WR/AN6 10 PIC16C74 RE2/CS/AN7 PIC16C74A OSC1/CLKIN 14 PIC16C77 OSC2/CLKOUT 15 RC0/T1OSO/T1CKI 1997 Microchip Technology Inc RC0/T1OSO/T1CKI 3 31 OSC2/CLKOUT 4 30 OSC1/CLKIN PIC16C74 RE2/CS/AN7 RE1/WR/AN6 RB1 9 25 RE0/RD/AN5 10 24 RB2 RA5/SS/AN4 ...
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... PIC16C7X Product Identification System........................................................................................................................................... 287 For register and module descriptions in this data sheet, device legends show which devices apply to those sections example, the legend below would mean that the following section applies only to the PIC16C72, PIC16C73A and PIC16C74A devices. Applicable Devices ...
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... A/D is provided. The 8-bit resolution is ideally suited for applications requiring low-cost analog inter- face, e.g. thermostat control, pressure sensing, etc. The PIC16C73/73A devices have 192 bytes of RAM, while the PIC16C76 has 368 byes of RAM. Each device has 22 I/O pins. In addition, several peripheral features are available including: three timer/counters, two Cap- ture/Compare/PWM modules and two serial ports ...
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... Yes Yes Yes Yes Yes — Yes Yes 18-pin DIP, 18-pin DIP, 18-pin DIP, 18-pin DIP, SOIC; SOIC SOIC; SOIC; 20-pin SSOP 20-pin SSOP 20-pin SSOP PIC16C73A PIC16C74A 192 192 TMR0, TMR0, TMR1, TMR1, TMR2 TMR2 SPI/I C, USART SPI/I C, USART — ...
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... The OTP devices, packaged in plastic packages, per- mit the user to program them once. In addition to the program memory, the configuration bits must also be programmed. 1997 Microchip Technology Inc. 2.3 Quick-Turnaround-Production (QTP) Devices Microchip offers a QTP Programming Service for fac- tory production orders ...
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... PIC16C7X NOTES: DS30390E-page 8 1997 Microchip Technology Inc. ...
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... MHz) except for program branches. The table below lists program memory (EPROM) and data memory (RAM) for each PIC16C7X device. Program Device Memory PIC16C72 PIC16C73 PIC16C73A PIC16C74 PIC16C74A PIC16C76 PIC16C77 The PIC16CXX can directly or indirectly address its register fi ...
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... FSR reg STATUS reg 3 MUX Power-up Timer Oscillator ALU Power-on 8 Reset Watchdog W reg Timer Brown-out Reset Timer2 CCP1 PORTA RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/V REF RA4/T0CKI RA5/SS/AN4 PORTB RB0/INT RB7:RB1 PORTC RC0/T1OSO/T1CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6 RC7 1997 Microchip Technology Inc. ...
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... Control Timing Generation OSC1/CLKIN OSC2/CLKOUT MCLR Timer0 Timer1 CCP1 CCP2 Note 1: Higher order bits are from the STATUS register. 2: Brown-out Reset is not available on the PIC16C73. 1997 Microchip Technology Inc. 8 Data Bus Program Counter 8 Level Stack RAM (13-bit) File Registers (1) RAM Addr ...
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... Brown-out (2) Reset Parallel Slave Port Timer2 A/D Synchronous USART Serial Port PORTA RA0/AN0 RA1/AN1 RA2/AN2 RA3/AN3/V REF RA4/T0CKI RA5/SS/AN4 PORTB RB0/INT RB7:RB1 PORTC RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT PORTD RD7/PSP7:RD0/PSP0 PORTE RE0/RD/AN5 RE1/WR/AN6 RE2/CS/AN7 1997 Microchip Technology Inc. ...
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... Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in serial programming mode. 3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise. 1997 Microchip Technology Inc. I/O/P Buffer ...
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... PIC16C7X TABLE 3-2: PIC16C73/73A/76 PINOUT DESCRIPTION DIP SOIC Pin Name Pin# Pin# OSC1/CLKIN 9 9 OSC2/CLKOUT MCLR/V PP RA0/AN0 2 2 RA1/AN1 3 3 RA2/AN2 4 4 RA3/AN3 REF RA4/T0CKI 6 6 RA5/SS/AN4 7 7 RB0/INT 21 21 RB1 22 22 RB2 23 23 RB3 24 24 RB4 25 25 RB5 26 26 RB6 ...
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... This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel Slave Port mode (for interfacing to a microprocessor bus). 4: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise. 1997 Microchip Technology Inc. I/O/P Buffer ...
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... Ground reference for logic and I/O pins. P — Positive supply for logic and I/O pins. — These pins are not internally connected. These pins should be left unconnected. I/O = input/output P = power TTL = TTL input ST = Schmitt Trigger input 2 C modes mode). 1997 Microchip Technology Inc. ...
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... Instruction @ address SUB_1 All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed. 1997 Microchip Technology Inc. 3.2 Instruction Flow/Pipelining An “ ...
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... PIC16C7X NOTES: DS30390E-page 18 1997 Microchip Technology Inc. ...
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... On-chip Program Memory 1997 Microchip Technology Inc. FIGURE 4-2: CALL, RETURN RETFIE, RETLW 0000h 0004h 0005h 07FFh 0800h 1FFFh PIC16C7X PIC16C73/73A/74/74A PROGRAM MEMORY MAP AND STACK PC<12:0> 13 Stack Level 1 Stack Level 8 Reset Vector 0000h Interrupt Vector 0004h 0005h On-chip Program Memory (Page 0) ...
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... GENERAL PURPOSE REGISTER FILE 07FFh 0800h The register file can be accessed either directly, or indi- rectly through 0FFFh (Section 4.5). 1000h 17FFh 1800h 1FFFh the File Select Register FSR 1997 Microchip Technology Inc. ...
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... ADCON0 9Fh 20h A0h BFh C0h 7Fh FFh Unimplemented data memory locations, read as '0'. Note 1: Not a physical register. 2: These registers are not physically imple- mented on the PIC16C73/73A, read as '0'. PIC16C7X PIC16C73/73A/74/74A REGISTER FILE MAP File Address (1) (1) INDF INDF 80h TMR0 ...
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... Purpose 118h 198h Register 119h 199h 16 Bytes 11Ah 19Ah 11Bh 19Bh 11Ch 19Ch 11Dh 19Dh 11Eh 19Eh 11Fh 19Fh 120h 1A0h General Purpose Register 80 Bytes 1EFh 16Fh 1F0h 170h accesses 70h - 7Fh 17Fh 1FFh Bank 3 1997 Microchip Technology Inc. ...
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... Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset. 4: The IRP and RP1 bits are reserved on the PIC16C72, always maintain these bits clear. 1997 Microchip Technology Inc. The special function registers can be classified into two sets (core and peripheral). Those registers associated with the “ ...
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... UA BF --00 0000 --00 0000 — — — — — — — — — — — — — — — — — — — — PCFG1 PCFG0 ---- -000 ---- -000 1997 Microchip Technology Inc. ...
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... PORTD and PORTE are not physically implemented on the PIC16C73/73A, read as ‘0’. 6: Brown-out Reset is not implemented on the PIC16C73 or the PIC16C74, read as '0'. 7: The IRP and RP1 bits are reserved on the PIC16C73/73A/74/74A, always maintain these bits clear. 1997 Microchip Technology Inc. Bit 5 ...
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... These registers can be addressed from either bank. 5: PORTD and PORTE are not physically implemented on the PIC16C73/73A, read as ‘0’. 6: Brown-out Reset is not implemented on the PIC16C73 or the PIC16C74, read as '0'. 7: The IRP and RP1 bits are reserved on the PIC16C73/73A/74/74A, always maintain these bits clear. DS30390E-page 26 Bit 5 ...
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... Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset. 3: Bits PSPIE and PSPIF are reserved on the PIC16C76, always maintain these bits clear. 4: These registers can be addressed from any bank. 5: PORTD and PORTE are not physically implemented on the PIC16C76, read as ‘0’. 1997 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 ...
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... UA BF 0000 0000 0000 0000 — — — — — — TRMT TX9D 0000 -010 0000 -010 0000 0000 0000 0000 — — — — — — — — — — PCFG1 PCFG0 ---- -000 ---- -000 1997 Microchip Technology Inc. ...
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... Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset. 3: Bits PSPIE and PSPIF are reserved on the PIC16C76, always maintain these bits clear. 4: These registers can be addressed from any bank. 5: PORTD and PORTE are not physically implemented on the PIC16C76, read as ‘0’. 1997 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 ...
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... Note 2: The C and DC bits operate as a borrow and digit borrow bit, respectively, in sub- traction. See the SUBLW and SUBWF instructions for examples. R-1 R/W-x R/W-x R/W bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ Value at POR reset 1997 Microchip Technology Inc. ...
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... TMR0 Rate WDT Rate 000 001 010 011 100 101 110 1 : 128 111 1 : 256 1997 Microchip Technology Inc. Note: To achieve a 1:1 prescaler assignment for the TMR0 register, assign the prescaler to the Watchdog Timer. R/W-1 R/W-1 R/W-1 R/W-1 PSA PS2 PS1 PS0 ...
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... At least one of the RB7:RB4 pins changed state (must be cleared in software None of the RB7:RB4 pins have changed state Note 1: For the PIC16C73 and PIC16C74 interrupt occurs while the GIE bit is being cleared, the GIE bit may be unintentionally re-enabled by the RETFIE instruction in the user’s Interrupt Service Routine. ...
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... Disables the TMR2 to PR2 match interrupt bit 0: TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt 1997 Microchip Technology Inc. Note: Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt. R/W-0 ...
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... TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Note 1: PIC16C73/73A/76 devices do not have a Parallel Slave Port implemented, this bit location is reserved on these devices, always maintain this bit clear. DS30390E-page 34 R/W-0 ...
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... Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. 1997 Microchip Technology Inc. Note: Interrupt flag bits get set when an interrupt ...
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... TMR1 register overflowed (must be cleared in software TMR1 register did not overflow Note 1: PIC16C73/73A/76 devices do not have a Parallel Slave Port implemented, this bit location is reserved on these devices, always maintain this bit clear. Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON< ...
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... U-0 — — — — bit7 bit 7-1: Unimplemented: Read as '0' bit 0: CCP2IE: CCP2 Interrupt Enable bit 1 = Enables the CCP2 interrupt 0 = Disables the CCP2 interrupt 1997 Microchip Technology Inc. U-0 U-0 U-0 R/W-0 — — — CCP2IE bit0 PIC16C7X R = Readable bit ...
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... GIE (INTCON<7>). User soft- ware should ensure the appropriate inter- rupt flag bits are clear prior to enabling an interrupt. U-0 U-0 U-0 R/W-0 — — — CCP2IF bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ Value at POR reset 1997 Microchip Technology Inc. ...
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... BOR : Brown-out Reset Status bit Brown-out Reset occurred Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Note 1: Brown-out Reset is not implemented on the PIC16C73/74. 1997 Microchip Technology Inc. Note: BOR is unknown on Power-on Reset. It must then be set by the user and checked on subsequent resets to see if BOR is clear, indicating a brown-out has occurred ...
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... Note: PIC16C7X devices with 4K or less of pro- gram GOTO, CALL PCLATH<4>. The use of PCLATH<4> general purpose read/write bit is not rec- Opcode <10:0> ommended since this may affect upward compatibility with future products. memory ignore paging bit 1997 Microchip Technology Inc. ...
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... Data Memory 7Fh Bank 0 For register file map detail see Figure 4-4, and Figure 4-5. 1997 Microchip Technology Inc. 4.5 Indirect Addressing, INDF and FSR Registers Applicable Devices 72 73 73A 74 74A 76 77 The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing ...
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... PIC16C7X NOTES: DS30390E-page 42 1997 Microchip Technology Inc. ...
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... STATUS, RP0 ; Select Bank 1 MOVLW 0xCF ; Value used to ; initialize data ; direction MOVWF TRISA ; Set RA<3:0> as inputs ; RA<5:4> as outputs ; TRISA<7:6> are always ; read as '0'. 1997 Microchip Technology Inc. PIC16C7X FIGURE 5-1: BLOCK DIAGRAM OF RA3:RA0 AND RA5 PINS Data bus Port CK Q Data Latch ...
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... Input/output or slave select input for synchronous serial port or analog input Bit 5 Bit 4 Bit 3 Bit 2 RA5 RA4 RA3 RA2 — — — PCFG2 PCFG1 Value on: Value on all Bit 1 Bit 0 POR, other resets BOR RA1 RA0 --0x 0000 --0u 0000 --11 1111 --11 1111 PCFG0 ---- -000 ---- -000 1997 Microchip Technology Inc. ...
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... Refer to the Embedded Control Handbook, "Implementing Wake-Up on Key Stroke" (AN552). Note: For the PIC16C73/74 change on the I/O pin should occur when the read opera- tion is being executed (start of the Q2 cycle), then interrupt flag bit RBIF may not get set. ...
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... PIC16C7X FIGURE 5-4: BLOCK DIAGRAM OF RB7:RB4 PINS (PIC16C73/74) (2) RBPU Data Latch Data bus Port CK TRIS Latch TRIS CK RD TRIS Latch Port Set RBIF From other Q D RB7:RB4 pins EN RB7:RB6 in serial programming mode Note 1: I/O pins have diode protection to V and enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION< ...
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... PORTB RB7 RB6 86h, 186h TRISB PORTB Data Direction Register 81h, 181h OPTION RBPU INTEDG Legend unknown unchanged. Shaded cells are not used by PORTB. 1997 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RB5 RB4 RB3 RB2 RB1 ...
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... RC4 can also be the SPI Data In (SPI mode) or data I/O (I Input/output port pin or Synchronous Serial Port data output Input/output port pin or USART Asynchronous Transmit, or USART Synchronous Clock Input/output port pin or USART Asynchronous Receive, or USART Synchronous Data ( I/O (1) pin Schmitt Trigger and mode). 1997 Microchip Technology Inc. ...
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... TABLE 5-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Address Name Bit 7 Bit 6 07h PORTC RC7 RC6 87h TRISC PORTC Data Direction Register Legend unknown unchanged. 1997 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 RC5 RC4 RC3 RC2 RC1 PIC16C7X Value on: ...
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... I/O PORT MODE (1) I/O pin CK Data Latch D Q Schmitt CK Trigger input TRIS Latch buffer RD TRIS and Function Value on: Value on all Bit 0 POR, other resets BOR RD0 xxxx xxxx uuuu uuuu 1111 1111 1111 1111 0000 -111 0000 -111 1997 Microchip Technology Inc. ...
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... Bit1: Direction Control bit for pin RE1/WR/AN6 1 = Input 0 = Output bit 0: Bit0: Direction Control bit for pin RE0/RD/AN5 1 = Input 0 = Output 1997 Microchip Technology Inc. Note Power-on Reset these pins are con- figured as analog inputs. FIGURE 5-8: PORTE BLOCK DIAGRAM (IN I/O PORT MODE) ...
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... Device is selected Bit 4 Bit 3 Bit 2 Bit 1 — — RE2 RE1 — PORTE Data Direction Bits — — PCFG2 PCFG1 Value on: Value on all Bit 0 POR, other resets BOR RE0 ---- -xxx ---- -uuu 0000 -111 0000 -111 PCFG0 ---- -000 ---- -000 1997 Microchip Technology Inc. ...
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... MOVWF PORTB MOVF PORTB,W fetched write to PORTB RB7:RB0 Instruction executed MOVWF PORTB write to PORTB 1997 Microchip Technology Inc. EXAMPLE 5-4: READ-MODIFY-WRITE INSTRUCTIONS ON AN I/O PORT ;Initial PORT settings: PORTB<7:4> Inputs ; ;PORTB<7:6> have external pull-ups and are ;not connected to other circuitry ; ; ; ...
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... FIGURE 5-11: PORTD AND PORTE BLOCK DIAGRAM (PARALLEL SLAVE PORT) Data bus PORT CK TTL PORT One bit of PORTD Set interrupt flag PSPIF (PIR1<7>) Read Chip Select Write Note: I/O pin has protection diodes to V 1997 Microchip Technology Inc. RDx pin RD TTL CS TTL WR TTL and ...
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... OBF IBOV PSPMODE 0Ch PIR1 PSPIF ADIF RCIF 8Ch PIE1 PSPIE ADIE RCIE 9Fh ADCON1 — — — Legend unknown unchanged unimplemented read as '0'. Shaded cells are not used by the Parallel Slave Port. 1997 Microchip Technology Inc Bit 4 Bit 3 Bit 2 Bit 1 — ...
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... PIC16C7X NOTES: DS30390E-page 56 1997 Microchip Technology Inc. ...
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... MODULES Applicable Devices 72 73 73A 74 74A 76 77 The PIC16C72, PIC16C73/73A, PIC16C76/77 each have three timer modules. Each module can generate an interrupt to indicate that an event has occurred (i.e. timer overflow). Each of these modules is explained in full detail in the following sections. The timer modules are: • ...
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... PIC16C7X NOTES: DS30390E-page 58 1997 Microchip Technology Inc. ...
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... Fetch T0 T0+1 TMR0 Instruction Executed 1997 Microchip Technology Inc. Source Edge Select bit T0SE (OPTION<4>). Clearing bit T0SE selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 7.2. The prescaler is mutually exclusively shared between the Timer0 module and the Watchdog Timer. The pres- caler assignment is controlled in software by control bit PSA (OPTION< ...
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... NT0 reads NT0 FFh 00h Inst (PC+1) Inst (PC) Dummy cycle PC+4 PC+5 PC+6 MOVF TMR0,W NT0+1 PC+6 Read TMR0 Read TMR0 reads NT0 reads NT0 + 01h 02h 0004h 0005h Inst (0004h) Inst (0005h) Dummy cycle Inst (0004h) 1997 Microchip Technology Inc. ...
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... Therefore, the error in measuring the interval between two edges on Timer0 input = 4Tosc max. 2: External clock if no prescaler selected, Prescaler output otherwise. 3: The arrows indicate the points in time where sampling occurs. 1997 Microchip Technology Inc. When a prescaler is used, the external clock input is divided by the asynchronous ripple-counter type pres- caler so that the prescaler output is symmetrical ...
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... Writing to TMR0 when the prescaler is assigned to Timer0 will clear the prescaler count, but will not change the prescaler assignment SYNC Cycles PSA 8-bit Prescaler 1MUX PS2:PS0 PSA WDT Time-out Data Bus 8 TMR0 reg Set flag bit T0IF on Overflow 1997 Microchip Technology Inc. ...
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... PEIE 10Bh,18Bh 81h,181h OPTION RBPU INTEDG 85h TRISA — — Legend unknown unchanged unimplemented locations read as '0'. Shaded cells are not used by Timer0. 1997 Microchip Technology Inc. BSF STATUS, RP0 ;Bank 1 MOVLW b'xx0x0xxx' ;Select clock source and prescale value of MOVWF OPTION_REG ...
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... PIC16C7X NOTES: DS30390E-page 64 1997 Microchip Technology Inc. ...
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... RC1/ T1OSI/CCP2 and RC0/T1OSO/T1CKI pins become inputs. That is, the TRISC<1:0> value is ignored. For the PIC16C73/74, when the Timer1 oscillator is enabled (T1OSCEN is set), RC1/T1OSI/CCP2 pin becomes an input, however the RC0/T1OSO/T1CKI pin will have to be configured as an input by setting the TRISC< ...
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... RC1/T1OSI/CCP2 Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain. 2: The CCP2 module is not implemented in the PIC16C72. 3: For the PIC16C73 and PIC16C74, the Schmitt Trigger is not implemented in external clock mode. DS30390E-page 66 8.2.1 ...
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... Reading the 16-bit value requires some care. Example 8 example routine to read the 16-bit timer value. This is useful if the timer cannot be stopped. 1997 Microchip Technology Inc. PIC16C7X EXAMPLE 8-1: READING A 16-BIT FREE- RUNNING TIMER ; All interrupts are disabled ...
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... Shaded cells are not used by the Timer1 module. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A/76, always maintain these bits clear. 2: The PIC16C72 does not have a Parallel Slave Port or a USART, these bits are unimplemented, read as '0'. ...
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... TMR2 interrupt (latched in flag bit TMR2IF, (PIR1<1>)). Timer2 can be shut off by clearing control bit TMR2ON (T2CON<2>) to minimize power consumption. Figure 9-2 shows the Timer2 control register. 1997 Microchip Technology Inc. 9.1 Timer2 Prescaler and Postscaler Applicable Devices 72 73 73A 74 74A 76 77 ...
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... Shaded cells are not used by the Timer2 module. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A/76, always maintain these bits clear. 2: The PIC16C72 does not have a Parallel Slave Port or a USART, these bits are unimplemented, read as '0'. ...
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... The PWMs will have the same frequency, and update rate (TMR2 interrupt). PWM Capture None PWM Compare None 1997 Microchip Technology Inc. PIC16C7X CCP1 module: Capture/Compare/PWM Register1 (CCPR1) is com- prised of two 8-bit registers: CCPR1L (low byte) and CCPR1H (high byte). The CCP1CON register controls the operation of CCP1. All are readable and writable. ...
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... CCP1IF following any such change in operating mode Readable bit W = Writable bit bit0 U = Unimplemented bit, read as ‘0’ =Value at POR reset OPERATION BLOCK DIAGRAM Set flag bit CCP1IF (PIR1<2>) CCPR1H CCPR1L Capture Enable TMR1H TMR1L CCP1CON<3:0> 1997 Microchip Technology Inc. ...
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... Special event trigger will: reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>), and set bit GO/DONE (ADCON0<2>) which starts an A/D conversion (CCP1 only for PIC16C72, CCP2 only for PIC16C73/73A/74/74A/76/77). Special Event Trigger Set flag bit CCP1IF (PIR1<2>) CCPR1H CCPR1L ...
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... Maximum PWM resolution (bits) for a given PWM frequency: Note: If the PWM duty cycle value is longer than the PWM period the CCP1 pin will not be cleared. • OSC (TMR2 prescale value) Tosc • (TMR2 prescale value OSC log F PWM = bits log(2) 1997 Microchip Technology Inc. ...
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... Shaded cells are not used by Capture and Timer1. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A/76, always maintain these bits clear. 2: The PIC16C72 does not have a Parallel Slave Port, USART or CCP2 module, these bits are unimplemented, read as '0'. ...
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... Shaded cells are not used by PWM and Timer2. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A/76, always maintain these bits clear. 2: The PIC16C72 does not have a Parallel Slave Port, USART or CCP2 module, these bits are unimplemented, read as '0'. ...
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... SPI Mode for PIC16C72/73/73A/74/74A ..........78 11.3 SPI Mode for PIC16C76/77..............................83 11.4 I2C™ Overview ................................................89 11.5 SSP I2C Operation...........................................93 Refer to Application Note AN578, “Use of the SSP 2 Module in the I C Multi-Master Environment.” 1997 Microchip Technology Inc. Applicable Devices 72 73 73A 74 74A 76 77 PIC16C7X DS30390E-page 77 ...
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... PIC16C7X 11.2 SPI Mode for PIC16C72/73/73A/74/74A This section contains register definitions and opera- tional characteristics of the SPI module for the PIC16C72, PIC16C73, PIC16C73A, PIC16C74A. FIGURE 11-1: SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS 94h) U-0 U-0 R-0 R-0 — — D/A ...
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... C firmware controlled Master Mode (slave idle) 2 1110 = I C slave mode, 7-bit address with start and stop bit interrupts enabled 2 1111 = I C slave mode, 10-bit address with start and stop bit interrupts enabled 1997 Microchip Technology Inc. Applicable Devices 72 73 73A 74 74A 76 77 R/W-0 R/W-0 R/W-0 R/W-0 ...
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... Bank 0 ;W reg = contents ;of SSPBUF ;Save in user RAM ;W reg = contents ; of TXDATA ;New data to xmit Internal data bus Write SSPBUF reg SSPSR reg shift bit0 clock Enable Edge 2 Clock Select SSPM3:SSPM0 TMR2 output 4 2 Edge Select T Prescaler CY 4, 16, 64 1997 Microchip Technology Inc. ...
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... Serial Input Buffer (SSPBUF register) Shift Register (SSPSR) MSb PROCESSOR 1 1997 Microchip Technology Inc. Applicable Devices 72 73 73A 74 74A 76 77 The master can initiate the data transfer at any time because it controls the SCK. The master determines when the slave (Processor broadcast data by the software protocol ...
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... Legend unknown unchanged unimplemented read as '0'. Shaded cells are not used by the SSP in SPI mode. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A, always maintain these bits clear. 2: The PIC16C72 does not have a Parallel Slave Port or USART, these bits are unimplemented, read as '0'. ...
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... Receive (SPI and I C modes Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty 2 Transmit (I C mode only Transmit in progress, SSPBUF is full 0 = Transmit complete, SSPBUF is empty 1997 Microchip Technology Inc. Applicable Devices 72 73 73A 74 74A 76 77 R-0 R-0 R-0 R-0 S R/W ...
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... C slave mode, 10-bit address with start and stop bit interrupts enabled DS30390E-page 84 Applicable Devices 72 73 73A 74 74A 76 77 R/W-0 R/W-0 R/W-0 R/W-0 SSPM3 SSPM2 SSPM1 SSPM0 bit0 /4 OSC /16 OSC /64 OSC R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ =Value at POR reset 1997 Microchip Technology Inc. ...
Page 85
... Example 11-2 shows the loading of the SSPBUF (SSPSR) for data transmission. The shaded instruction is only required if the received data is meaningful. 1997 Microchip Technology Inc. Applicable Devices 72 73 73A 74 74A 76 77 EXAMPLE 11-2: LOADING THE SSPBUF BCF ...
Page 86
... In sleep mode, the slave can transmit and receive data and wake the device from sleep. SPI Slave SSPM3:SSPM0 = 010xb SDO SDI SDI SDO LSb Serial Clock SCK SCK ) Serial Input Buffer (SSPBUF) Shift Register (SSPSR) MSb LSb PROCESSOR 2 1997 Microchip Technology Inc. ...
Page 87
... SS (optional) SCK (CKP = 0) SCK (CKP = 1) bit7 SDO SDI (SMP = 0) bit7 SSPIF 1997 Microchip Technology Inc. Applicable Devices 72 73 73A 74 74A Note: When the SPI is in Slave Mode with SS pin control enabled, (SSPCON<3:0> = 0100) the SPI module will reset if the SS pin is set ...
Page 88
... P S R/W UA bit1 bit0 bit0 Value on: Value on Bit 0 POR, all other BOR resets RBIF 0000 000x 0000 000u 1111 1111 1111 1111 xxxx xxxx uuuu uuuu SSPM0 0000 0000 0000 0000 --11 1111 --11 1111 BF 0000 0000 0000 0000 1997 Microchip Technology Inc. ...
Page 89
... Procedure that ensures that only one of the master devices will control the bus. This ensure that the transfer data does not get corrupted. Synchronization Procedure where the clock signals of two or more devices are synchronized. 1997 Microchip Technology Inc. Applicable Devices 72 73 73A 74 74A both cases the master generates the clock signal. ...
Page 90
... R/W ACK Wait Data State ACKNOWLEDGE not acknowledge acknowledge Clock Pulse for Acknowledgment acknowledgment signal from receiver Stop ACK Condition 1997 Microchip Technology Inc. ...
Page 91
... A = not acknowledge (SDA high) From master to slave S = Start Condition From slave to master P = Stop Condition 1997 Microchip Technology Inc. Applicable Devices 72 73 73A 74 74A 76 77 SCL is high), but occurs after a data transfer acknowl- edge pulse (not the bus-free state). This allows a mas- ter to send “ ...
Page 92
... SCL line low. The SCL line high time is determined by the device with the shortest high period, Figure 11-23. FIGURE 11-23: CLOCK SYNCHRONIZATION CLK 1 counter CLK reset 2 SCL start counting wait state HIGH period 1997 Microchip Technology Inc. ...
Page 93
... Serial Receive/Transmit Buffer (SSPBUF) • SSP Shift Register (SSPSR) - Not directly acces- sible • SSP Address Register (SSPADD) 1997 Microchip Technology Inc. Applicable Devices 72 73 73A 74 74A 76 77 The SSPCON register allows control of the I tion. Four mode selection bits (SSPCON<3:0>) allow ...
Page 94
... Receive first (high) byte of Address (bits SSPIF and BF are set). 9. Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. Generate ACK SSPBUF Pulse Yes Yes Set bit SSPIF (SSP Interrupt occurs if enabled) Yes Yes Yes Yes 1997 Microchip Technology Inc. ...
Page 95
... SCL S SSPIF (PIR1<3>) BF (SSPSTAT<0>) SSPOV (SSPCON<6>) 1997 Microchip Technology Inc. Applicable Devices 72 73 73A 74 74A SSP interrupt is generated for each data transfer byte. Flag bit SSPIF (PIR1<3>) must be cleared in soft- ware. The SSPSTAT register is used to determine the status of the byte. ...
Page 96
... A2 A1 ACK SCL held low while CPU responds to SSPIF cleared in software SSPBUF is written in software Set bit after writing to SSPBUF (the SSPBUF must be written-to before the CKP bit can be set) Transmitting Data ACK From SSP interrupt service routine 1997 Microchip Technology Inc. ...
Page 97
... Shaded cells are not used by SSP module in SPI mode. Note 1: PSPIF and PSPIE are reserved on the PIC16C73/73A/76, always maintain these bits clear. 2: The SMP and CKE bits are implemented on the PIC16C76/77 only. All other PIC16C7X devices have these two bits unim- plemented, read as '0' ...
Page 98
... Applicable Devices 72 73 73A 74 74A MODULE IN IDLE_MODE, RCV_MODE OR XMIT_MODE Set interrupt Send ACK = 0; set XMIT_MODE; } else if (R set RCV_MODE; End of transmission; Go back to IDLE_MODE; { PRIOR_ADDR_MATCH = TRUE; Send ACK = 0; while (SSPADD not updated) Hold SCL low; Clear Set RCV_MODE; } 1997 Microchip Technology Inc. ...
Page 99
... Asynchronous mode 1 = High speed Note: For the PIC16C73/73A/74/74A, the asynchronous high speed mode (BRGH = 1) may expe- rience a high rate of receive errors recommended that BRGH = 0. If you desire a higher baud rate than BRGH = 0 can support, refer to the device errata for additional information, or use the PIC16C76/77 ...
Page 100
... Overrun error (Can be cleared by clearing bit CREN overrun error bit 0: RX9D: 9th bit of received data (Can be parity bit) DS30390E-page 100 U-0 R-0 R-0 R-x — FERR OERR RX9D bit0 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ =Value at POR reset 1997 Microchip Technology Inc. ...
Page 101
... This is because the F OSC baud rate error in some cases. Note: For the PIC16C73/73A/74/74A, the asyn- chronous high speed mode (BRGH = 1) may experience a high rate of receive errors recommended that BRGH = 0. If you desire a higher baud rate than ...
Page 102
... MHz SPBRG % value KBAUD ERROR (decimal 1.203 +0.23 92 2.380 -0.83 46 9.322 -2.90 11 18.64 -2. 111 0.437 - 255 32.768 kHz SPBRG SPBRG % value % value ERROR (decimal) KBAUD ERROR (decimal) +0.16 51 0.256 -14.67 +0. -6. 0.512 - - 255 0.0020 - 255 1997 Microchip Technology Inc 255 ...
Page 103
... NA Note: For the PIC16C73/73A/74/74A, the asynchronous high speed mode (BRGH = 1) may experience a high rate of receive errors recommended that BRGH = 0. If you desire a higher baud rate than BRGH = 0 can support, refer to the device errata for additional information, or use the PIC16C76/77. 1997 Microchip Technology Inc. ...
Page 104
... FIGURE 12-4: RX PIN SAMPLING SCHEME, BRGH = 1 (PIC16C73/73A/74/74A) RX pin baud clk x4 clk Q2, Q4 clk FIGURE 12-5: RX PIN SAMPLING SCHEME, BRGH = 1 (PIC16C73/73A/74/74A) RX pin baud clk First falling edge after RX pin goes low x4 clk Q2, Q4 clk DS30390E-page 104 set (i.e., at the high baud rates), the sampling is done on the 3 clock edges preceding the second rising edge after the fi ...
Page 105
... FIGURE 12-6: RX PIN SAMPLING SCHEME, BRGH = 0 OR BRGH = 1 (PIC16C76/77) RX (RC7/RX/DT pin) baud CLK x16 CLK 1997 Microchip Technology Inc. Start bit Baud CLK for all but start bit Samples PIC16C7X Bit0 DS30390E-page 105 ...
Page 106
... TSR register (if the TSR is empty). In such a case, an incorrect ninth data bit maybe loaded in the TSR regis- ter. Data Bus TXREG register 8 MSb LSb (8) 0 TSR register TRMT TX9 TX9D Pin Buffer and Control RC6/TX/CK pin SPEN 1997 Microchip Technology Inc. ...
Page 107
... SPBRG Baud Rate Generator Register Legend unknown unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Transmission. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A/76, always maintain these bits clear. 1997 Microchip Technology Inc 9-bit transmission is desired, then set transmit bit TX9 ...
Page 108
... RSR register MSb Stop (8) Data RX9 Recovery RX9D RCREG register RCIF Interrupt RCIE Start Stop bit7/8 Stop bit bit0 bit7/8 bit bit WORD 2 WORD 1 RCREG RCREG FERR LSb 0 1 Start FIFO 8 Data Bus Start bit Stop bit7/8 bit 1997 Microchip Technology Inc. ...
Page 109
... SPBRG Baud Rate Generator Register Legend unknown unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Reception. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A/76, always maintain these bits clear. 1997 Microchip Technology Inc. 6. Flag bit RCIF will be set when reception is com- plete and an interrupt will be generated if enable bit RCIE was set ...
Page 110
... If interrupts are desired, then set enable bit TXIE 9-bit transmission is desired, then set bit TX9. 5. Enable the transmission by setting bit TXEN 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. 7. Start transmission by loading data to the TXREG register. 1997 Microchip Technology Inc. ...
Page 111
... SPBRG Baud Rate Generator Register Legend unknown unimplemented, read as '0'. Shaded cells are not used for Synchronous Master Transmission. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A/76, always maintain these bits clear. FIGURE 12-12: SYNCHRONOUS TRANSMISSION Q1Q2 Q3Q4 Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2 Q3Q4 ...
Page 112
... Baud Rate Generator Register Legend unknown unimplemented read as '0'. Shaded cells are not used for Synchronous Master Reception. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A/76, always maintain these bits clear. DS30390E-page 112 Steps to follow when setting up a Synchronous Master Reception: 1 ...
Page 113
... RC6/TX/CK pin Write to bit SREN SREN bit '0' CREN bit RCIF bit (interrupt) Read RXREG Note: Timing diagram demonstrates SYNC master mode with bit SREN = '1' and bit BRG = '0'. 1997 Microchip Technology Inc Q4Q1 Q4Q1 Q4Q1 bit1 bit2 bit3 bit4 bit5 PIC16C7X bit6 bit7 ...
Page 114
... RCIE was set. 6. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. 7. Read the 8-bit received data by reading the RCREG register any error occurred, clear the error by clearing bit CREN. 1997 Microchip Technology Inc. ...
Page 115
... SPBRG Baud Rate Generator Register Legend unknown unimplemented read as '0'. Shaded cells are not used for Synchronous Slave Reception. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C73/73A/76, always maintain these bits clear. 1997 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 ...
Page 116
... PIC16C7X NOTES: DS30390E-page 116 1997 Microchip Technology Inc. ...
Page 117
... A/D converter module is operating 0 = A/D converter module is shutoff and consumes no operating current Note 1: A/D channels 5, 6, and 7 are implemented on the PIC16C74/74A/77 only. 1997 Microchip Technology Inc. The A/D converter has a unique feature of being able to operate while the device is in SLEEP mode. To operate in sleep, the A/D conversion clock must be derived from the A/D’ ...
Page 118
... R/W-0 — PCFG2 PCFG1 PCFG0 RA1 RA2 RA5 RA3 RE0 REF REF REF R/W Readable bit W = Writable bit bit0 U = Unimplemented bit, read as ‘0’ Value at POR reset (1) (1) (1) V RE1 RE2 REF RA3 RA3 RA3 D D — 1997 Microchip Technology Inc. ...
Page 119
... FIGURE 13-3: A/D BLOCK DIAGRAM A/D Converter V REF (Reference voltage) Note 1: Not available on PIC16C72/73/73A/76. 1997 Microchip Technology Inc. 3. Wait the required acquisition time. 4. Start conversion: • Set GO/DONE bit (ADCON0) 5. Wait for A/D conversion to complete, by either: • Polling for the GO/DONE bit to be cleared OR • ...
Page 120
... C)(0.05 s/ C)] ACQ 10.747 s + 1.25 s 11.997 Sampling Switch leakage V = 0.6V T 500 has no REF ) is HOLD delay must complete before acqui- AD MINIMUM REQUIRED ACQUISITION TIME + [(Temp - 25 C)(0.05 s/ C)] CAP ( ln(1/511 HOLD = DAC capacitance = 51 Sampling Switch ( k ) 1997 Microchip Technology Inc. ...
Page 121
... For faster conversion times, the selection of another clock source is recommended. 4: When device frequency is greater than 1 MHz, the RC A/D conversion clock source is recommended for sleep operation only. 5: For extended voltage devices (LC), please refer to Electrical Specifications section. 1997 Microchip Technology Inc. 13.3 Configuring Analog Port Pins Applicable Devices 72 73 73A 74 74A 76 77 ...
Page 122
... RC Clock, A/D is on, Channel 0 is selected ; ; Clear A/D interrupt flag bit ; Enable peripheral interrupts ; Enable all interrupts ; Start A/D Conversion ; The ADIF bit will be set and the GO/DONE bit ; is cleared upon completion of the A/D Conversion. wait AD 1997 Microchip Technology Inc. ...
Page 123
... N)( OSC Note 1: PIC16C7X devices have a minimum T 1997 Microchip Technology Inc. Since the T AD user must use some method (a timer, software loop, etc.) to determine when the A/D oscillator may be changed. Example 13-3 shows a comparison of time required for a conversion with 4-bits of resolution, ver- sus the 8-bit resolution conversion ...
Page 124
... V (over DD REF The value that is in the ADRES register is not modified DD for a Power-on Reset. The ADRES register will contain unknown data after a Power-on Reset should be derived from the device oscil kept away from on-chip OSC 1997 Microchip Technology Inc. , ...
Page 125
... The ideal transfer function of the A/D converter is as follows: the first transition occurs when the analog input voltage ( Analog V /256 (Figure 13-5). AIN REF 1997 Microchip Technology Inc. FIGURE 13-5: A/D TRANSFER FUNCTION FFh FEh 04h 03h 02h 01h 00h 13 ...
Page 126
... PORTA Data Direction Register Yes Wait Value on: Value on all Bit 0 POR, other Resets BOR RBIF 0000 000x 0000 000u -0-- 0000 -0-- 0000 xxxx xxxx uuuu uuuu ADON 0000 00-0 0000 00-0 PCFG0 ---- -000 ---- -000 --0x 0000 --0u 0000 RA0 --11 1111 --11 1111 1997 Microchip Technology Inc. ...
Page 127
... TABLE 13-3: SUMMARY OF A/D REGISTERS, PIC16C73/73A/74/74A/76/77 Address Name Bit 7 Bit 6 INTCON GIE PEIE 0Bh,8Bh, 10Bh,18Bh (1) PIR1 PSPIF ADIF 0Ch (1) PIE1 PSPIE ADIE 8Ch PIR2 — — 0Dh PIE2 — — 8Dh ADRES A/D Result Register 1Eh ADCON0 ADCS1 ADCS0 1Fh ADCON1 — ...
Page 128
... PIC16C7X NOTES: DS30390E-page 128 1997 Microchip Technology Inc. ...
Page 129
... It runs off its own RC oscillator for added reliability. There are two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep FIGURE 14-1: CONFIGURATION WORD FOR PIC16C73/74 — — — ...
Page 130
... Ensure the Power-up Timer is enabled anytime Brown-out Reset is enabled. 2: All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed. DS30390E-page 130 — BODEN CP1 CP0 PWRTE WDTE FOSC1 FOSC0 (2) (1) (1) Register: CONFIG Address 2007h bit0 1997 Microchip Technology Inc. ...
Page 131
... Note 1: A series resistor may be required for AT strip cut crystals. FIGURE 14-4: EXTERNAL CLOCK INPUT OPERATION (HS OSC CONFIGURATION) OSC1 Clock from ext. system PIC16CXX Open OSC2 1997 Microchip Technology Inc. TABLE 14-1: Ranges Tested: Mode XT 455 kHz 2.0 MHz 4.0 MHz HS 8.0 MHz 16.0 MHz These values are for design guidance only ...
Page 132
... OSC2/CLKOUT pin, and can be used for test pur- poses or to synchronize other logic (see Figure 3-4 for waveform). FIGURE 14-7: RC OSCILLATOR MODE V DD Rext Cext PIC16CXX V SS CLKIN Fosc/4 for given Rext/ DD values. DD Internal OSC1 clock PIC16CXX OSC2/CLKOUT 1997 Microchip Technology Inc. ...
Page 133
... Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin. 2: Brown-out Reset is implemented on the PIC16C72/73A/74A/76/77. 3: See Table 14-3 and Table 14-4 for time-out situations. 1997 Microchip Technology Inc. A simplified block diagram of the on-chip reset circuit is shown in Figure 14-8. The PIC16C72/73A/74A/76/77 have a MCLR noise fil- ter in the MCLR reset path. The fi ...
Page 134
... The Power-up Timer should always be enabled when Brown-out Reset is enabled. cal brown-out situations < falls below 4.0V (3.8V - 4.2V range) for falls below DD rises above BV . The DD DD drops below DD rises above Figure 14-9 shows typi- BV Max Min Max Min Max Min. DD 1997 Microchip Technology Inc. , ...
Page 135
... Applicable Devices 72 73 73A 74 74A 76 77 The Power Control/Status Register, PCON has up to two bits, depending upon the device. Bit0 is not imple- mented on the PIC16C73 or PIC16C74. time-out Bit0 is Brown-out Reset Status bit, BOR. Bit BOR is unknown on a Power-on Reset. It must then be set by the user and checked on subsequent resets to see if bit BOR cleared, indicating a BOR occurred ...
Page 136
... When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 3: See Table 14-7 for reset value for specific condition. DS30390E-page 136 Program STATUS PCON Counter Register Register PIC16C73/74 000h 0001 1xxx ---- --0- 000h 000u uuuu ---- --u- 000h 0001 0uuu ---- --u- ...
Page 137
... Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 3: See Table 14-7 for reset value for specific condition. 1997 Microchip Technology Inc. Power-on Reset, MCLR Resets Brown-out Reset ...
Page 138
... WDT Reset 0000 0000 0000 0000 --00 0000 --00 0000 0000 -010 0000 -010 0000 0000 0000 0000 ---- -000 ---- -000 - = unimplemented bit, read as '0 value depends on condition Wake-up via WDT or Interrupt uuuu uuuu --uu uuuu uuuu -uuu uuuu uuuu ---- -uuu 1997 Microchip Technology Inc. ...
Page 139
... FIGURE 14-11: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 14-12: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET 1997 Microchip Technology Inc. T PWRT T OST T PWRT T OST ) DD T PWRT T OST PIC16C7X ...
Page 140
... Internal brown-out detection on the PIC16C72/73A/74A/76/77 should be disabled when using this circuit. 3: Resistors should be adjusted for the characteristics of the transistor. PROTECTION CIRCUIT 10k MCLR 40k PIC16CXX DD PROTECTION CIRCUIT MCLR 40k PIC16CXX is below a certain level 0.7V V • 1997 Microchip Technology Inc. ...
Page 141
... Individual interrupt flag bits are set regard- less of the status of their corresponding mask bit or the GIE bit. Note: For the PIC16C73/74 interrupt occurs while the Global Interrupt Enable (GIE) bit is being cleared, the GIE bit may uninten- tionally be re-enabled by the user’s Inter- ...
Page 142
... CCP2IF CCP2IE The following table shows which devices have which interrupts. Device T0IF INTF RBIF PSPIF PIC16C72 Yes Yes Yes PIC16C73 Yes Yes Yes PIC16C73A Yes Yes Yes PIC16C74 Yes Yes Yes PIC16C74A Yes Yes Yes PIC16C76 Yes Yes Yes PIC16C77 ...
Page 143
... The interrupt can be enabled/disabled by setting/clearing enable bit RBIE (INTCON<4>). (Section 5.2) Note: For the PIC16C73/74 change on the I/O pin should occur when the read opera- tion is being executed (start of the Q2 cycle), then the RBIF interrupt flag may not get set. ...
Page 144
... PSA 0 1 MUX WDT Time-out Bit 6 Bit 5 Bit 4 Bit 3 (1) CP1 CP0 BODEN PWRTE INTEDG T0CS T0SE PSA = Min., Temperature = Max., and DD PS2:PS0 To TMR0 (Figure 7-6) PSA Bit 2 Bit 1 Bit 0 (1) WDTE FOSC1 FOSC0 PS2 PS1 PS0 1997 Microchip Technology Inc. ...
Page 145
... Special event trigger (Timer1 in asynchronous mode using an external clock). 8. USART (synchronous slave mode). 1997 Microchip Technology Inc. Other peripherals cannot generate interrupts since dur- ing SLEEP, no on-chip Q clocks are present. When the SLEEP instruction is being executed, the next instruction ( pre-fetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled) ...
Page 146
... PIC16C6X/7X Program- ming Specifications (Literature #DS30228). FIGURE 14-21: TYPICAL IN-CIRCUIT SERIAL External Connector Signals + CLK Data I 0004h 0005h Inst(0004h) Inst(0005h) Dummy cycle Inst(0004h (see programming IL IHH PROGRAMMING CONNECTION To Normal Connections PIC16CXX MCLR/V PP RB6 RB7 Normal Connections 1997 Microchip Technology Inc. ...
Page 147
... Assigned to < > Register bit field In the set of i talics User defined term (font is courier) 1997 Microchip Technology Inc. PIC16C7X The instruction set is highly orthogonal and is grouped into three basic categories: • Byte-oriented operations • Bit-oriented operations • Literal and control operations ...
Page 148
... TO 00 0000 0110 0011 1 C,DC,Z 11 110x kkkk kkkk 1010 kkkk kkkk 1997 Microchip Technology Inc. Notes 1,2 1,2 2 1,2 1,2 1,2,3 1,2 1,2,3 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1,2 1 ...
Page 149
... Q Cycle Activity Decode Read register 'f' Example ADDWF FSR, 0 Before Instruction W = 0x17 FSR = 0xC2 After Instruction W = 0xD9 FSR = 0xC2 1997 Microchip Technology Inc. ANDLW Syntax: Operands: Operation: Status Affected: Encoding: kkkk kkkk Description: . Words: Cycles: Q Cycle Activity Process Write to data W Example ANDWF ...
Page 150
... Q3 Q4 Decode Read Process No- register 'f' data Operation (2nd Cycle No- No- No- No- Operation Operation Operation Operation HERE BTFSC FLAG,1 FALSE GOTO PROCESS_CODE • TRUE • • Before Instruction PC = address HERE After Instruction if FLAG<1> address TRUE if FLAG<1>= address FALSE 1997 Microchip Technology Inc. ...
Page 151
... Operation Operation Example HERE BTFSC FALSE GOTO • TRUE • • Before Instruction PC = address HERE After Instruction if FLAG<1> FLAG<1> 1997 Microchip Technology Inc. CALL Syntax: Operands: Operation: Status Affected: bfff ffff Encoding: Description: instruction. CY Words Cycles: Process No- Q Cycle Activity: data ...
Page 152
... CLRWDT instruction resets the Watch- dog Timer. It also resets the prescaler of the WDT. Status bits TO and PD are set Decode No- Process Clear Operation data WDT Counter CLRWDT Before Instruction WDT counter = ? After Instruction WDT counter = 0x00 WDT prescaler 1997 Microchip Technology Inc. ...
Page 153
... Cycles Cycle Activity Decode Read register 'f' Example DECF CNT, 1 Before Instruction CNT = Z = After Instruction CNT = Z = 1997 Microchip Technology Inc. DECFSZ Syntax: Operands: Operation: Status Affected: dfff ffff Encoding: Description Words: Process Write to data destination Cycles: Q Cycle Activity: 0x13 If Skip: 0x13 0xEC ...
Page 154
... Z 00 1010 dfff ffff The contents of register 'f' are incre- mented the result is placed in the W register the result is placed back in register 'f Decode Read Process Write to register data destination 'f' INCF CNT, 1 Before Instruction CNT = 0xFF After Instruction CNT = 0x00 1997 Microchip Technology Inc. ...
Page 155
... Before Instruction PC = address HERE After Instruction CNT = CNT + 1 if CNT address CONTINUE if CNT address HERE +1 1997 Microchip Technology Inc. IORLW Syntax: Operands: Operation: Status Affected: Encoding: Description: dfff ffff Words: Cycles: Q Cycle Activity: CY Example Q3 Q4 Process Write to data destination ...
Page 156
... After Instruction W = 0x5A Move label ] MOVWF 127 (W) (f) None 00 0000 1fff ffff Move data from W register to register . ' Decode Read Process Write register data register 'f' 'f' MOVWF OPTION_REG Before Instruction OPTION = 0xFF W = 0x4F After Instruction OPTION = 0x4F W = 0x4F 1997 Microchip Technology Inc. ...
Page 157
... PIC16C5X products. Since OPTION is a readable/writable register, the user can directly address it. Words: 1 Cycles: 1 Example To maintain upward compatibility with future PIC16CXX products, do not use this instruction. 1997 Microchip Technology Inc. RETFIE Syntax: Operands: Operation: Status Affected: 0xx0 0000 Encoding: Description ...
Page 158
... Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a two cycle instruction Decode No- No- Pop from Operation Operation the Stack No- No- No- No- Operation Operation Operation Operation RETURN After Interrupt PC = TOS 1997 Microchip Technology Inc. ...
Page 159
... Words: 1 Cycles Cycle Activity Decode Read register 'f' Example RLF REG1,0 Before Instruction REG1 C After Instruction REG1 W C 1997 Microchip Technology Inc. RRF Syntax: Operands: Operation: Status Affected: Encoding: dfff ffff Description: Words: Cycles Cycle Activity: Process Write to data destination Example = 1110 0110 ...
Page 160
... The result is placed in the W register Decode Read Process Write to W literal 'k' data SUBLW 0x02 Before Instruction After Instruction result is positive Before Instruction After Instruction result is zero Before Instruction After Instruction W = 0xFF result is negative 1997 Microchip Technology Inc. ...
Page 161
... Before Instruction REG1 = After Instruction REG1 = 0xFF result is negative 1997 Microchip Technology Inc. SWAPF Syntax: Operands: Operation: Status Affected: dfff ffff Encoding: Description: Words: Cycles Cycle Activity: Process Write to data destination Example TRIS Syntax: Operands: Operation: Status Affected: None Encoding: Description: ...
Page 162
... Exclusive OR the contents of the W register with register 'f the result is stored in the W register the result is stored back in register 'f Decode Read Process Write to register data destination 'f' XORWF REG 1 Before Instruction REG = 0xAF W = 0xB5 After Instruction REG = 0x1A W = 0xB5 1997 Microchip Technology Inc. ...
Page 163
... Microsoft Windows 3.x environment were chosen to best make these fea- tures available to you, the end user compliant version of PICMASTER is available for European Union (EU) countries. 1997 Microchip Technology Inc. 16.3 ICEPIC: Low-cost PIC16CXXX In-Circuit Emulator ICEPIC is a low-cost in-circuit emulator solution for the Microchip PIC16C5X and PIC16CXXX families of 8-bit OTP microcontrollers ...
Page 164
... PICDEM-2 Low-Cost PIC16CXX Demonstration Board The PICDEM simple demonstration board that supports the PIC16C62, PIC16C64, PIC16C65, PIC16C73 and PIC16C74 microcontrollers. All the necessary hardware and software is included to run the basic demonstration programs. The user can program the sample microcontrollers provided with the PICDEM-2 board PRO MATE II pro- grammer or PICSTART-16C, and easily test fi ...
Page 165
... TECH-MP, edition for imple- menting more complex systems. Both versions include Microchip’s fuzzy LAB stration board for hands-on experience with fuzzy logic systems implementation. 1997 Microchip Technology Inc. 16.14 MP-DriveWay Generator MP-DriveWay is an easy-to-use Windows-based Appli- cation Code Generator. With MP-DriveWay you can visually confi ...
Page 166
... PIC16C7X TABLE 16-1: DEVELOPMENT TOOLS FROM MICROCHIP Products Emulator DS30390E-page 166 Tools Software Programmers Boards Demo 1997 Microchip Technology Inc. ...
Page 167
... The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications recommended that the user select the device type that ensures the specifications required. 1997 Microchip Technology Inc. Applicable Devices 72 73 73A 74 74A 76 77 (except V , MCLR, and RA4) ...
Page 168
... Rext in kOhm. measurement. T +125˚C for extended +85˚C for industrial and A T +70˚C for commercial A Conditions = 4 MHz 5.5V (Note MHz 5. 5. 4.0V, WDT enabled 4.0V, WDT disabled + 4.0V, WDT disabled 4.0V, WDT disabled, - +125 and 1997 Microchip Technology Inc. ...
Page 169
... This is not tested. 6: The current is the additional current consumed when this peripheral is enabled. This current should be added to the base 1997 Microchip Technology Inc. Applicable Devices 72 73 73A 74 74A 76 77 Standard Operating Conditions (unless otherwise stated) Operating temperature -40˚C 0˚C Sym Min Typ† ...
Page 170
... For entire V range DD V For entire V range Note1 5V PIN SS A Vss Pin at hi- PIN DD impedance A Vss V V PIN DD A Vss XT, HS and PIN DD LP osc configuration 8.5 mA 4. 7.0 mA 4.5V - +125 1.6 mA 4. 1.2 mA 4.5V - +125 C 1997 Microchip Technology Inc. ...
Page 171
... The leakage current on the MCLR/V levels represent normal operating conditions. Higher leakage current may be measured at different input volt- ages. 3: Negative current is defined as current sourced by the pin. 1997 Microchip Technology Inc. Applicable Devices 72 73 73A 74 74A 76 77 Standard Operating Conditions (unless otherwise stated) Operating temperature -40˚ ...
Page 172
... C specifications only specifications only) T Time osc OSC1 SCK T0CKI t1 T1CKI Period R Rise V Valid Z Hi-impedance High High Low Low SU Setup STO STOP condition Load condition Pin V SS for all pins except OSC2 for OSC2 output 1997 Microchip Technology Inc. ...
Page 173
... All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin. When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices. 1997 Microchip Technology Inc. Applicable Devices 72 73 73A 74 74A 76 77 ...
Page 174
... Max Units Conditions 75 200 ns Note 1 75 200 ns Note 1 35 100 ns Note 1 35 100 ns Note 1 — 0. Note 1 CY — — ns Note 1 — — ns Note 1 50 150 ns — — ns — — ns — — — — — — ns — — ns 1997 Microchip Technology Inc. ...
Page 175
... Brown-out Reset pulse width BOR * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. 1997 Microchip Technology Inc. Applicable Devices 72 73 73A 74 74A ...
Page 176
... N = prescale value (2, 4, ..., 256) — ns Must also meet parameter 47 — ns — ns — ns — ns — ns Must also meet parameter 47 — ns — ns — ns — ns — prescale value ( prescale value ( — ns — ns 200 kHz 7Tosc — 1997 Microchip Technology Inc. ...
Page 177
... TccF CCP1 output fall time * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. 1997 Microchip Technology Inc. Applicable Devices 72 73 73A 74 74A ...
Page 178
... Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30390E-page 178 75 Min — — 10 — — — Typ† Max Units Conditions — — ns — — ns — — ns — — ns — — — — 1997 Microchip Technology Inc. ...
Page 179
... Hold time STOP condition SU STO Setup time STOP condition HD STO Hold time 1997 Microchip Technology Inc. Applicable Devices 72 73 73A 74 74A 76 77 Min Typ Max Units 100 kHz mode 4700 — — ns 400 kHz mode 600 — — 100 kHz mode 4000 — ...
Page 180
... Cb is specifi from 10 to 400 pF s Only relevant for repeated START condition s s After this period the first clock pulse is generated Note Note Time the bus must be free before a new transmission can s start pF 2 C-bus system, but the requirement 1997 Microchip Technology Inc. ...
Page 181
... Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes any such leakage from the A/D module current is from RA3 pin or V REF 1997 Microchip Technology Inc. Applicable Devices 72 73 73A 74 74A 76 77 Min Typ† — ...
Page 182
... LSb (i.e., 20 5.12V) from the last sampled voltage (as stated HOLD — If the A/D clock source is selected as RC, a time added CY before the A/D clock starts. This allows the SLEEP instruction to be executed 1997 Microchip Technology Inc. ...
Page 183
... SS Note 3: PORTD and PORTE are not implemented on the PIC16C73. † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specifi ...
Page 184
... PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 18.1 DC Characteristics: PIC16C73/74-04 (Commercial, Industrial) PIC16C73/74-10 (Commercial, Industrial) PIC16C73/74-20 (Commercial, Industrial) DC CHARACTERISTICS Param Characteristic Sym No. D001 Supply Voltage V D001A D002* RAM Data Retention V Voltage (Note 1) D003 V start voltage ensure internal Power-on Reset signal D004* ...
Page 185
... DD 5: Timer1 oscillator (when enabled) adds approximately the specification. This value is from charac- terization and is for design guidance only. This is not tested. 1997 Microchip Technology Inc. Applicable Devices 72 73 73A 74 74A 76 77 Standard Operating Conditions (unless otherwise stated) Operating temperature -40˚ ...
Page 186
... PIC16C7X Applicable Devices 72 73 73A 74 74A 76 77 18.3 DC Characteristics: PIC16C73/74-04 (Commercial, Industrial) PIC16C73/74-10 (Commercial, Industrial) PIC16C73/74-20 (Commercial, Industrial) PIC16LC73/74-04 (Commercial, Industrial) DC CHARACTERISTICS Param Characteristic No. Input Low Voltage I/O ports D030 with TTL buffer D030A D031 with Schmitt Trigger buffer D032 MCLR, OSC1 (in RC mode) ...
Page 187
... The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. 1997 Microchip Technology Inc. Applicable Devices 72 73 73A 74 74A 76 77 Standard Operating Conditions (unless otherwise stated) Operating temperature -40˚ ...
Page 188
... Load condition Pin 464 for all pins except OSC2, but including PORTD and PORTE outputs as L ports 15 pF for OSC2 output Note: PORTD and PORTE are not implemented on the PIC16C73. DS30390E-page 188 specifications only specifications only) T Time osc OSC1 rd ...
Page 189
... All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin. When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices. 1997 Microchip Technology Inc. Applicable Devices 72 73 73A 74 74A 76 77 ...
Page 190
... DS30390E-page 190 20, 21 Min — — — — — 0.25T + — PIC16C73/74 100 PIC16LC73/74 200 0 PIC16C73/74 — PIC16LC73/74 — PIC16C73/74 — PIC16LC73/74 — OSC new value Typ† Max Units Conditions 75 200 ns Note 1 75 200 ns Note 1 35 100 ns Note 1 35 100 ...
Page 191
... Watchdog Timer Reset * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. 1997 Microchip Technology Inc. PIC16C7X Applicable Devices 72 73 73A 74 74A Min Typ† ...
Page 192
... N = prescale value (2, 4, ..., 256) — ns Must also meet parameter 47 — ns — ns — ns — ns — ns Must also meet parameter 47 — ns — ns — ns — ns — prescale value ( prescale value ( — ns — ns 200 kHz 7Tosc — 1997 Microchip Technology Inc. ...
Page 193
... Applicable Devices 72 73 73A 74 74A Min 0. PIC16C73/74 10 PIC16LC73/ PIC16C73/74 PIC16LC73/ PIC16C73/74 — PIC16LC73/74 — PIC16C73/74 — PIC16LC73/74 — PIC16C7X Typ† Max Units Conditions — — ns — — ns — — ns — — ns — — ns — — ns — — prescale value (1,4 or 16) ...
Page 194
... Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30390E-page 194 65 62 Min Typ† Max Units 20 PIC16C74 20 PIC16LC74 35 — Conditions — — ns — — ns — — ns — — 1997 Microchip Technology Inc. ...
Page 195
... SCK output fall time (master mode) 80 TscH2doV, SDO data output valid after SCK TscL2doV edge † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. 1997 Microchip Technology Inc. Applicable Devices 72 73 73A 74 74A 75 Min T ...
Page 196
... STOP Condition Conditions Only relevant for repeated START condition After this period the first clock pulse is generated 1997 Microchip Technology Inc. ...
Page 197
... SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line T max.+tsu;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I R released. 1997 Microchip Technology Inc. Applicable Devices 72 73 73A 74 74A 76 77 100 101 106 ...
Page 198
... Data in “Typ” column unless otherwise stated. These parameters are for design guidance only and are not tested. DS30390E-page 198 121 Min PIC16C73/74 — PIC16LC73/74 — PIC16C73/74 — PIC16LC73/74 — PIC16C73/74 — PIC16LC73/74 — 125 126 Min Typ† (DT setup time) 15 — (DT hold time) 15 — ...
Page 199
... TABLE 18-13: A/D CONVERTER CHARACTERISTICS: PIC16C73/74-04 (Commercial, Industrial) PIC16C73/74-10 (Commercial, Industrial) PIC16C73/74-20 (Commercial, Industrial) PIC16LC73/74-04 (Commercial, Industrial) Param Sym Characteristic No. A01 N Resolution R A02 E Total Absolute error ABS A03 E Integral linearity error IL A04 E Differential linearity error DL A05 E Full scale error FS A06 E Offset error ...
Page 200
... Note 1: If the A/D clock source is selected as RC, a time of T SLEEP instruction to be executed. TABLE 18-14: A/D CONVERSION REQUIREMENTS Param Sym Characteristic No. 130 T A/D clock period PIC16C73/74 AD PIC16LC73/74 PIC16C73/74 PIC16LC73/74 131 T Conversion time (not including S/H time) CNV (Note 1) 132 T Acquisition time ACQ 134 ...