Z86E40 Zilog, Inc., Z86E40 Datasheet
Z86E40
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Z86E40 Summary of contents
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... On-Chip Oscillator that Accepts a Crystal, Ceramic Resonator, LC, RC, or External Clock Drive For applications demanding powerful I/O capabilities, the Z86E30/E31 have 24 pins, and the Z86E40 has 32 pins of dedicated input and output. These lines are grouped into four ports, eight lines per port, and are configurable under ...
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Z86E30/E31/E40 Z8 4K OTP Microcontroller Power connections follow conventional descriptions be- low: Connection Circuit Power V CC Ground GND Output Input Port 3 Counter/ Timers (2) Interrupt Control Two Analog Comparators Port 2 I/O (Bit Programmable) Figure 1. Z86E30/E31/E40 Functional ...
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Zilog AD 11 MCU MSN Port Port 0 PGM + T est Mode Logic EPM PGM P32 P30 CE XT1 Figure 2. EPROM Programming Block Diagram DS97Z8X0502 11- 0 ...
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Z86E30/E31/E40 Z8 4K OTP Microcontroller PIN IDENTIFICATION R/W 1 P25 P26 P27 P04 P05 P06 P14 P15 40-Pin DIP P07 V CC P16 P17 XTAL2 XTAL1 P31 P32 P33 P34 20 AS Figure 3. 40-Pin DIP Pin Configuration Standard Mode ...
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Zilog Table 2. 44-Pin PLCC Pin Identification Pin # Symbol Function 1–2 GND Ground 3–4 P12–P13 Port 1, Pins 2,3 5 P03 Port 0, Pin 3 6–10 P20–P24 Port 2, Pins 0,1,2,3,4 In/Output 11 DS Data Strobe ...
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Z86E30/E31/E40 Z8 4K OTP Microcontroller PIN IDENTIFICATION (Continued) Table 3. 44-Pin LQFP Pin Identification Table 3. 44-Pin QFP Pin Identification Pin # Symbol Function 1–2 P05–P06 Port 0, Pins 5,6 3–4 P14–P15 Port 1, Pins 4,5 5 P07 Port 0, ...
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Zilog 40-Pin DIP EPM Figure 6. 40-Pin DIP Pin Configuration EPROM Mode DS97Z8X0502 Table 4. 40-Pin DIP ...
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Z86E30/E31/E40 Z8 4K OTP Microcontroller PIN IDENTIFICATION (Continued) Table 5. 44-Pin PLCC Pin Configuration EPROM Programming Mode Pin # Symbol Function 1–2 GND Ground 3– Connection 5 A3 Address 3 6–10 D0–D4 Data 0,1,2,3,4 11– Connection ...
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Zilog Table 6. 44-Pin LQFP Pin Configuration Table 6. 44-Pin QFP Pin Identification EPROM Programming Mode EPROM Programming Mode Pin # Symbol Function 1–2 A5–A6 Address 5,6 3– Connection 5 A7 Address 7 6–7 V Power Supply CC ...
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Z86E30/E31/E40 Z8 4K OTP Microcontroller PIN IDENTIFICATION (Continued) 1 P25 P26 P27 P04 P05 P06 P07 28-Pin DIP V CC XTAL2 XTAL1 P31 P32 P33 P34 14 Figure 9. Standard Mode 28-Pin DIP/SOIC Pin Configuration Table 7. 28-Pin DIP/SOIC/PLCC Pin ...
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Zilog XXX A5 XXX A6 XXX A7 28-Pin PLCC VCC XXX XXX NC XXX CE 11 XXX OE 12 Figure 12. EPROM Programming Mode 28-Pin PLCC Pin Configuration DS97Z8X0502 Pin # Symbol 1–3 D5–D7 4–7 A4–A7 26 ...
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Z86E30/E31/E40 Z8 4K OTP Microcontroller ABSOLUTE MAXIMUM RATINGS Parameter Ambient Temperature under Bias Storage Temperature Voltage on any Pin with Respect to V Voltage on V Pin with Respect Voltage on XTAL1 and RESET Pins with Respect ...
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Zilog CAPACITANCE GND = 0V 1.0 MHz; unmeasured pins returned to GND Parameter Min Input capacitance 0 Output capacitance 0 I/O capacitance 0 DC ELECTRICAL CHARACTERISTICS Sym Parameter V Clock ...
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... STD Mode (not Low EMI Mode) 9. Auto Latch (mask option) selected 10. For analog comparator inputs when analog comparators are enabled. 11. Clock must be forced Low, when XTAL1 is clock driven and XTAL2 is floating. 12. Typicals are 5.0V and 13. Z86E40 only 14. WDT running + Note [3] Min Max 3 ...
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Zilog V Sym Parameter Note [3] V Clock Input High 4.5V CH Voltage 5.5V V Clock Input Low 4.5V CL Voltage 5.5V V Input High Voltage 4.5V IH 5.5V V Input Low Voltage 4.5V IL 5.5V V Output High 4.5V ...
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... STD Mode (not Low EMI Mode) 9. Auto Latch (mask option) selected 10. For analog comparator inputs when analog comparators are enabled. 11. Clock must be forced Low, when XTAL1 is clock driven and XTAL2 is floating. 12. Typicals are 5.0V CC 13. Z86E40 only 14. WDT is not running =– +105 Min Max -1 ...
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... Zilog R Port 0 18 Port (Read) Port1 rite) Figure 14. External I/O or Memory Read/Write Timing DS97Z8X0502 OUT 14 Z86E40 Only Z86E30/E31/E40 Z8 4K OTP Microcontroller ...
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Z86E30/E31/E40 Z8 4K OTP Microcontroller DC ELECTRICAL CHARACTERISTICS (Continued) No Symbol Parameter 1 TdA(AS) Address Valid to AS Rise Delay 2 TdAS(A) AS Rise to Address Float Delay 3 TdAS(DR) AS Rise to Read Data Req’d Valid 4 TwAS AS ...
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Zilog No Symbol Parameter 1 TdA(AS) Address Valid to AS Rise Delay 2 TdAS(A) ASAS Rise to Address Float Delay 3 TdAS(DR) AS Rise to Read Data Req’d Valid 4 TwAS AS Low Width 5 TdAS(DS) Address Float to DS ...
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Z86E30/E31/E40 Z8 4K OTP Microcontroller DC ELECTRICAL CHARACTERISTICS (Continued) Clock 7 7 TIN 4 IRQN 8 Clock Setup Stop Mode Recovery Source Figure 15. Additional Timing Diagram P R ...
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Zilog Additional Timing Table (Divide-By-One Mode) No Symbol Parameter 1 TpC Input Clock Period 2 TrC,TfC Clock Input Rise & Fall Times 3 TwC Input Clock Width 4 TwTinL Timer Input Low Width 5 TwTinH Timer Input High Width 6 ...
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Z86E30/E31/E40 Z8 4K OTP Microcontroller DC ELECTRICAL CHARACTERISTICS (Continued) Handshake Timing Diagrams Data In Valid Data (Input) RDY (Output) Data Out 7 DAV (Output) RDY (Input Delayed DAV 4 Figure 16. Input Handshake ...
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Zilog Additional Timing Table No Symbol Parameter 1 TpC Input Clock Period 2 TrC,TfC Clock Input Rise & Fall Times 3 TwC Input Clock Width 4 TwTinL Timer Input Low Width 5 TwTinH Timer Input High Width 6 TpTin Timer ...
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... After the POR time, RESET is a Schmitt-triggered input. To avoid asynchronous and noisy reset problems, the Z86E40 is equipped with a reset filter of four external clocks (4TpC). If the external reset signal is less than 4TpC in duration, no reset occurs. On the fifth clock after the re- ...
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Zilog Port 0 (P07–P00). Port 8-bit, bidirectional, CMOS- compatible I/O port. These eight I/O lines can be config- ured under software control as a nibble I/O port address port for interfacing external memory. The ...
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... Address/Data mode. If more than 256 external locations are required, Port 0 outputs the additional lines (Figure 19). Port 1 can be placed in the high-impedance state along with Port 0, AS, DS, and R/W, allowing the Z86E40 to share common resources in multiprocessor and DMA ap- plications. Port 2 (I/O) MCU ...
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... I/O port. These eight I/O lines can be config- ured under software control as an input or output, indepen- dently. All input buffers are Schmitt-triggered. Bits pro- grammed as outputs can be globally programmed as either push-pull or open-drain. Low EMI output buffers can Z86E40 Open-Drain OEN Out TTL Level Shifter ...
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Z86E30/E31/E40 Z8 4K OTP Microcontroller PIN FUNCTIONS (Continued) Port 3 (P37–P30). Port 8-bit, CMOS-compatible port with four fixed inputs (P33–P30) and four fixed outputs (P37–P34). These eight lines can be configured by soft- ware for interrupt and ...
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... I/O CTC1 P30 IN P31 P32 IN P33 IN P34 OUT P35 OUT P36 OUT T OUT P37 OUT DS97Z8X0502 Z86E40 Port 3 MCU (I/O or Control) Auto Latch R 500 K R247 = P3M 1 = Analog Digital DIG Figure 21. Port 3 Configuration Table 9. Port 3 Pin Assignments Analog Interrupt P0 HS IRQ3 ...
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... Auto Latches are available on Port 0, Port 2, and P30. There are no Auto Latches on P31, P32, and P33. Low EMI Emission. The Z86E40 can be programmed to operate in a low EMI Emission Mode in the PCON register. The oscillator and all I/O ports can be programmed as low EMI emission mode independently ...
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... EPROM. After reset, the program counter points at the address 000CH, which is the starting address of the user program. In ROMless mode, the Z86E40 can address External Program Memory. The ROM/ROMless option is only available on the 44-pin devices. EPROM ...
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... FUNCTIONAL DESCRIPTION (Continued) Data Memory (DM). In EPROM Mode, the Z86E40 can address external data memory beginning at location 4096. In ROMless mode, the Z86E40 can address data memory. External data memory may be included with, or separated from, the external program memory space. DM, an optional I/O function that can be ...
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Zilog Register File. The register file consists of three I/O port registers, 236/125 general-purpose registers, 15 control and status registers, and three system configuration regis- ters in the expanded register group. The instructions can access registers directly or indirectly through ...
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Z86E30/E31/E40 Z8 4K OTP Microcontroller FUNCTIONAL DESCRIPTION (Continued The upper nibble of the register file address provided by the register pointer specifies the active working-register group. FF Register Group F F0 ...
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... Group Pointer Z8 Reg. File %FF %FO Z86E30/E40 Only Z86E30/E40 Only %7F %0F %00 Notes Unknown † For Z86E40 (ROMless) reset condition: "10110110" * Will not be reset with a STOP Mode Recovery ** Will not be reset with a STOP Mode Recovery, except Bit D0. Figure 26. Expanded Register File Architecture DS97Z8X0502 REGISTER % ...
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... RAM protect by loading respectively. A “1” indicates RAM Protect enabled. RAM Protect is not available on the Z86E31. Stack. The Z86E40 external data memory or the internal register file can be used for the stack. The 16-bit Stack Pointer (R254–R255) is used for the external stack, which can reside anywhere in the data memory for ROMless mode, but only from 4096 to 65535 in ROM mode ...
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Zilog OSC D1 (SMR (SMR) 16 Internal Clock External Clock Clock Logic 4 Internal Clock Gated Clock Triggered Clock TIN P31 DS97Z8X0502 Internal Data Bus Write Write PRE0 Initial Value Register 6-Bit 4 Down Counter 6-Bit Down Counter ...
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Z86E30/E31/E40 Z8 4K OTP Microcontroller FUNCTIONAL DESCRIPTION (Continued) Interrupts. The MCU has six different interrupts from six different sources. The interrupts are maskable and priori- tized (Figure 28). The six sources are divided as follows: four sources are claimed by ...
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Zilog When more than one interrupt is pending, priorities are re- solved by a programmable priority encoder that is con- trolled by the Interrupt Priority Register (IPR). An interrupt machine cycle is activated when an interrupt request is granted. Thus, ...
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Z86E30/E31/E40 Z8 4K OTP Microcontroller FUNCTIONAL DESCRIPTION (Continued) Power-On Reset (POR). A timer circuit clocked by a ded- icated on-board RC oscillator is used for the Power-On Re- set (POR) timer function. The POR timer allows V the oscillator circuit ...
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Zilog Comparator Output Port 3 (D0). Bit 0 controls the com- parator output in Port 3. A “1” in this location brings the comparator outputs to P34 and P37, and a “0” releases the Port to its standard I/O configuration. ...
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Z86E30/E31/E40 Z8 4K OTP Microcontroller FUNCTIONAL DESCRIPTION (Continued) SMR ( Default setting after RESET. ** Default setting after RESET and STOP-Mode Recovery. 42 SCLK/TCLK Divide OFF 1 ...
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Zilog SCLK/TCLK Divide-by-16 Select (D0). This bit of the SMR controls a divide-by-16 prescaler of SCLK/TCLK. The purpose of this control is to selectively reduce device power consumption during normal processor execution (SCLK control) and/or HALT mode (where TCLK sources ...
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Z86E30/E31/E40 Z8 4K OTP Microcontroller FUNCTIONAL DESCRIPTION (Continued) Table 12. Stop-Mode Recovery Source SMR Source selection POR recovery only P30 transition P31 transition (Not in analog mode) 0 ...
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Zilog cycles from the execution of the first instruction after Power-On Reset, Watch-Dog reset or a STOP-Mode Recovery (Figures 33 and 34). After this point, the register cannot be modified by any means, intentional or WDTMR ( ...
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Z86E30/E31/E40 Z8 4K OTP Microcontroller FUNCTIONAL DESCRIPTION (Continued) Reset 4 Clock Filter WDT Select (WDTMR) CLK Source Select (WDTMR) XTAL Internal RC OSC. + VDD VLV - WDT From Stop Mode Recovery Source Stop Delay Select (SMR) 46 Clear 18 ...
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... CC operation of the device. Reset is globally driven if V below V (Figure 35). LV 3.7 VCC (Volts) 3.5 3.3 3.1 2.9 2.7 2.5 2.3 -60 Figure 35. Typical Z86E40 V DS97Z8X0502 Note the minimum Power-On Reset time-out ( -40 - Voltage vs. Temperature Z86E30/E31/E40 Z8 4K OTP Microcontroller ...
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... Table 14 shows the programming voltages of each pro- gramming mode. Table 15, and figures that follow show the programming timing of each programming mode. Fig- ure 38 shows the circuit diagram of a Z86E40 program- ming adapter, which adapts from 2764A to Z86E40 and Figure 39 shows the Z86E30/E31 Programming Adapter Circuitry ...
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Zilog Programming V Modes PP EPROM READ1 X EPROM READ2 X PROGRAM V PP PROGRAM V PP VERIFY OPTION BIT PGM V PP OPTION BIT READ X Notes 13 per specific ...
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Z86E30/E31/E40 Z8 4K OTP Microcontroller FUNCTIONAL DESCRIPTION (Continued) VIH Address VIL VIH Data VIL VH VPP VIL VH EPM VIL V CC 4.5V VIH CE VIL VIH OE VIL VIH PGM VIL 50 Address Stable 16 Invalid Valid Invalid 9 ...
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... Zilog Z86E40 TIMING DIAGRAMS V IH Address Data EPM 4. PGM V IL Figure 37. Timing Diagram of EPROM Program and Verify Modes DS97Z8X0502 Address Stable 1 Data Stable Program Cycle Z86E30/E31/E40 Z8 4K OTP Microcontroller Data Out Valid Verify Cycle 1 51 ...
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... A7 P37 P07 XTAL1 GND 14 21 RESET XTAL2 Z86E40 40-Pin DIP Socket 12. GND 4 X3 VCC 15 IX1 IX2 X IH5043 Figure 38. Z86E40 Z8 OTP Programming Adapter 52 EPM KOhm 1 A10 R1 1 KOhm A11 1 GND 12. EPM GND 5.0 V VCC For use with Standard EPROM Programmers ...
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Zilog P20 25 D1 P21 D2 26 P22 D3 27 P23 D4 28 P24 D5 1 P25 D6 2 P26 D7 3 P27 P30 P00 P31 P01 P32 ...
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... Duration No Increment Last Addr ? Address Yes Vcc = Vpp = 4.5V * Verify All Bytes Pass Vcc = Vpp = 5.5V * Verify All Bytes Pass Device Passed Figure 40. Z86E40 Programming Algorithm Z86E30/E31/E40 Z8 4K OTP Microcontroller Yes Fail Verify Byte Pass Fail Device Failed Fail 1 55 ...
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Z86E30/E31/E40 Z8 4K OTP Microcontroller EXPANDED REGISTER FILE CONTROL REGISTERS PCON (FH) 00H Default Setting After Reset † Must Be 1 for Z86E30/E31 Figure 41. Port Configuration Register Write Only SMR ...
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Zilog Z8 CONTROL REGISTER DIAGRAMS R240 Figure 45. Reserved R241 TMR Default After Reset = 00H Figure 46. Timer Mode Register F1H: Read/Write R242 ...
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Z86E30/E31/E40 Z8 4K OTP Microcontroller Z8 CONTROL REGISTER DIAGRAMS (Continued) R246 P2M Default After Reset Figure 51. Port 2 Mode Register F6H: Write Only R247 P3M ...
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... Zero Flag Carry Flag Z86E30/E31/E40 Z8 4K OTP Microcontroller Expanded Register File Working Register Pointer Figure 58. Register Pointer FDH: Read/Write (Z86E40) Stack Pointer Upper Byte (SP8 - SP15) (Z86E30/E31 State State Figure 59. Stack Pointer High FEH: Read/Write Stack Pointer Lower Byte (SP0 - SP7) Figure 60 ...
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Z86E30/E31/E40 Z8 4K OTP Microcontroller PACKAGE INFORMATION (Continued) PACKAGE INFORMATION 60 Figure 61. 40-Pin DIP Package Diagram Zilog DS97Z8X0502 ...
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Zilog DS97Z8X0502 Figure 62. 44-Pin PLCC Package Diagram Figure 63. 44-Pin LQFP Package Diagram Figure 63. 44-Pin QFP Package Diagram Z86E30/E31/E40 Z8 4K OTP Microcontroller 1 61 ...
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Z86E30/E31/E40 Z8 4K OTP Microcontroller 62 Figure 64. 28-Pin DIP Package Diagram Figure 65. 28-Pin SOIC Package Diagram Zilog DS97Z8X0502 ...
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Zilog DS97Z8X0502 Figure 66. 28-Pin PLCC Package Diagram Z86E30/E31/E40 Z8 4K OTP Microcontroller 1 63 ...
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... LQFP 44-Pin QFP Z86E4016FSC Z86E4016FEC 28-Pin PLCC Z86E3016VSC Z86E3016VEC 28-Pin PLCC Z86E3116VSC Z86E3116VEC Temperature + - +105 C Speed MHz Environmental C= Plastic Standard E = Hermetic Standard is a Z86E40, 16 MHz, DIP +70 C, Plastic Standard Flow Environmental Flow T emperature Package Speed Product Number Zilog Prefix Zilog DS97Z8X0502 ...
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