CDP1852E Intersil Corporation, CDP1852E Datasheet

CDP1852E

Manufacturer Part Number

CDP1852E

Description

Byte-Wide Input/Output Port

Manufacturer

Intersil Corporation

Datasheet

1.CDP1852E.pdf (9 pages)

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Meier Automation Equipment Co., Limited

Part Number:

CDP1852E

Manufacturer:

HARRIS

Quantity:

20 000

Current page: 1 of 9
Download datasheet (154Kb)

March 1997

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 321-724-7143

Features

• Static Silicon-Gate CMOS Circuitry

• Parallel 8-Bit Data Register and Buffer

• Handshaking Via Service Request Flip-Flop

• Low Quiescent and Operating Power

• Interfaces Directly with CDP1800-Series

• Single Voltage Supply

• Full Military Temperature Range (-55

Ordering Information

Pinout

PDIP

SBDIP

CSI/CSI

CLOCK

PACKAGE TEMP. RANGE

MODE

Microprocessors

DO0

DO1

DO2

DO3

DI0

DI1

DI2

DI3

24 LEAD DIP

TOP VIEW

-40

C to +85

Intersil (and design) is a trademark of Intersil Americas Inc.

C CDP1852CE CDP1852E E24.6

C CDP1852CD CDP1852D D24.6

SR/SR

DI7

DO7

DI6

DO6

DI5

DO5

DI4

DO4

CLEAR

CS2

Typical CDP1802 Microprocessor System

ROM

C to +125

10V

ADDR BUS

TPA

MRD

CEO

PKG.

NO.

RAM

BIDIRECTIONAL DATA BUS

ADDR BUS

Description

The CDP1852 and CDP1852C are parallel, 8-bit, mode-pro-

grammable input/output ports. They are compatible and will

interface directly with CDP1800-series microprocessors. They

are also useful as 8-bit address latches when used with the

CDP1800 multiplexed address bus and as I/O ports in general-

purpose applications.

The mode control is used to program the device as an input port

(mode = 0) or as an output port (mode = 1). The SR/SR output

can be used as a signal to indicate when data is ready to be

transferred. In the input mode, a peripheral device can strobe

data into the CDP1852, and microprocessor can read that data

by device selection. In the output mode, a microprocessor

strobes data into the CDP1852, and handshaking is established

with a peripheral device when the CDP1852 is deselected.

In the input mode, data at the data-in terminals (DI0-DI7) is

strobed into the port’s 8-bit register by a high (1) level on the

clock line. The negative high-to-low transition of the clock

latches the data in the register and sets the service request out-

put low (SR/SR = 0). When CS1/CS1 and CS2 are high

(CS1/CS1 and CS2 = 1), the three-state output drivers are

enabled and data in the 8-bit register appear at the data-out ter-

minals (D00-D07). When either CS1/CS1 or CS2 goes low

(CS1/CS1 or CS2 = 0), the data-out terminals are three-stated

and the service request output returns high (SR/SR =1).

In the output mode, the output drivers are enabled at all times.

Data at the data-in terminals (DI0-DI7) is strobed into the 8-bit

clock are high (1), and are present at the data-out terminals

(D00-D07). The negative high-to-low transition of the clock

latches the data in the register. The SR/SR output goes high

(SR/SR = 1) when the device is deselected (CS1/CS1 = 1 or

CS2 = 0) and returns low (SR/SR = 0) on the following trailing

edge of the clock.

MWR

MRD

TPA

CDP1802

FIGURE 1.

CPU

Byte-Wide Input/Output Port

DMA - IN DMA - OUT

N0 - N2 MRD

INTERRUPT

CDP1852C

EF1 - EF4

SC0 SC1

TPB

CDP1852,

CDP1852

File Number

I/O

CONTROL

DATA

1166.2

Related parts for CDP1852E

CDP1852E Summary of contents

Page 1

... Low Quiescent and Operating Power • Interfaces Directly with CDP1800-Series Microprocessors • Single Voltage Supply • Full Military Temperature Range (-55 Ordering Information PACKAGE TEMP. RANGE PDIP - +85 C CDP1852CE CDP1852E E24 SBDIP - +85 C CDP1852CD CDP1852D D24.6 Pinout 24 LEAD DIP TOP VIEW CSI/CSI 1 24 ...

Page 2

Absolute Maximum Ratings DC Supply-voltage Range (Voltage Referenced to V Terminal) SS CDP1852 . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 3

Logic Diagram 13 CS2 1 CS1/CS1 MODE 2 14 CLEAR CLOCK 11 DI0 3 5 DI1 22 DI7 Static Electrical Specifications At T PARAMETER Quiescent Device Current I DD Output Low Drive I OL (Sink) Current Output High Drive I ...

Page 4

Static Electrical Specifications At T PARAMETER Output Voltage High Level V OH (Note 2) Input Low Voltage V IL Input High Voltage V lH Input Leakage Current I lN Three-State Output Leakage I OUT Current Operating Current (Note 3) I ...

Page 5

Dynamic Electrical Specifications PARAMETER Minimum Data Setup Time Minimum Data Hold Time Data Out Hold Time (Note 2) Propagation Delay Times PLH PHL Select to Data Out (Note 2) Clear to SR Clock to SR Select to ...

Page 6

CS1 - CS2 (NOTE 1) CLOCK t DATA IN DATA BUS SR t RSR CLEAR t CLR NOTE 1. CS1 CS2 is the overlap of CS1 = 1 and CS2 = 1. MODE 0 TRUTH TABLE CLOCK † CS1-CS2 CLEAR ...

Page 7

Dynamic Electrical Specifications PARAMETER MODE 1- OUTPUT PORT (See Figure 6) Minimum Clock Pulse Width Minimum Write Pulse Width Minimum Clear Pulse Width Minimum Data Setup Time Minimum Data Hold Time Minimum Select-After-Clock Hold Time Propagation Delay Times ...

Page 8

CS1 CS2 (NOTE 1) CLOCK DATA IN t RDO DATA OUT t SR RSR t CLR CLEAR NOTES 1. CS1 CS2 is the overlap of CS1 0 and CS2 = 1. 2. Write is the overlap of CS1 CS2 and ...

Page 9

... Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use ...

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