MCM67M518FN11 Motorola, MCM67M518FN11 Datasheet

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MCM67M518FN11

Manufacturer Part Number
MCM67M518FN11
Description
32K x 18 bit burstRAM synchronous fast static RAM
Manufacturer
Motorola
Datasheet

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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
32K x 18 Bit BurstRAM
Synchronous Fast Static RAM
With Burst Counter and Self–Timed Write
designed to provide a burstable, high–performance, secondary cache for the
MC68040 and PowerPC microprocessors. It is organized as 32,768 words of
18 bits, fabricated using Motorola’s high–performance silicon–gate BiCMOS
technology. The device integrates input registers, a 2–bit counter, high speed
SRAM, and high drive capability outputs onto a single monolithic circuit for
reduced parts count implementation of cache data RAM applications. Synchro-
nous design allows precise cycle control with the use of an external clock (K).
BiCMOS circuitry reduces the overall power consumption of the integrated
functions for greater reliability.
except output enable (G), are clock (K) controlled through positive–edge–trig-
gered noninverting registers.
start cache controller (TSC) input pins. Subsequent burst addresses are gen-
erated internally by the MCM67M518 (burst sequence imitates that of the
MC68040 and PowerPC) and controlled by the burst address advance (BAA) in-
put pin. The following pages provide more detailed information on burst controls.
clock (K) input. This feature eliminates complex off–chip write pulse generation
and provides increased flexibility for incoming signals.
bytes. LW controls DQ0 – DQ8 (the lower bits), while UW controls DQ9 – DQ17
(the upper bits).
cache memory.
BurstRAM is a trademark of Motorola, Inc.
PowerPC is a trademark of IBM Corp.
MOTOROLA FAST SRAM
REV 3
5/95
The MCM67M518 is a 589,824 bit synchronous static random access memory
Addresses (A0 – A14), data inputs (DQ0 – DQ17), and all control signals,
Bursts can be initiated with either transfer start processor (TSP) or transfer
Write cycles are internally self–timed and are initiated by the rising edge of the
Dual write enables (LW and UW) are provided to allow individually writeable
This device is ideally suited for systems that require wide data bus widths and
Motorola, Inc. 1994
Single 5 V
Fast Access Times: 9/11/14 ns Max and
Cycle Times: 12.5/15/20 ns Min
Byte Writeable via Dual Write Strobes
Internal Input Registers (Address, Data, Control)
Internally Self–Timed Write Cycle
TSP, TSC, and BAA Burst Control Pins
Asynchronous Output Enable Controlled Three–State Outputs
Common Data Inputs and Data Outputs
High Board Density 52–PLCC Package
3.3 V I/O Compatible
5% Power Supply
DQ12
DQ13
DQ14
DQ15
DQ16
DQ10
DQ11
DQ17
DQ9
V CC
V CC
V SS
V SS
A0 – A14
K
BAA
LW
UW
TSP, TSC
E
G
DQ0 – DQ17
V CC
V SS
NC
All power supply and ground pins must be
connected for proper operation of the device.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . .
8
9
10
11
12
13
14
15
16
17
18
19
20
. . . . . . . . . . . . . . . . . . . . . .
21 22 23 24 25 26 27 28 29 30 31 32 33
7 6 5 4 3 2 1 52 51 50 49 48 47
. . . . . . . . . . . .
. . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . .
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. . . . . . . . . . . . . . . . . . . . . . . . . .
MCM67M518
. . . . . . . . . . . . . . . .
PIN ASSIGNMENT
. . . . . . . . . . . . . . . .
. . . . . . . . . .
PIN NAMES
FN PACKAGE
CASE 778–02
PLASTIC
Lower Byte Write Enable
Upper Byte Write Enable
Burst Address Advance
Order this document
+ 5 V Power Supply
by MCM67M518/D
Data Input/Output
MCM67M518
Address Inputs
No Connection
Output Enable
Transfer Start
Chip Enable
Ground
Clock
46
45
44
43
42
41
40
39
38
37
36
35
34
1
DQ8
DQ7
DQ6
V CC
V SS
DQ5
DQ4
DQ3
DQ2
V SS
V CC
DQ1
DQ0

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MCM67M518FN11 Summary of contents

Page 1

... MC68040 and PowerPC microprocessors organized as 32,768 words of 18 bits, fabricated using Motorola’s high–performance silicon–gate BiCMOS technology. The device integrates input registers, a 2–bit counter, high speed SRAM, and high drive capability outputs onto a single monolithic circuit for reduced parts count implementation of cache data RAM applications ...

Page 2

... NOTE: The external two values for A1 and A0 provide the starting point for the burst sequence graph. The burst logic ad- vances A1 and A0 as shown above. INTERNAL ADDRESS A0 32K MEMORY A1 ARRAY – A14 9 18 DATA–IN REGISTERS OUTPUT BUFFER 9 9 MOTOROLA FAST SRAM 9 ...

Page 3

... Operating Temperature Storage Temperature NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPER- ATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. MOTOROLA FAST SRAM Address X L–H ...

Page 4

... Min Max Unit V CC 4. 0.3 – 0.5* 0.8 V 20.0 mA. Symbol Min Max Unit I lkg(I) — 1.0 I lkg(O) — 1.0 I CCA9 — 290 mA I CCA11 275 I CCA14 250 I SB1 — — 0 2.4 3.3 V Symbol Typ Max Unit I MOTOROLA FAST SRAM A A ...

Page 5

... TSP or TSC are low and the chip is selected. All other synchronous inputs must meet the specified setup and hold times for ALL rising edges of K when the chip is selected. Chip enable must be valid at each rising edge of clock for the device (when TSP or TSC is low) to remain enabled. OUTPUT Figure 1A MOTOROLA FAST SRAM Unless Otherwise Noted) 1.5 V Output Timing Reference Level 0 to 3.0 V Output Load ...

Page 6

... MCM67M518 6 MOTOROLA FAST SRAM ...

Page 7

... MOTOROLA FAST SRAM MCM67M518 7 ...

Page 8

... TSVKH t KHTSX TSP t AVKH t KHAX ADDRESS A1 LW, UW BAA G t KHQV DATA IN t KHQX1 DATA OUT READ MCM67M518 8 t KHKH t KHKL t KLKH WVKH t KHWX t BAVKH t KHBAX t DVKH t KHDX D(A2) t GHQZ t GLQX Q(A1) WRITE t GLQV t KHQX2 Q(A3 BURST READ MOTOROLA FAST SRAM ...

Page 9

... DATA ADDRESS MPC604 (PowerPC ) SYSCLK TS CONTROL Using Four MCM67M518FN11s with a 66 MHz (bus speed) MPC604 PowerPC MOTOROLA FAST SRAM APPLICATION EXAMPLE ADDRESS BUS CLOCK ADDR K CACHE CONTROL LOGIC 256K Byte Burstable, Secondary Cache DATA BUS ADDR DATA K G MCM67M518FN11 TSC W BAA ...

Page 10

... Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc Equal Opportunity/Affirmative Action Employer. MCM67M518 10 ORDERING INFORMATION (Order by Full Part Number) MCM 67M518 XX XX Speed ( ns ns ns) Package (FN = PLCC) MCM67M518FN11 MCM67M518FN14 MOTOROLA FAST SRAM ...

Page 11

... DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635). MOTOROLA FAST SRAM PACKAGE DIMENSIONS FN PACKAGE 52–LEAD PLCC CASE 778–02 B ...

Page 12

... USA/EUROPE: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. JAPAN: Nippon Motorola Ltd.; 4–32–1, Nishi–Gotanda, Shinagawa–ku, Tokyo 141, Japan. ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Center, No. 2 Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong. CODELINE TO BE PLACED HERE ...

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