DS2153Q Dallas Semiconductor, DS2153Q Datasheet
DS2153Q
Available stocks
Related parts for DS2153Q
DS2153Q Summary of contents
Page 1
... CMOS Industrial grade version (– +85 C) available (DS2153QN) DESCRIPTION The DS2153Q T1 Single–Chip Transceiver (SCT) con- tains all of the necessary functions for connection to E1 lines. The onboard clock/data recovery circuitry coverts the AMI/HDB3 E1 waveforms to a NRZ serial stream. ...
Page 2
... E1 transmission. Once the data stream has been prepared for transmission sent via the jitter attenuation mux to the waveshaping and line driver functions. The DS2153Q will drive the E1 line from the TTIP and TRING pins via a coupling trans- former. ...
Page 3
... DS2153Q BLOCK DIAGRAM Figure 1–1 FAS Word Insertion Si Bit Insertion Signaling Extraction E Bit Insertion Sa Bit Insertion FAS Error Count Signaling Insertion E Bit Count CRC4 Error Count Idle Code Insertion Alarm Detection CRC4 Generation Synchronizer HDB3 Encode BPV Counter AIS Generation HDB3 Decoder ...
Page 4
... DS2153Q PIN DESCRIPTION Table 1–1 PIN SYMBOL TYPE 1 AD4 I/O 2 AD5 3 AD6 4 AD7 5 RD(DS ALE(AS) 8 WR(R/W) 9 RLINK O 10 RLCLK O 11 DVSS – 12 RCLK O 13 RCHCLK O 14 RSER O 15 RSYNC I/O 16 RLOS/LOTC O 17 SYSCLK 18 RCHBLK O 19 ACLKI 022697 4/48 Address/Data Bus. A 8–bit multiplexed address/data bus. ...
Page 5
... TCLK to insert the Sa bits See Section 13 for timing details. Transmit Sync. A pulse at this pin will establish either frame or multiframe boundaries for the DS2153Q. Via TCR1.1, the DS2153Q can be pro- grammed to output either a frame or multiframe pulse at this pin. See Section 13 for timing details. ...
Page 6
... DS2153Q PIN SYMBOL TYPE 40 TCHCLK O 41 AD0 I/O 42 AD1 43 AD2 44 AD3 DS2153Q REGISTER MAP ADDRESS R/W REGISTER NAME 00 R BPV or Code Violation Count BPV or Code Violation Count CRC4 Count 1/FAS Error Count CRC4 Error Count E–Bit Count 1/FAS Error Count E– ...
Page 7
... RD transitions high in Intel timing tran- sitions low in Motorola timing. 3.0 CONTROL AND TEST REGISTERS The operation of the DS2153Q is configured via a set of seven registers. Typically, the control registers are only accessed when the system is first powered up. Once the DS2153Q has been initialized, the control registers will only need to be accessed when there is a change in the system configuration ...
Page 8
... DS2153Q RCR1: RECEIVE CONTROL REGISTER 1 (Address=10 Hex) (MSB) RSMF RSM SYMBOL POSITION RSMF RCR1.7 RSM RCR1.6 RSIO RCR1.5 – RCR1.4 – RCR1.3 FRC RCR1.2 SYNCE RCR1.1 RESYNC RCR1.0 SYNC/RESYNC CRITERIA Table 3–1 FRAME OR MULTIFRAME SYNC CRITERIA LEVEL FAS FAS present in frames N and and FAS not present in frame ...
Page 9
... TPOS and TNEG Transmit International Bit Select. 0=sample Si bits at TSER pin 1=source Si bits from TAF and TNAF registers (in this mode, TCR1.6 must be set to 0) (LSB) RSCLKM RESE (LSB) TSA1 TSM TSIO 022697 9/48 DS2153Q – ...
Page 10
... DS2153Q TSA1 TCR1.2 TSM TCR1.1 TSIO TCR1.0 Note: See Figure 13–9 for more details about how the Transmit Control Registers affect the operation of the DS2153Q. TCR2: TRANSMIT CONTROL REGISTER 2 (Address=13 Hex) (MSB) Sa8S Sa7S SYMBOL POSITION Sa8S TCR2.7 Sa7S TCR2.6 Sa6S TCR2 ...
Page 11
... CCR1.1 RCRC4 CCR1.0 FRAMER LOOPBACK When CCR1.7 is set to a one, the DS2153Q will enter a Framer LoopBack (FLB) mode. This loopback is useful in testing and debugging applications. In FLB, the DS2153Q will loop data from the transmit side back to the receive side. When FLB is enabled, the following ...
Page 12
... CCR2.1 LLB CCR2.0 REMOTE LOOPBACK When CCR2.1 is set to a one, the DS2153Q will be forced into Remote LoopBack (RLB). In this loopback, data recovered off of the E1 line from the RTIP and RRING pins will be transmitted back onto the E1 line (with any BPV’s that might have occurred intact) via the TTIP and TRING pins ...
Page 13
... Next, the LIRST bit should be toggled from zero to one to reset the line interface cir- cuitry (it will take the DS2153Q about recover from the LIRST bit being toggled). Finally, after the SY- SCLK input is stable, the ESR bit should be toggled from a zero to a one and back to zero (this step can be skipped if the elastic store is not being used) ...
Page 14
... DS2153Q RIR: RECEIVE INFORMATION REGISTER (Address=08 Hex) (MSB) TESF TESE SYMBOL POSITION TESF RIR.7 TESE RIR.6 JALT RIR.5 RESF RIR.4 RESE RIR.3 CRCRC RIR.2 FASRC RIR.1 CASRC RIR.0 SSR: SYNCHRONIZER STATUS REGISTER (Address=1E Hex) (MSB) CSC5 CSC4 SYMBOL POSITION CSC5 SSR.7 CSC4 SSR ...
Page 15
... SR1.2 RCL SR1.1 RLOS SR1.0 amount of time the DS2153Q has been searching for synchronization at the CRC4 level. Annex B of CCITT G.706 suggests that if synchronization at the CRC4 level cannot be obtained within 400 ms, then the search should be abandoned and proper action taken. The CRC4 Sync Counter will rollover ...
Page 16
... DS2153Q ALARM CRITERIA Table 4–1 ALARM RSA1 over 16 consecutive frames (one full (receive signaling MF) timeslot 16 contains less than 3 all ones) zeros RSA0 over 16 consecutive frames (one full (receive signaling MF) timeslot 16 contains all zeros all zeros) RDMA bit 6 in timeslot 16 of frame 0 set to ...
Page 17
... Receive Elastic Store Slip Occurrence. 0=interrupt masked 1=interrupt enabled Receive Unframed All Ones. 0=interrupt masked 1=interrupt enabled Receive Remote Alarm. 0=interrupt masked 1=interrupt enabled Receive Carrier Loss. 0=interrupt masked 1=interrupt enabled Receive Loss of Sync. 0=interrupt masked 1=interrupt enabled DS2153Q (LSB) RRA RCL RLOS 022697 17/48 ...
Page 18
... RCMF IMR2.1 TSLIP IMR2.0 5.0 ERROR COUNT REGISTERS There are a set of four counters in the DS2153Q that record bipolar or code violations, errors in the CRC4 SMF code words, E bits as reported by the far end, and word errors in the FAS. Each of these four counters are automatically updated on either one second boundaries (CCR2 ...
Page 19
... E–bit is set to zero. Since the maximum E–bit count in a one second period is 1000, this counter cannot saturate. counter is disabled during loss of sync at either the FAS or CRC4 level; it will continue to count if loss of multi- frame sync occurs at the CAS level. DS2153Q (LSB) VCR1 ...
Page 20
... Sa bits. This allows the user to create a clock that can be used to capture the needed Sa bits. On the transmit side, the individual Sa bits can be either sourced from the internal TNAF register (TCR1.6=0) or from the external TLINK pin. Via TCR2, the DS2153Q can be programmed to source any combination of the (LSB) EB9 ...
Page 21
... Receive Signaling Registers are updated on multi- frame boundaries so the user can utilize the Receive receive stream and inserted into the transmit stream by the DS2153Q. Each of the 30 channels has four signal- ing bits (A/B/C/D) associated with it. The numbers in parenthesis () are the channel associated with a particu- lar signaling bit ...
Page 22
... Each Transmit Signaling Register (TS1 to TS16) con- tains the CAS bits for two timeslots that will be inserted into the outgoing stream if enabled via TCR1.5. On multiframe boundaries, the DS2153Q will load the values present in the Transmit Signaling Register into an outgoing signaling shift register that is internal to the device ...
Page 23
... Transmit Data Flow diagram in Section 13 for more details. Via the 8.0 TRANSMIT IDLE REGISTERS There is a set of five registers in the DS2153Q that can be used to custom tailor the data that transmitted onto the E1 line channel by channel basis. Each of the 32 E1 channels can be forced to have a user defined idle code inserted into them ...
Page 24
... DS2153Q 9.0 CLOCK BLOCKING REGISTERS The Receive Channel (RCBR1/RCBR2/RCBR3/RCBR4) and the Transmit Channel Blocking Registers (TCBR1/TCBR2/TCBR3/ TCBR4) control the RCHBLK and TCHBLK pins respectively. The RCHBLK and TCHCLK pins are user programmable outputs that can be forced either high or low during individual channels. These outputs can be used to block clocks to a USART or LAPD controller in ISDN– ...
Page 25
... TNAF registers. It has 250 s to update the data or else the old data will be retransmitted. Data in the Si bit posi- tion will be overwritten if either the DS2153Q is pro- grammed: (1) to source the Si bits from the TSER pin, (2) in the CRC4 mode, or (3) have automatic E–bit inser- tion enabled ...
Page 26
... DS2153Q RAF: RECEIVE ALIGN FRAME REGISTER (Address=2F Hex) (MSB SYMBOL POSITION Si RAF.7 0 RAF.6 0 RAF.5 1 RAF.4 1 RAF.3 0 RAF.2 1 RAF.1 1 RAF.0 RNAF: RECEIVE NON–ALIGN FRAME REGISTER (Address=1F Hex) (MSB SYMBOL POSITION Si RNAF.7 1 RNAF.6 A RNAF.5 Sa4 RNAF.4 Sa5 RNAF.3 Sa6 RNAF.2 Sa7 RNAF.1 Sa8 RNAF ...
Page 27
... TNAF.3 Sa6 TNAF.2 Sa7 TNAF.1 Sa8 TNAF.0 12.0 LINE INTERFACE FUNCTIONS The line interface function in the DS2153Q contains three sections; (1) the receiver which handles clock and data recovery, (2) the transmitter which waveshapes LICR: LINE INTERFACE CONTROL REGISTER (Address=18 Hex) (MSB SYMBOL ...
Page 28
... Receive Clock and Data Recovery The DS2153Q contains a digital clock recovery system. See the DS2153Q Block Diagram in Section 1 and Fig- ure 12.1 for more details. The DS2153Q couples to the receive E1 shielded twisted pair or COAX via a 1:1 transformer. See Table 12.3 for transformer details. The ...
Page 29
... NM=Not Meaningful Due to the nature of the design of the transmitter in the DS2153Q, very little jitter (less then 0.00 5UIpp broad- band from 100 KHz) is added to the jitter pres- ent on TCLK. Also, the waveforms that they create are independent of the duty cycle of TCLK. The transmitter in the DS2153Q couples to the E1 transmit shielded TRANSFORMER SPECIFICATIONS Table 12– ...
Page 30
... DS2153Q DS2153Q will divide the attached crystal by either 3.5 or 4.5 instead of the normal 4 to keep the buffer from over- flowing. When the device divides by either 3.5 or 4.5, it CRYSTAL SELECTION GUIDELINES Table 12–4 PARAMETER Parallel Resonant Frequency Mode Load Capacitance Tolerance Pullability ...
Page 31
... DS2153Q JITTER TOLERANCE Figure 12–2 1K 100 0.1 1 DS2153Q TRANSMIT WAVEFORM TEMPLATE Figure 12–3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –250 DS2153Q TOLERANCE 1.5 MINIMUM TOLERANCE LEVEL AS PER ITU G.823 20 10 100 FREQUENCY (Hz) ...
Page 32
... DS2153Q DS2153Q JITTER ATTENUATION Figure 12– –20 dB –40 dB – 13.0 TIMING DIAGRAMS/SYNCHRONIZATION FLOWCHART/TRANSMIT DATA FLOW DIAGRAM RECEIVE SIDE TIMING Figure 13–1 FRAME RSYNC 2 RSYNC 3 RLCLK 4 RLINK NOTES: 1. RSYNC in the frame mode (RCR1.6=0). 2. RSYNC in the multiframe mode (RCR1.6=1). 3. RLCLK is programmed to output just the Sa4 bit. ...
Page 33
... RLINK is programmed to output the Sa4 bits. 3. RLINK is programmed to output the SA4 and SA8 bits. 4. RLINK is programmed to output the Sa5 and Sa7 bits. 5. Shown is a non–align frame boundary. CHANNEL 1 LSB Sa4 Sa5 Sa6 Sa7 Sa8 Sa4 Sa5 Sa6 Sa7 Sa8 DS2153Q CHANNEL 2 MSB 022697 33/48 ...
Page 34
... DS2153Q 1.544 MHz BOUNDARY TIMING WITH ELASTIC STORE(S) ENABLED Figure 13–3 SYSCLK CHANNEL 23/31 1 RSER , TSER 2 RSYNC 3 RSYNC RCHCLK 4 RCHBLK NOTES: 1. Data from the E1 channels 13, 17, 21, 25, and 29 is dropped (channel 2 from the E1 link is mapped to channel 1 of the T1 link, etc.) and the F–bit position is added (forced to one). ...
Page 35
... TRANSMIT SIDE TIMING Figure 13–5 FRAME TSYNC 2 TSYNC 3 TCLK 3 TLINK NOTES: 1. TSYNC in the frame mode (TCR1.1=0). 2. TSYNC in the multiframe mode (TCR1.1=1). 3. TLINK is programmed to source only the Sa4 bit. 4. This diagram assumbes both the CAS MF and the CRC4 begin with the align frame DS2153Q 022697 35/48 ...
Page 36
... DS2153Q TRANSMIT SIDE BOUNDARY TIMING Figure 13–6 TCLK TSER LSB Si 1 TSYNC 2 TSYNC TCHCLK 3 TCHBLK 4 TLCLK Don’t Care 4 TLINK 5 TLCLK Don’t Care 5 TLINK NOTES: 1. TSYNC is in the input mode (TCR1.0=0). 2. TSYNC is in the output mode (TCR1.0=1). 3. TCHBLK is programmed to block channel 2. ...
Page 37
... G.802 TIMING Figure 13–7 TIMESLOT RSYNC/ TSYNC RCHCLK/ TCHCLK RCHBLK/ 1 TCHBLK NOTE: 1. RCHBLK or TCHBLK is programmed to pulse high during timeslots 25, and during bit 1 of time- slot 26. RCLK/TCLK TIMESLOT 25 RSER/TSER RCHCLK/TCHCLK RCHBLK/TCHCLK DS2153Q DETAIL TIMESLOT 26 LSB MSB 022697 37/48 4 ...
Page 38
... DS2153Q DS2153Q SYNCHRONIZATION FLOWCHART Figure 13–8 RLOS=1 RESYNC IF RCR1.1=0 INCREMENT CRC4 SYNC COUNTER; CRC4SA=0 SET FASRC (RIR.1) CRC4 RESYNC CRITERIA MET (RIR.2) CAS RESYNC CRITERIA MET; SET CASRC (RIR.0) 022697 38/48 CRC4 MULTIFRAME 8 MS SEARCH (IF ENABLED TIME VIA CCR.0) OUT CRC4SA=1 CRC4 SYNC CRITERIA MET ...
Page 39
... DS2153Q TRANSMIT DATA FLOW Figure 13–9 TAF TNAF 0 TIMESLOT 0 PASS–THROUGH (TCR1. BIT INSERTION CONTROL (TCR1.3) CRC4 MULTIFRAME ALIGNMENT WORD GENERATION (CCR1.4) TCBR1/2/3/4 CCR3.6 TCR1.5 KEY = REGISTER = DEVICE PIN = SELECTOR NOTE: 1. TCLK must be tied to RCLK (or SYSCLK if the elastic store is enabled) and TSYNC must be tied to RSYNC for data to be properly sourced from RSER ...
Page 40
... V 2 –0 4. 4.80 DD SYMBOL MIN TYP OUT (– + SYMBOL MIN TYP –1 –1 +4.0 OL (– +85 C for DS2153QN (– +85 C for DS2153QN) MAX UNITS V +0 +0.8 V 5.25 V 5.25 V MAX UNITS =5V +5%/–4% for DS2153QN) DD MAX UNITS mA +1 NOTES = NOTES =5V + 5%) ...
Page 41
... SYMBOL MIN TYP t 250 CYC PW 150 EL PW 100 RWH t 50 RWS DHR t 0 DHW t 20 ASL t 10 AHL t 25 ASD PW 40 ASH t 20 ASED t 20 DDR t 80 DSW DS2153Q ( =5V + 5%) DD =5V +5%/–4% for DS2153QN) DD MAX UNITS NOTES 100 ns ns 022697 41/48 ...
Page 42
... DS2153Q INTEL READ BUS AC TIMING Figure 14–1 ALE t ASD AD0-AD7 INTEL WRITE BUS AC TIMING Figure 14–2 ALE t ASD AD0-AD7 022697 42/48 PW ASH t t ASD ASED ASL t AHL PW ASH t t ASED ASD ASL t AHL t CYC DDR t CYC DSW DHR DHW ...
Page 43
... MOTOROLA BUS AC TIMING Figure 14– ASD R/W AD0-AD7 (READ) CS AD0-AD7 (WRITE) PW ASH t ASED RWS t ASL t AHL ASL t AHL CYC t RWH t t DDR DSW DS2153Q DHR t DHW 022697 43/48 ...
Page 44
... Jitter attenuator disabled or enabled in the transmit path. 3. SYSCLK=1.544 MHz. 4. SYSCLK=2.048 MHz. 022697 44/48 (– + SYMBOL MIN TYP t 488 CP t 180 244 CH t 180 244 244 CH t 200 244 CL t 648 SP t 488 =5V DD =5V +5%/–4% for DS2153QN) DD MAX UNITS NOTES – 5%) ...
Page 45
... RSYNC is in the input mode (RCR1.5=1). 3. RLCLK and RLINK only have a timing relationship to RCLK; no timing relationship between RLCLK/RLINK and RSYNC is implied. 4. RCLK can exhibit a short high time if the jitter attenuator is either disabled or in the transmit path MSB OF CHANNEL DS2153Q 022697 45/48 ...
Page 46
... Delay TCLK to TSYNC Delay TCLK to TLCLK NOTES the transmit side elastic store is enabled,then TSER is sampled on the falling edge of SYSCLK and the parameters t and t still apply 022697 46/48 (– + SYMBOL MIN TYP t 488 =5V + 5%) DD =5V +5%/–4% for DS2153QN) DD MAX UNITS NOTES – ...
Page 47
... TSYNC 2 TSYNC 3 TLCLK 3 TLINK NOTES: 1. TSYNC is in the output mode (TCR1.0=1). 2. TSYNC is in the input mode (TCR1.0=0 timing relationship between TSYNC and TLCLK/TLINK is implied. 4. TSER is sampled on the falling edge of SYSCLK if the transmit side elastic store is enabled LSB MSB DS2153Q 022697 47/48 ...
Page 48
... DS2153Q DS2153Q E1 SINGLE–CHIP TRANSCEIVER 44–PIN PLCC .075 MAX NOTE 1 CH1 .150 MAX E2 NOTE1: PIN 1 IDENTIFIER TO BE LOCATED IN ZONE INDICATED. INCHES DIM MIN MAX A 0.165 0.180 A1 0.090 0.120 A2 0.020 – B 0.026 0.033 B1 0.013 0.021 C 0.009 0.012 CH1 0.042 0.048 D 0.685 0.695 D1 0 ...