MACH110-12JC Lattice Semiconductor Corp., MACH110-12JC Datasheet
MACH110-12JC
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MACH110-12JC Summary of contents
Page 1
... EE CMOS MACH 1 family. This device has approxi- mately three times the logic macrocell capability of the popular PAL22V10 without loss of speed. The MACH110 consists of two PAL blocks intercon- nected by a programmable switch matrix. The two PAL blocks are essentially “PAL22V16” structures complete with product-term arrays and programmable macro- cells ...
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... BLOCK DIAGRAM 2 I/O – I I/O Cells 16 16 Macrocells AND Logic Array and Logic Allocator 22 Switch Matrix AND Logic Array and Logic Allocator OE 2 Macrocells 16 16 I/O Cells 16 16 I/O – I MACH110-12/15/20 I – – CLK / CLK / 14127I-1 ...
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... CONNECTION DIAGRAM Top View I/O 5 I GND CLK I/O 8 I/O 9 I/O 10 I/O 11 Note: Pin-compatible with MACH111, MACH210, MACH211, and MACH215. PIN DESIGNATIONS CLK/I = Clock or Input GND = Ground I = Input I/O = Input/Output V = Supply Voltage CC PLCC MACH110-12/15/ I CLK GND 14127I-2 3 ...
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... The Valid Combinations table lists configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. MACH110-12/15/20 (Com’l) OPTIONAL PROCESSING Blank = Standard Processing OPERATING CONDITIONS C = Commercial ( +70 C) PACKAGE TYPE ...
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... The Valid Combinations table lists configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. MACH110-14/18/25 (Ind) OPTIONAL PROCESSING Blank = Standard Processing OPERATING CONDITIONS I = Industrial (– +85 C) PACKAGE TYPE ...
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... I/O cells; the other two control the last eight macrocells. The Logic Allocator The logic allocator in the MACH110 takes the 64 logic product terms and allocates them to the 16 macrocells as needed. Each macrocell can be driven product terms. The design software automatically configures the logic allocator when fitting the design into the device ...
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... Switch Matrix Figure 1. MACH110 PAL Block MACH110-12/15/20 Output Enable Output Enable Asynchronous Reset Asynchronous Preset I/O Cell Output M Macro 0 Cell I/O Cell Output M Macro 1 Cell I/O Cell Output M Macro 2 Cell I/O Cell Output M Macro 3 Cell I/O Cell C Output 0 M Macro 4 Cell ...
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... Voltage for all Inputs (Note 5. Max (Note Max (Note 5. Max OUT (Note Max OUT (Note 0 Max (Note 3) OUT = MHz (Note 4) and I (or I and OZL IH OZH MACH110-12/15/20 (Com’ + +4. +5.25 V Min Typ Max Unit 2.4 V 0.5 V 2 – –10 A –30 –160 ...
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... 5 2 MHz OUT -12 Min Max 7 D-type 8 T-type 0 6 LOW 6 HIGH 66.7 D-type + 62.5 T-type D-type 76.9 ) CNT 71.4 T-type 1/( 83 MACH110-12/15/20 (Com’l) Typ Unit -15 -20 Min Max Min Max Unit MHz 47.6 38.5 MHz 66.6 47.6 MHz 55.5 43.5 MHz 83 ...
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... VIN = 0 V, VCC = Max (Note 2) VOUT = 5.25 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0.5 V, VCC = Max (Note 3) VCC = MHz (Note 4) and I (or I and OZL IH OZH MACH110-14/18/20 (Ind – +5.5 V Min Typ Max Unit 2.4 V ...
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... Min Max 14.5 8.5 D-type 10 T-type 0 10 7.5 LOW 7.5 HIGH 53.5 D-type + T-type D-type 61.5 ) CNT 57 T-type 1/( 66 19.5 14.5 10 19.5 14.5 10 14.5 14.5 MACH110-14/18/20 (Ind) Typ Unit -18 -24 Min Max Min Max Unit 13 14 MHz 38 30 MHz 53 ...
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... TYPICAL CURRENT VS. VOLTAGE (I-V) CHARACTERISTICS –1.0 12 (mA –0.8 –0.6 –0.4 –0 –20 –40 –60 –80 Output, LOW I (mA –3 –2 –1 –25 –50 –75 –100 –125 –150 Output, HIGH I (mA –2 – –20 –40 –60 –80 –100 Input MACH110-12/15/ 1.0 14127I (V) OH 14127I 14127I-6 ...
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... CC A 150 125 100 75 ICC (mA The selected “typical” pattern is a 16-bit up/down counter. This pattern is programmed in each PAL block and is capable of being loaded, enabled, and reset. Maximum frequency shown uses internal feedback and a D-type register Frequency (MHz) MACH110-12/15/20 MACH110 14127I-7 13 ...
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... Furthermore, jc tests on packages are performed in a constant-temperature bath, keeping the package surface at a constant temperature. Therefore, the measurements can only be used in a similar environment. 14 200 lfpm air 400 lfpm air 600 lfpm air 800 lfpm air MACH110-12/15/20 Typ PLCC Unit 14 C/W 39 ...
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... V T Out 14127I-9 Gate t WL 14127I- Registered Input t HIR Input V T Register Clock t ICO V T Output Register Clock 14127I-13 MACH110-12/15/ 14127I PDL Latched Output (MACH 2, 3, and GWS Gate Width (MACH 2, 3, and ICS V T Input Register to Output Register Setup (MACH 2 and 4) ...
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... Latch Gate t IGS Output Latch Gate Notes 1 Input pulse amplitude 3 Input rise and fall times 2 ns–4 ns typical SIL HIL Latched Input (MACH 2 and 4) t IGOL Latched Input and Output (MACH 2, 3, and 4) MACH110-12/15/ IGO V T 14127I-15 t PDLL SLL V T 14127I-16 ...
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... Input rise and fall times 2 ns–4 ns typical. Input V Latch T Gate t WICL 14127I-17 Input, I/ Feedback Registered V T Output t ARR Clock V T 14127I- Outputs + V OL Output Disable/Enable MACH110-12/15/20 t WIGL Input Latch Gate Width (MACH 2 and 4) t APW Asynchronous Preset 0. 0.5V 14127I- 14127I- APR V T 14127I-20 17 ...
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... Don’t Care, Any Change Permitted Does Not Apply Output Commercial 300 390 5 pF MACH110-12/15/20 OUTPUTS Will be Steady Will be Changing from Will be Changing from Changing, State Unknown Center Line is High- Impedance “Off” State KS000010-PAL Test Point 14127I-22 Measured R Output Value 2 1 ...
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... All frequencies except f MAX other measured AC parameters. f ured directly. ” (SECOND CHIP MACH110-12/15/ type is the mini- MAX + t ). Usually, this minimum feedback.” MAX . Because this involves no MAXIR + the sum of SIR HIR + t ). The clock widths are nor- WICL ...
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... Min Pattern Data Retention Time Max Reprogramming Cycles 20 bipolar parts result, the device can be erased and reprogrammed, a feature which allows 100% testing at the factory. Min Units 10 Years 20 Years 100 Cycles MACH110-12/15/20 Test Conditions Max Storage Temperature Max Operating Temperature Normal Programming Conditions ...
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... INPUT/OUTPUT EQUIVALENT SCHEMATICS ESD Protection Input 100 k Preload Feedback Circuitry Input I/O MACH110-12/15/20 CC 100 14127I-24 21 ...
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... CC 2. Following reset, the clock input must not be driven from LOW to HIGH until all applicable input and feedback setup times are met Power-Up Reset Waveform MACH110-12/15/20 can rise to its steady state, two CC rise must be monotonic. Max 10 See Switching Characteristics V CC 14127I-25 ...
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... All MACH 2 devices support both preload and observability. Contact individual programming vendors in order to verify programmer support. On Preload Off Mode Figure 2. Preload/Reset Conflict Set Reset Figure 3. Combinatorial Latch MACH110-12/15/20 Preloaded HIGH Preloaded HIGH 14127I-26 14127I-27 23 ...
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... REF .032 TOP VIEW *For reference only. BSC is an ANSI standard for Basic Space Centering. 28 .062 .083 .042 .056 .009 .015 .090 .120 .165 .180 SIDE VIEW MACH110-12/15/20 .500 .590 REF .630 .013 .021 SEATING PLANE 16-038-SQ PL 044 DA78 6-28-94 ae ...