MC14522BCP Motorola, MC14522BCP Datasheet

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MC14522BCP

Manufacturer Part Number
MC14522BCP
Description
Presettable 4-bit down counter
Manufacturer
Motorola
Datasheet

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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Dual 1.1 GHz PLL Frequency
Synthesizer
BiCMOS
serial interface capable of direct usage up to 1.1 GHz. The device simulta-
neously supports two loops. The two on–chip dual–modulus prescalers may be
independently programmed to divide by either 32/33 or 64/65.
counters, two 12–stage N counters, two fully programmable 13–stage R
(reference) counters, and two lock detectors. Four phase/frequency detectors
are included: two with current source/sink outputs and two with double–ended
outputs.
compatible. The serial port is byte–oriented to facilitate control via an MCU. Due
to the innovative BitGrabber Plus registers, the MC145220 may be cascaded
with other peripherals featuring BitGrabber Plus without requiring leading
dummy bits or multiple address bits in the serial data stream. In addition,
BitGrabber Plus peripherals may be cascaded with existing BitGrabber
peripherals. Because this device is a dual synthesizer, a single steering bit is
used in the serial data stream to direct the data to either side of the chip.
zones). The current delivered by the current source/sink outputs is controllable
via the serial port.
on–board support of an external crystal. In addition, the part may be configured
such that the REF in pin accepts an external reference signal. In this
configuration, the REF out pin may be programmed to output the REF in
frequency divided by 1, 2, 4, 8, or 16.
NOTE: This product has been evaluated for operation over a wider range than 40 MHz to 1.1 GHz. If your design requires a wider
frequency range, contact your local Motorola representative for further information.
BitGrabber and BitGrabber Plus are trademarks of Motorola, Inc.
REV 4
1/98
MOTOROLA
The MC145220 is a low–voltage, single–chip frequency synthesizer with
The device consists of two dual–modulus prescalers, two 6–stage A
The counters are programmed via a synchronous serial port which is SPI
The phase/frequency detectors have linear transfer functions (no dead
Also featured are low–power standby for either one or both loops and
Motorola, Inc. 1998
Operating Frequency: 40 to 1100 MHz
Operating Supply Voltage Range: 2.7 to 5.5 V
Supply Current: Both PLLs Operating — 12 mA Nominal
Phase Detector Output Current: Up to 2 mA @ 5 V
Operating Temperature Range: – 40 to 85 C
Independent R Counters Allow Use of Different Step Sizes for Each Loop
Double–Buffered R Register — Reference and Loop Divide Ratios
Updated Simultaneously
R Counter Division Range: 1 and 10 to 8,191
Dual–Modulus Capability Provides Total Division of the VCO Frequency up
to 262,143
Direct Interface to Motorola SPI Data Port
Evaluation Kit Available (Part Number MC145220EVK)
See Application Note AN1253/D for Low–Pass Filter Design, and
AN1277/D for Offset Reference PLLs for Fine Resolution or Fast Hopping
TN98012300
One PLL Operating, One on Standby — 6.5 mA Nominal
Both PLLs on Standby — 30 A Maximum
Up to 1 mA @ 3 V
20
OUTPUT A
PD out / R
20
ORDERING INFORMATION
MC145220F
MC145220DT
REF out
MC145220
Rx / V
REF in
GND
1
LD
V+
f in
f in
PIN ASSIGNMENT
1
1
2
3
4
5
6
7
8
9
10
SOG Package
TSSOP
Order this document
SOG PACKAGE
20
19
18
17
16
15
14
13
12
11
CASE 803C
CASE 948D
DT SUFFIX
F SUFFIX
by MC145220/D
TSSOP
D in
CLK
LD
PD out / R
Rx / V
GND
f in
f in
V+
ENB
MC145220
1

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MC14522BCP Summary of contents

Page 1

... AN1277/D for Offset Reference PLLs for Fine Resolution or Fast Hopping NOTE: This product has been evaluated for operation over a wider range than 40 MHz to 1.1 GHz. If your design requires a wider frequency range, contact your local Motorola representative for further information. BitGrabber and BitGrabber Plus are trademarks of Motorola, Inc. ...

Page 2

... DATA OUT 5 ADDRESS 2 LOGIC AND STORAGE PHASE/ FREQUENCY 4 PD out / R DETECTOR 5 PAIR f R Rx/ V STBY 2 UNUSED 2 BitGrabber Plus C REGISTER BitGrabber Plus 7 BITS C REGISTER 7 BITS UNUSED STBY (INTERNAL PHASE/ 17 FREQUENCY PD out / R DETECTOR PAIR PORT MUX OUTPUT SELECT FROM PLL / PLL A REGISTER (INTERNAL) MOTOROLA ...

Page 3

... Maximum Input Current I OZ Maximum Output Leakage Current (PD out / out I OZ Maximum Output Leakage Current I STBY Maximum Standby Supply Current I T Total Operating Supply Current * The nominal value is 12 mA. This is not a guaranteed limit. MOTOROLA Value Unit – 0 6.0 V – 0 0.5 V – ...

Page 4

... – Input unless otherwise indicated) i Parameter 2 Guaranteed Limit Unit 0 – 0 Guaranteed Limit Unit (Figure 2.0 MHz 200 ns 200 ns 200 Guaranteed Limit Unit (Figure (Figure 4) 100 ns (Figure 4) * cycles (Figure 1) 250 ns (Figure 1) 100 s MOTOROLA ...

Page 5

... OUT) 10% t TLH t THL Figure 1. VALID 50 50% CLK Figure 3. TEST POINT DEVICE UNDER TEST * Includes all probe and fixture capacitance. Figure 5. MOTOROLA V+ GND ENB OUTPUT A V+ ENB 50% GND CLK 50% GND FIRST CLOCK Includes all probe and fixture capacitance. V+ 50% GND ...

Page 6

... REF out pF, Includes Stray Capacitance; R Counter and REF Counter same as above Phase with – Guaranteed Operating Range Min Max Unit – dBm* – – MHz 4 27 MHz MHz MHz dc 1 MHz 16 125 ns — MOTOROLA ...

Page 7

... Figure 8. Test Circuit — Reference Mode REF in C1 DEVICE UNDER TEST REF out C2 GND V+ Figure 9. Test Circuit — Crystal Mode t w 50% OUTPUT Figure 11. Switching Waveform MOTOROLA DC 50 PAD BLOCK f in DEVICE UNDER TEST f in GND V+ GND pad may network. Figure 7. Test Circuit ...

Page 8

... F 878 + j 703 800 G 705 + j 208 1100 H 215 – j 69.3 (50 – 1100 MHz) Impedance ( ) 5 V Supply 1970 – j 102 1510 + j 19 671 – j 334 223 – j 147 Impedance ( ) 5 V Supply 1930 + j 214 746 + j 741 626 + j 327 243 – j 61.3 MOTOROLA ...

Page 9

... Not Allowed Values > 32 See Figures MOTOROLA CLK Serial Data Clock Input (Pin 19) Low–to–high transitions on CLK shift bits available at the D in pin, while high–to–low transitions shift bits from Output A (when configured as Data Out, see Pin 10). The 24–1/2 stage shift register is static, allowing clock rates down continuous or intermittent mode ...

Page 10

... Figure 7). Note that driven while f in must be tied to ac ground (via capacitor). The signal sources driving these pins originate from external VCOs. Motorola does not recommend driving f in while terminating f in because this configuration is not tested for sensitivity. The sensitivity is dependent on the frequency as shown in the Loop Specifications table ...

Page 11

... V these outputs can be combined externally to generate a loop error signal. Through use of a Motorola patented technique, the detector’s dead zone has been eliminated. Therefore, the phase/frequency detector is characterized by a linear trans- fer function. The operation of the phase/frequency detectors are described below and are shown in Figure 17. ...

Page 12

... GND and GND i and a i Grounds (Pins 6 and 15) must be at the i The GND pin is the ground for the main PLL and GND the ground for PLL using separate low–induc MOTOROLA ...

Page 13

... Selects the output polarity of the associated phase/frequency detectors. When set high, this bit inverts the associated current source/sink output and interchanges the associated double–ended output relative to the waveforms in Figure 17. Also, see the phase detector output pin descriptions for more information. This bit is cleared low at power up. Figure 14. C and C MOTOROLA ...

Page 14

... Figure 15. A and A i MC145220 14 Register Accesses and Format (24 Clock Cycles are Used) MOTOROLA ...

Page 15

... Bits R0 – R12 are transferred to the second buffer of the R register (Rs in the Block Diagram subsequent 24–bit write to the A register. The bits are transferred new ratio after completing the rest of its present count cycle. 6. Allows direct access to reference input of phase/frequency detectors. Figure 16. R Register Access and Format (16 Clock Cycles are Used) MOTOROLA ...

Page 16

... Figure 14 for POL High voltage level Low voltage level. 4. The waveforms are applicable to both the main PLL and PLL . Figure 17. Phase/Frequency Detectors and Lock Detector Output Waveforms MC145220 NOTE 1 SOURCING CURRENT FLOAT SINKING CURRENT HIGH IMPEDANCE V L MOTOROLA ...

Page 17

... CRYSTAL OSCILLATOR CONSIDERATIONS The following options may be considered to provide a ref- erence frequency to Motorola’s CMOS frequency synthe- sizers. Use of a Hybrid Crystal Oscillator Commercially available temperature–compensated crystal oscillators (TCXOs) or crystal–controlled data clock oscilla- tors provide very stable reference frequencies. An oscillator capable of CMOS logic levels at the output may be direct or dc coupled to REF in ...

Page 18

... D. Kemper, L. Rosine, “Quartz Crystals for Frequency Table 4. Partial List of Crystal Manufacturers Motorola — Internet Address http://motorola.com NOTE: Motorola cannot recommend one supplier over another and in no way suggests that this is a complete listing of crystal manufacturers. MC145220 18 Control”, Electro–Technology , June 1969. ...

Page 19

... AN535, Phase–Locked Loop Design Fundamentals, Motorola Semiconductor Products, Inc., 1970. AR254, Phase–Locked Loop Design Articles, Motorola Semiconductor Products, Inc., Reprinted with permission from Electronic Design, 1987. AN1253, An Improved PLL Design Method Without n and , Motorola Semiconductor Products, Inc., 1995. MOTOROLA K K VCO ...

Page 20

... Figure 21. Application Showing Use of the Two Single–Ended Phase/Frequency Detectors MC145220 20 NOTE 5 R1 MC145220 1 REF REF out CLK out / R PD out / Rx GND GND OUTPUT A ENB (PORT) pins to GND and GND with low–inductance capacitors NOTE MCU LOW–PASS FILTER VCO +V BUFFER OUTPUT MOTOROLA ...

Page 21

... LD and LD are open–drain outputs. This allows the wired–OR configuration shown. Note that R1 and Q1 form the “pull–up device”. 6. Use optional and depends on loading. Figure 22. Application Showing Use of the Two Double–Ended Phase/Frequency Detectors MOTOROLA NOTE 5 R1 MC145220 ...

Page 22

... this determines the values (N, A) that must be programmed into the N and A counters, DEVICE #1 OUTPUT A CLK ENB (DATA OUT OPTIONAL Figure 24. Cascading Two Devices +V NOTE MCU LOW–PASS FILTER VCO +V BUFFER OUTPUT DEVICE #2 OUTPUT A CLK ENB (DATA OUT) MOTOROLA ...

Page 23

... Figure 25. Accessing the Registers of MOTOROLA Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç ...

Page 24

... Two Cascaded MC145220 Devices (48 Clock Cycles are Used) MOTOROLA ...

Page 25

... MOTOROLA Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç Ç ...

Page 26

... D 0.05 0.25 0.002 0.010 F 0.45 0.55 0.018 0.022 G 0.65 BSC 0.026 BSC H 0.275 0.375 0.010 0.015 J 0.09 0.24 0.004 0.009 J1 0.09 0.18 0.004 0.007 K 0.16 0.32 0.006 0.013 K1 0.16 0.26 0.006 0.010 L 6.30 6.50 0.248 0.256 MOTOROLA ...

Page 27

... Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “ ...

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