TDA4853 NXP Semiconductors, TDA4853 Datasheet

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TDA4853

Manufacturer Part Number
TDA4853
Description
Manufacturer
NXP Semiconductors
Datasheet

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TDA4853
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Philips
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Part Number:
TDA4853
Manufacturer:
PHILLIP
Quantity:
20 000
Product specification
Supersedes data of 1998 May 12
File under Integrated Circuits, IC02
DATA SHEET
TDA4853; TDA4854
I
controllers for PC/TV monitors
2
C-bus autosync deflection
INTEGRATED CIRCUITS
1999 Jul 13

Related parts for TDA4853

TDA4853 Summary of contents

Page 1

... DATA SHEET TDA4853; TDA4854 2 I C-bus autosync deflection controllers for PC/TV monitors Product specification Supersedes data of 1998 May 12 File under Integrated Circuits, IC02 INTEGRATED CIRCUITS 1999 Jul 13 ...

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... C-bus controllable output for horizontal and vertical parabolas Vertical parabola is independent of frequency and tracks with vertical adjustments Horizontal parabola independent of frequency Pre-correction of delay in focus output stage. 2 C-bus and f by external max 2 Product specification TDA4853; TDA4854 2 C-bus controllable vertical sawtooth and 2 C-bus. ...

Page 3

... B+ control, an extensive set of geometry control facilities, and a combined output for horizontal and vertical focus signals. The TDA4853 is an economy version of the TDA4854, especially designed for use in 14” and 15” monitors with combined EHT generation. It provides the same features as the TDA4854 except for the dynamic focus block. ...

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... HPLL1 3.3 k 8.2 nF 100 nF (1) For the calculation of f range see Section “Calculation of line frequency range”. H (2) See Figs 23 and 24. Fig.1 Block diagram and application circuit of TDA4853. EHT compensation via vertical size EHT compensation 22 100 via horizontal size 150 k nF ...

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Acrobat reader. white to force landscape pages to be ... VERTICAL VERTICAL VSYNC 14 SYNC INPUT SYNC AND POLARITY (TTL level) INTEGRATOR CORRECTION VIDEO ...

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... HPLL2 30 external filter for PLL2/soft start HSMOD 31 input for EHT compensation (via horizontal size) i.c. 32 internally connected; note 1: TDA4853 FOCUS 32 output for horizontal and vertical focus: TDA4854 Note 1. External connections to this pin are not allowed. 1999 Jul 13 TDA4853; TDA4854 DESCRIPTION 6 Product specifi ...

Page 7

... HSYNC 15 CLBL 16 MGM066 Fig.3 Pin configuration for TDA4853. FUNCTIONAL DESCRIPTION Horizontal sync separator and polarity correction HSYNC (pin 15) is the input for horizontal synchronization signals, which can be DC-coupled TTL signals (horizontal or composite sync) and AC-coupled negative-going video sync signals. Video syncs are clamped to 1.28 V and sliced at 1 ...

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... HBUF output is clamped to 2.5 V and an internally defined PLL1 control range of 10% is established. To return to standard operation of the frequency-to-voltage converter the bit TVMOD has to be reset. For an optimal operation with VCR signals the RC combination at pin HPLL1 has to be switched externally. 8 Product specification TDA4853; TDA4854 2 C-bus 2 C-bus, ...

Page 9

... Control bit MOD disables the moire cancellation function. can be calculated using 2. 726 = kHz 9 Product specification TDA4853; TDA4854 is calculated as the value of R HBUFpar in parallel. The formulae for R HBUF R R HREF HBUFpar = --------------------------------------------- - 0.8 ...

Page 10

... HUNLOCK (pin 17) switches from the floating status to normal vertical blanking, and continuous blanking at CLBL (pin 16) is removed. 1999 Jul 13 TDA4853; TDA4854 Output stage for line drive pulses [HDRV (pin 8)] An open-collector output stage allows direct drive of an inverting driver transistor because of a low saturation voltage of 0 ...

Page 11

... To achieve a cancellation of vertical moire (also known as 2 C-bus. A precise ‘scan moire’) the vertical picture position can be modulated by half the vertical frequency. The amplitude of the modulation is controlled by register VMOIRE and can be switched off via control bit MOD. 11 Product specification TDA4853; TDA4854 ...

Page 12

... I will be HSMOD as shown in the equation 2. Control bit ACD = 0 f(HSIZE HPIN h(I ) HREF If the tube does not need HPINBAL and HPARAL, then pin ASCOR can be used for other purposes, i.e. for a simple dynamic convergence. 12 TDA4853; TDA4854 V + HSIZE 1 = – ------------------------------------------------------------------------- - I HREF = ------------------------------- - HREF I HREF ...

Page 13

... FOCUS (pin 32) is designed as a voltage output for the superimposed vertical and horizontal parabolas. B+ control function block The B+ control function block of the TDA4853; TDA4854 consists of an Operational Transconductance Amplifier (OTA), a voltage comparator, a flip-flop and a discharge circuit. This configuration allows easy applications for different B+ control concepts. See also Application Note AN96052: “ ...

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... Jul 13 2 C-bus will When the protection mode is active, several pins of the TDA4853; TDA4854 are forced into a defined state: HDRV (horizontal driver output) is floating BDRV (B+ control driver output) is floating HUNLOCK (indicates, that the frequency-to-voltage converter is out of lock) is floating (HIGH via external ...

Page 15

... Note 1. Tests are performed with application reference board. Tests with other boards will have different results. 1999 Jul 13 PARAMETER PARAMETER CONDITIONS note 1 note 1 15 Product specification TDA4853; TDA4854 CONDITIONS MIN. MAX. 0.5 +16 0.5 +6.0 0.5 +6.5 0.5 +8.0 ...

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... 0.52 mA HREF f = 31.45 kHz 1.052 mA HREF kHz 2.141 mA HREF f = 100 kHz 3.345 mA HREF 0 V < V SYNC 16 Product specification TDA4853; TDA4854 MIN. TYP. 1.7 1 VIDEO NEGATIVE SYNC POLARITY 300 90 120 1.1 1.28 1.7 2.4 0 3.9 5 ...

Page 17

... CLAMP = 1; measured CLBL notes 1 and 2 1.7 control bit VBLK = 0 220 control bit VBLK = 1 305 0.59 CLBL 2.4 17 Product specification TDA4853; TDA4854 TYP. MAX. UNIT 400 s 1.8 ms 0.7 0.8 s 4.75 5. mV/K 50 ns/V 130 ns 1 ...

Page 18

... PLL1 locked = 1 V HUNLOCK case of HUNLOCK unlocked PLL1 and/or protection active notes 4 and 5 locked mode, level 1 locked mode, level 2 minimum horizontal frequency maximum horizontal frequency 18 Product specification TDA4853; TDA4854 TYP. MAX. UNIT 31.45 32.39 kHz 3 +100 10 /K 130 kHz 2.55 2 ...

Page 19

... MOD = 0 H register HMOIRE = 31; V control bit MOD = 0 control bit MOD = 1 maximum advance; register HPINBAL = 07; register HPARAL = 07 minimum advance; register HPINBAL = 07; register HPARAL = 07 V < 3.7 V HPLL2 HFLB HFLB 19 Product specification TDA4853; TDA4854 MIN. TYP. MAX. UNIT 0 0 ...

Page 20

... V R XSEL no reset via VREF C = 100 nF VCAP constant amplitude; note 7 50 control bit VBLK = 0 control bit VBLK = 1 control bit AGCDIS = 0 control bit AGCDIS = 1 20 Product specification TDA4853; TDA4854 MIN. TYP 45.5 48 6.22 6.39 500 set control bit SOFTST via ...

Page 21

... VPOS = X; control bit VPC = 1 ; see Fig.7 register VLIN = 0; control bit VSC = 0; note 8 register VLIN = 15; control bit VSC = 0; note 8 register VLIN = X; control bit VSC = 1; note 8 maximum VLIN 21 Product specification TDA4853; TDA4854 MIN. TYP. MAX. 150 220 ; see Fig.5 60 100 70 115.9 116.8 117 ...

Page 22

... HSIZE = 255 note 9 register HPIN = 0; note 8 register HPIN = 63; note 8 register HCOR = 0; control bit VSC = 0; note 8 register HCOR = 31; control bit VSC = 0; note 8 register HCOR = X; control bit VSC = 1; note 8 22 Product specification TDA4853; TDA4854 MIN. TYP. MAX. 3.3 2.5 1.7 1.7 2.5 3 ...

Page 23

... FHMULT = 1; note 10 function disabled; control bit FHMULT = 0; note 10 register HPARAL = 0; control bit HPC = 0; note 8 register HPARAL = 15; control bit HPC = 0; note 8 register HPARAL = X; control bit HPC = 1; note 8 23 Product specification TDA4853; TDA4854 TYP. MAX. UNIT 0. 0. ...

Page 24

... VFOCUS = 0; note 8 register VFOCUS = 07; note FOCUS FOCUS BIN BOP PINS AND I < BOP note 11 note 12 24 Product specification TDA4853; TDA4854 MIN. TYP. 1.0 1.0 0.05 4 6.5 4.0 1.9 1.5 50 0.06 3.2 350 = 350 ns 1.9 = 350 ns 0.02 0.8 5 ...

Page 25

... BSENS V > 2.5 V BSENS fault condition STDBY = 1; V 3.5 V < kHz V decreasing from decreasing from increasing from below CC typical Product specification TDA4853; TDA4854 MIN. TYP 250 500 = 3 V 0.85 1.0 4.5 6.0 1.2 1.3 2 9.2 70 < PLL2 < ...

Page 26

... All vertical and EW adjustments are specified at nominal vertical settings; unless otherwise specified, which means: a) VSIZE = 100% (register VSIZE = 127 and control bit VOVSCN = 0) b) VSMOD = 0 (no EHT compensation) 1999 Jul 13 CONDITIONS V decreasing from CC above typical 8.3 V VOLTAGE ]’. fr(V) 26 Product specification TDA4853; TDA4854 MIN. TYP. MAX. UNIT 7.7 8.1 8.5 V 4.7 V 3 ...

Page 27

... I VOUT1 I VOUT2 ( ( the maximum amplitude setting at register VSIZE = 127 1 and control bit VPC = 1. I – 2 VPOS = --------------------- - 2 I Fig.6 Adjustment of vertical position. 27 Product specification TDA4853; TDA4854 . The EWDRV low level of 1.2 V HREF V BOP ------------- - with no resistive load V BIN ( 100% 1 MBG592 ...

Page 28

... VLINBAL handbook, halfpage MGM069 V EWDRV V HPIN(EWDRV) t Fig.10 Influence of corner correction at 28 Product specification TDA4853; TDA4854 I VOUT1 I VOUT2 I is the maximum amplitude setting at register VSIZE = 127, 1 register VOVSCN = 0, control bit VPC = 1, control bit VLIN = 1 and control bit VLINBAL = – --------------------- - ...

Page 29

... Fig.13 Adjustment of parallelogram at pin ASCOR. 1999 Jul 13 MGM071 handbook, halfpage V EWDRV V HTRAP(EWDRV) t Fig.12 Influence of HSIZE and EHT compensation MGM073 handbook, halfpage V ASCOR V c(ASCOR) V HPARAL(ASCOR) t Fig.14 Adjustment of pin balance at pin ASCOR. 29 Product specification TDA4853; TDA4854 V HSIZE(EWDRV) V HEHT(EWDRV) at pin EWDRV. V HPINBAL(ASCOR) MGM072 t MGM074 t ...

Page 30

... VOUT2 (pin 12) EW drive waveform at EWDRV (pin 11) 1999 Jul 13 4.0 V automatic trigger level 3.8 V synchronized trigger level 1.4 V inhibited I VOUT1 I VOUT2 DC shift 3.6 V maximum Fig.15 Pulse diagram for vertical part. 30 Product specification TDA4853; TDA4854 7.0 V maximum low-level 1.2 V fixed MGM075 ...

Page 31

... PLL2 control current at HPLL2 (pin 30) line drive pulse at HDRV (pin 8) horizontal focus parabola at FOCUS (pin 32) 1999 Jul PLL2 control range 45 to 52% of line period Fig.16 Pulse diagram for horizontal part. 31 Product specification TDA4853; TDA4854 - vertical blanking level – t precor MGM076 ...

Page 32

... Generation of video clamping pulses during vertical sync with serration pulses. Fig.18 Pulse diagrams for composite sync applications. 1999 Jul time of HDRV as a function of horizontal frequency. OFF a. Reduced influence of vertical sync on horizontal phase. 32 Product specification TDA4853; TDA4854 MGM077 110 130 f H (kHz) MGC947 MBG596 ...

Page 33

... C-bus message until the start of the vertical sync or vertical blanking. vertical handbook, full pagewidth sync pulse vertical blanking pulse SDA Fig.19 Timing of the I 1999 Jul 13 (2) (3) A SUBADDRESS 2 C-bus transmission for interference-free adjustment. 33 Product specification TDA4853; TDA4854 (4) (3) (5) A DATA parameter change takes effect MGM088 (3) ( ...

Page 34

... X = don’t care this bit is occupied by another function. If the register is addressed, the bit values for both functions must be transferred. 3. Bits STDBY and SOFTST can be reset by internal protection circuit. 1999 Jul 13 FUNCTION not activated activated 34 Product specification TDA4853; TDA4854 REGISTER ASSIGNMENT SAD (HEX ...

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Acrobat reader. white to force landscape pages to be ... 2 Table 5 List of I C-bus controlled functions and those accessible by pins; ...

Page 36

Acrobat reader. white to force landscape pages to be ... SAD FUNCTION NAME BITS (HEX) TDA4854 Vertical focus VFOCUS 3 0A Horizontal focus HFOCUS ...

Page 37

... Setting control bit SOFTST = 0 is the only way (except yes power-down via pin V (1) L4 Soft-down sequence: MGM078 See L4 of Fig.21 for starting the soft-down sequence. 37 Product specification TDA4853; TDA4854 < 8.6 V register SOFTST cannot be set C-bus 2 C-bus data transfer as follows leave the operating mode. CC ...

Page 38

... Decreasing the supply voltage below 8.1 V. 01H A P Standby mode: MBK382 38 TDA4853; TDA4854 Start the sequence by setting control bit SOFTST = 0 BDRV duty cycle decreases HDRV duty cycle decreases. Pins HDRV and BDRV are floating Continuous blanking at pin CLBL is active Pin HUNLOCK is floating PLL1 and PLL2 are disabled Register contents are kept in internal memory ...

Page 39

... All driver outputs are immediately disabled IC enters standby mode. 1999 Jul 8.1 V (1) L1 MGM079 2 Fig.22 I C-bus flow for any mode. shut-down: 39 Product specification TDA4853; TDA4854 soft-down sequency followed by a soft start sequence is generated 8.6 V internally. 8 enters standby mode. 8.6 V 8.1 V ...

Page 40

... V HDRV V HPLL2 SOFT START OTA 2 BIN V BOP 4 V BSENS BOP Feedback mode application. Fig.23 Application and timing for feedback mode. 40 Product specification TDA4853; TDA4854 ( BDRV S Q TR1 R Q INVERTING BUFFER DISCHARGE R5 t off(min) V RESTART(BSENS) V STOP(BSENS) MBG600 c. Waveforms for fault condition. ...

Page 41

... S OTA R DISCHARGE BOP BSENS C BSENS BOP Forward mode application. V BOP Fig.24 Application and timing for feed forward mode. 41 TDA4853; TDA4854 INVERTING HORIZONTAL BUFFER OUTPUT Q STAGE Q EHT transformer 3 V BDRV TR1 R3 t off (discharge time of C BSENS ) c. Waveforms for fault condition. ...

Page 42

... Start-up sequence. continuous blanking (pin 16 and 17) activated PLL2 soft-down sequence is triggered 8 data accepted from I video clamping pulse disabled 3 Shut-down sequence. Fig.25 Start-up sequence and shut-down sequence. 42 TDA4853; TDA4854 MGM082 continuous blanking off (1) PLL2 soft start/soft-down enabled 2 C-bus time MGM083 (2) 2 ...

Page 43

... HDRV/HFLB protection disabled 3.4 V BDRV duty cycle begins to decrease 2.8 V BDRV floating HDRV duty cycle begins to decrease 1 < 8 Product specification TDA4853; TDA4854 MGM084 continuous blanking off PLL2 enabled frequency detector enabled HDRV/HFLB protection enabled time > 8 MGM085 (1) (1) HDRV floating ...

Page 44

... HDRV/HFLB protection disabled 3.3 V BDRV duty cycle begins to decrease 3.0 V BDRV floating HDRV duty cycle begins to decrease 1.7 V HDRV floating < 8 Product specification TDA4853; TDA4854 MHB108 continuous blanking off PLL2 enabled frequency detector enabled HDRV/HFLB protection enabled time > 8 MHB109 (1) (1) time > ...

Page 45

... VOUT VCAP I – Which means -------------- – 1 Vertical linearity error = 1 max – -------------- 1999 Jul 13 X-ray latch triggered approximately 25 ms (1) I VOUT ( A) 415 ( 415 I I – -------------- I 0 Fig.29 Definition of vertical linearity error. 45 TDA4853; TDA4854 floating floating floating MGM087 MBG551 (3) ( VCAP Product specification ...

Page 46

... B-drive line in parallel to ground SMD For optimum performance of the TDA4853; TDA4854 the ground paths must be routed as shown. Only one connection to other grounds on the PCB is allowed. Note: The tracks for HDRV and BDRV should be kept separate. 1999 Jul 13 further connections to other components or ground paths are not allowed 2 ...

Page 47

... Philips Semiconductors 2 I C-bus autosync deflection controllers for PC/TV monitors INTERNAL PIN CONFIGURATION PIN SYMBOL 1 HFLB 2 XRAY 3 BOP 4 BSENS 1999 Jul 13 INTERNAL CIRCUIT 1 MBG562 Product specification TDA4853; TDA4854 MBG561 6.25 V 5.3 V MBG563 MBG564 ...

Page 48

... Philips Semiconductors 2 I C-bus autosync deflection controllers for PC/TV monitors PIN SYMBOL 5 BIN 6 BDRV 7 PGND power ground, connected to substrate 8 HDRV 9 XSEL EWDRV 1999 Jul 13 TDA4853; TDA4854 INTERNAL CIRCUIT 5 MBG565 6 MBG566 8 MGM089 MBK381 10 MGM090 108 11 108 MBG570 48 Product specification ...

Page 49

... Philips Semiconductors 2 I C-bus autosync deflection controllers for PC/TV monitors PIN SYMBOL 12 VOUT2 13 VOUT1 14 VSYNC 15 HSYNC 16 CLBL 1999 Jul 13 TDA4853; TDA4854 INTERNAL CIRCUIT MBG571 12 MBG572 13 100 1 7 MBG575 49 Product specification MBG573 1.4 V MBG574 ...

Page 50

... Philips Semiconductors 2 I C-bus autosync deflection controllers for PC/TV monitors PIN SYMBOL 17 HUNLOCK 18 SCL 19 SDA 20 ASCOR 21 VSMOD 1999 Jul 13 TDA4853; TDA4854 INTERNAL CIRCUIT 17 MGM091 18 MGM092 19 MGM093 480 20 MGM094 250 MGM095 50 Product specification ...

Page 51

... Philips Semiconductors 2 I C-bus autosync deflection controllers for PC/TV monitors PIN SYMBOL 22 VAGC 23 VREF 24 VCAP 25 SGND signal ground 26 HPLL1 27 HBUF 1999 Jul 13 TDA4853; TDA4854 INTERNAL CIRCUIT MBG582 24 MBG583 26 4 MGM097 51 Product specification MBG581 MGM096 ...

Page 52

... Philips Semiconductors 2 I C-bus autosync deflection controllers for PC/TV monitors PIN SYMBOL 28 HREF 29 HCAP 30 HPLL2 31 HSMOD 1999 Jul 13 INTERNAL CIRCUIT HFLB 250 31 52 Product specification TDA4853; TDA4854 2.525 V MBG585 6.25 V MGM098 5 V MGM099 ...

Page 53

... I C-bus autosync deflection controllers for PC/TV monitors PIN SYMBOL (1) 32 FOCUS Note 1. This pin is internally connected for TDA4853. Electrostatic discharge (ESD) protection pin Fig.31 ESD protection for pins 13, 16 and 17. 1999 Jul 13 INTERNAL CIRCUIT MBG559 Fig.32 ESD protection for pins Product specifi ...

Page 54

... Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC SOT232-1 1999 Jul scale (1) ( 1.3 0.53 0.32 29.4 9.1 0.8 0.40 0.23 28.5 8.7 REFERENCES JEDEC EIAJ 54 Product specification TDA4853; TDA4854 3.2 10.7 12.2 1.778 10.16 2.8 10.2 10.5 EUROPEAN PROJECTION SOT232-1 M ...

Page 55

... If the temperature of the soldering iron bit is less than 300 C it may remain in contact for seconds. If the bit temperature is between 300 and 400 C, contact may seconds. SOLDERING METHOD DIPPING suitable 55 Product specification TDA4853; TDA4854 ). If the stg(max) WAVE (1) suitable ...

Page 56

... I Philips. This specification can be ordered using the code 9398 393 40011. 1999 Jul components conveys a license under the Philips’ system provided the system conforms to the I 56 Product specification TDA4853; TDA4854 2 C patent to use the 2 C specification defined by ...

Page 57

... Philips Semiconductors 2 I C-bus autosync deflection controllers for PC/TV monitors 1999 Jul 13 TDA4853; TDA4854 NOTES 57 Product specification ...

Page 58

... Philips Semiconductors 2 I C-bus autosync deflection controllers for PC/TV monitors 1999 Jul 13 TDA4853; TDA4854 NOTES 58 Product specification ...

Page 59

... Philips Semiconductors 2 I C-bus autosync deflection controllers for PC/TV monitors 1999 Jul 13 TDA4853; TDA4854 NOTES 59 Product specification ...

Page 60

Philips Semiconductors – a worldwide company Argentina: see South America Australia: 3 Figtree Drive, HOMEBUSH, NSW 2140, Tel. +61 2 9704 8141, Fax. +61 2 9704 8139 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. + 101 ...

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