HT46R22 Holtek, HT46R22 Datasheet
HT46R22
Specifications of HT46R22
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HT46R22 Summary of contents
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... Supports PFD for sound generation HALT function and wake-up feature reduce power consumption General Description The HT46R22/HT46C22 are 8-bit, high performance, RISC architecture microcontroller devices specifically designed for A/D applications that interface directly to analog signals, such as those from sensors. The mask version HT46C22 is fully pin and functionally compatible with the OTP version HT46R22 device ...
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... Block Diagram Pin Assignment Rev. 2.00 HT46R22/HT46C22 2 November 23, 2005 ...
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... Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliabil- ity. Rev. 2.00 HT46R22/HT46C22 Description 2 C Bus function is used, the internal regis- +6.0V Storage Temperature ...
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... OL I I/O Port Source Current OH R Pull-high Resistance PH V A/D Input Voltage AD E A/D Conversion Error AD Additional Power Consumption I ADC if A/D Converter is Used Rev. 2.00 HT46R22/HT46C22 Test Conditions Min. Typ. V Conditions DD f =4MHz 2.2 SYS f =8MHz 3.3 SYS 3V 0.6 No load, f =4MHz ...
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... Interrupt Pulse Width INT t A/D Clock Period AD t A/D Conversion Time ADC t A/D Sampling Time ADCS Bus Clock Period IIC Note: *t =1/f SYS SYS Rev. 2.00 HT46R22/HT46C22 Test Conditions Min. Typ. V Conditions DD 2.2V~5.5V 400 3.3V~5.5V 400 2.2V~5.5V 0 3.3V~5. Wake-up from HALT ...
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... Note: *10~*0: Program counter bits #10~#0: Instruction code bits Rev. 2.00 HT46R22/HT46C22 cremented by 1. The program counter then points to the memory word containing the next instruction code. When executing a jump instruction, conditional skip ex- ecution, loading PCL register, subroutine call, initial re- ...
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... Note: *10~*0: Table location bits @7~@0: Table pointer bits Rev. 2.00 HT46R22/HT46C22 · Location 00CH This area is reserved for the A/D converter interrupt service program A/D converter interrupt results from an end of A/D conversion, and if the interrupt is enabled and the stack is not full, the program begins execution at location 00CH. · ...
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... Rev. 2.00 HT46R22/HT46C22 All of the data memory areas can handle arithmetic, logic, increment, decrement and rotate operations di- rectly. Except for some dedicated bits, each bit in the data memory can be set and reset by ² ...
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... WDT time-out Unused bit, read as 0 Rev. 2.00 HT46R22/HT46C22 the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flag. In addi- tion operations related to the status register may give different results from those intended ...
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... HIF I C Bus interrupt request flag (1=active; 0=inactive) 5~7 Unused bit, read as 0 Rev. 2.00 HT46R22/HT46C22 2 The I C Bus interrupt is initialized by setting the I interrupt request flag (HIF; bit 4 of INTC1), caused by a slave address match (HAAS byte of data transfer is completed. When the interrupt is enabled, the stack is not full and the HIF bit is set, a subroutine call to lo- cation 10H will occur ...
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... oscillator is used, an external resistor between OSC1 and VSS is required and the resistance must range from 30kW to 750kW. The system clock, divided Rev. 2.00 HT46R22/HT46C22 available on OSC2 with pull-high resistor, which can be used to synchronize external logic. The RC os- cillator provides the most cost effective solution. How- ...
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... All of the I/O ports maintain their original status. · The PDF flag is set and the TO flag is cleared. Rev. 2.00 HT46R22/HT46C22 The system can leave the HALT mode by means of an external reset, an interrupt, an external falling edge sig- nal on port WDT overflow. An external reset causes a device initialization and the WDT overflow per- forms a ² ...
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... Timer/Event Counter Off Input/Output ports Input mode Stack Pointer Points to the top of the stack Rev. 2.00 HT46R22/HT46C22 Reset Circuit Note: * Make the length of the wiring, which is con- nected to the RES pin as short as possible, to avoid noise interference. Reset Timing Chart Reset Configuration ...
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... ADCR 0100 0000 0100 0000 ACSR 1--- --00 1--- --00 Note: * stands for warm reset u stands for unchanged x stands for unknown Rev. 2.00 HT46R22/HT46C22 RES Reset RES Reset WDT Time-out (Normal Operation) (HALT) xxxx xxxx xxxx xxxx 00-0 1000 00-0 1000 000H 000H ...
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... TM1 11=Pulse width measurement mode 00=Unused Rev. 2.00 HT46R22/HT46C22 In the event count or timer mode, once the timer/event counter starts counting, it will count from the current contents in the timer/event counter to FFH. Once over- flow occurs, the counter is reloaded from the timer/event counter preload register and generates the interrupt re- quest flag (TF ...
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... There are 19 bidirectional input/output lines in the microcontroller, labeled as PA, PB, PC and PD, which are mapped to the data memory of [12H], [14H], [16H] Rev. 2.00 HT46R22/HT46C22 Timer/Event Counter and [18H] respectively. All of these I/O ports can be used for input and output operations. For input opera- ...
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... PWM signal will appear on PD0 (if PD0 is op- erating in output mode). Writing 1 to PD0 data register will enable the PWM output function and writing 0 will force the PD0 to remain The I/O functions of PD0 is as shown. Rev. 2.00 HT46R22/HT46C22 I/O I/P O/P Mode (Normal) ...
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... ADRH and ADRL should be read to get the conversion result data. The ADCR is an A/D converter control regis- ter, which defines the A/D channel number, analog Rev. 2.00 HT46R22/HT46C22 (6+2) PWM Mode (7+1) PWM Mode channel select, start A/D conversion control bit and the end of A/D conversion flag ...
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... PB7 PB7 AN7 ACS2 ACS1 Analog Input Channel Selection Rev. 2.00 HT46R22/HT46C22 Function ACSR (27H) Register Function ADCR (26H) Register PB6 PB5 PB4 PB3 PB2 PB6 PB5 PB4 PB3 PB2 PB6 PB5 PB4 PB3 PB2 PB6 PB5 PB4 PB3 AN2 PB6 ...
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... ACSR register to select f mov a,00100000B ; setup ADCR register to configure Port PB0~PB3 as A/D inputs mov ADCR,a ; and select AN0 to be connected to the A/D converter : ; As the Port B channel bits have changed the following START Rev. 2.00 HT46R22/HT46C22 Bit5 Bit4 Bit3 Bit2 the A/D clock ...
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... START set START ; reset A/D clr START ; start A EXIT_INT_ISR: mov a,status_stack mov STATUS,a ; restore STATUS from user defined memory mov a,acc_stack ; restore ACC from user defined memory reti Rev. 2.00 HT46R22/HT46C22 A/D Conversion Timing 21 November 23, 2005 ...
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... To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system clock pulses before entering the normal operation. *2: Since low voltage state has to be maintained in its original state for over 1ms, therefore after 1ms delay, the device enters the reset mode. Rev. 2.00 HT46R22/HT46C22 Bus Serial Interface Bus is implemented in the device ...
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... HDR. Transmit 2 or Receive data from I C Bus must be via the HDR reg- Rev. 2.00 HT46R22/HT46C22 ister. At the beginning of the transfer of the I device must initial the bus, the following are the notes for 2 initialing the I C Bus ...
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... Rev. 2.00 HT46R22/HT46C22 24 November 23, 2005 ...
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... SRW bit and sends an acknowl- edge bit (low level) to the 9th bit. The slave device also sets the status flag (HAAS), when the slave address is matched. Rev. 2.00 HT46R22/HT46C22 In interrupt subroutine, check HAAS bit to know whether 2 the I C Bus interrupt comes from a slave address that is matched or a data byte transfer is completed ...
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... Low voltage reset selection: Enable or disable LVR function Bus function: Enable or disable Rev. 2.00 HT46R22/HT46C22 master sends a STOP signal to release the I data is stored in the HDR register. The transmitter must write data to the HDR before transmit data and the re- ceiver must read data from the HDR after receiving data. ...
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... The resistance and capacitance for reset circuit should be designed in such a way as to ensure that the VDD is stable and remains within a valid operating voltage range before bringing RES to high. * Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise interference. Rev. 2.00 HT46R22/HT46C22 C1 0pF 10k ...
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... Move data memory to ACC MOV [m],A Move ACC to data memory MOV A,x Move immediate data to ACC Bit Operation CLR [m].i Clear bit of data memory SET [m].i Set bit of data memory Rev. 2.00 HT46R22/HT46C22 Instruction Description 28 Flag Cycle Affected 1 Z,C,AC,OV (1) 1 Z,C,AC,OV ...
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... The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared. Otherwise the TO and PDF flags remain unchanged. Rev. 2.00 HT46R22/HT46C22 Instruction Description 29 Flag Cycle Affected 2 None ...
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... Operation ACC ACC+x Affected flag(s) TO PDF ADDM A,[m] Add the accumulator to the data memory Description The contents of the specified data memory and the accumulator are added. The result is stored in the data memory. Operation [m] ACC+[m] Affected flag(s) TO PDF Rev. 2.00 HT46R22/HT46C22 ...
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... The indicated address is then loaded. Program execution continues with the instruction at this address. Operation Stack Program Counter+1 Program Counter Affected flag(s) TO PDF CLR [m] Clear data memory Description The contents of the specified data memory are cleared to 0. Operation [m] 00H Affected flag(s) TO PDF Rev. 2.00 HT46R22/HT46C22 addr ...
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... PDF and TO 0* Affected flag(s) TO PDF 0* 0* CPL [m] Complement data memory Description Each bit of the specified data memory is logically complemented (1 s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. Operation [m] [m] Affected flag(s) TO PDF Rev. 2.00 HT46R22/HT46C22 ...
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... Decrement data memory and place result in the accumulator Description Data in the specified data memory is decremented by 1, leaving the result in the accumula- tor. The contents of the data memory remain unchanged. Operation ACC [m] 1 Affected flag(s) TO PDF Rev. 2.00 HT46R22/HT46C22 (ACC.3~ACC.0)+6, AC1=AC (ACC.3~ACC.0), AC1=0 ACC.7~ACC.4+6+AC1,C=1 ACC.7~ACC.4+AC1,C ...
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... The program counter are replaced with the directly-specified address unconditionally, and control is passed to this destination. Operation Program Counter Affected flag(s) TO PDF MOV A,[m] Move data memory to the accumulator Description The contents of the specified data memory are copied to the accumulator. Operation ACC [m] Affected flag(s) TO PDF Rev. 2.00 HT46R22/HT46C22 Program Counter addr ...
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... ORM A,[m] Logical OR data memory with the accumulator Description Data in the data memory (one of the data memories) and the accumulator perform a bitwise logical_OR operation. The result is stored in the data memory. Operation [m] ACC OR [m] Affected flag(s) TO PDF Rev. 2.00 HT46R22/HT46C22 Program Counter ...
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... Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. The contents of the data memory remain unchanged. Operation ACC.(i+1) [m].i; [m].i:bit i of the data memory (i=0~6) ACC.0 [m].7 Affected flag(s) TO PDF Rev. 2.00 HT46R22/HT46C22 Stack Stack ...
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... The contents of the specified data memory and the carry flag are together rotated 1 bit right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position. Operation [m].i [m].(i+1); [m].i:bit i of the data memory (i=0~6) [m]. [m].0 Affected flag(s) TO PDF Rev. 2.00 HT46R22/HT46C22 ...
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... If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cy- cles). Otherwise proceed with the next instruction (1 cycle). Operation Skip if ([m] 1)=0, ACC Affected flag(s) TO PDF Rev. 2.00 HT46R22/HT46C22 ...
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... If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data memory is not 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Other- wise proceed with the next instruction (1 cycle). Operation Skip if [m].i 0 Affected flag(s) TO PDF Rev. 2.00 HT46R22/HT46C22 ([m]+1) ...
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... Swap data memory and place result in the accumulator Description The low-order and high-order nibbles of the specified data memory are interchanged, writ- ing the result to the accumulator. The contents of the data memory remain unchanged. Operation ACC.3~ACC.0 ACC.7~ACC.4 Affected flag(s) TO PDF Rev. 2.00 HT46R22/HT46C22 ...
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... Move the ROM code (last page) to TBLH and data memory Description The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to the data memory and the high byte transferred to TBLH directly. Operation [m] ROM code (low byte) TBLH ROM code (high byte) Affected flag(s) TO PDF Rev. 2.00 HT46R22/HT46C22 ...
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... TO PDF XOR A,x Logical XOR immediate data to the accumulator Description Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR op- eration. The result is stored in the accumulator. The 0 flag is affected. Operation ACC ACC XOR x Affected flag(s) TO PDF Rev. 2.00 HT46R22/HT46C22 November 23, 2005 ...
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... Package Information 24-pin SKDIP (300mil) Outline Dimensions Symbol Min. A 1235 B 255 C 125 D 125 295 I 345 0 Rev. 2.00 HT46R22/HT46C22 Dimensions in mil Nom. Max. 1265 265 135 145 20 70 100 315 360 15 43 November 23, 2005 ...
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... SOP (300mil) Outline Dimensions Symbol Min. A 394 B 290 C 14 590 Rev. 2.00 HT46R22/HT46C22 Dimensions in mil Nom. Max. 419 300 20 614 104 November 23, 2005 ...
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... Reel Dimensions SOP 24W Symbol Description A Reel Outer Diameter B Reel Inner Diameter C Spindle Hole Diameter D Key Slit Width T1 Space Between Flange T2 Reel Thickness Rev. 2.00 HT46R22/HT46C22 Dimensions in mm 330 1.0 62 1.5 13.0+0.5 0.2 2.0 0.5 24.8+0.3 0.2 30.2 0.2 45 November 23, 2005 ...
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... Cavity to Perforation (Length Direction) A0 Cavity Length B0 Cavity Width K0 Cavity Depth t Carrier Tape Thickness C Cover Tape Width Rev. 2.00 HT46R22/HT46C22 Dimensions in mm 24.0 0.3 12.0 0.1 1.75 0.1 11.5 0.1 1.55+0.1 1.5+0.25 4.0 0.1 2.0 0.1 10.9 0.1 15.9 0.1 3.1 0.1 ...
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... Holtek s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Rev. 2.00 HT46R22/HT46C22 47 November 23, 2005 ...