FM93C56LN Fairchild Semiconductor, FM93C56LN Datasheet

FM93C56LN

Manufacturer Part Number

FM93C56LN

Description

(MICROWIRE? Bus Interface) 2048-Bit Serial EEPROM with Data Protect and Sequential Read

Manufacturer

Fairchild Semiconductor

Datasheet

1.FM93C56LN.pdf (16 pages)

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FM93CS56 Rev. C.1

FM93CS56 is a 2048-bit CMOS non-volatile EEPROM organized

as 128 x 16-bit array. This device features MICROWIRE interface

which is a 4-wire serial bus with chipselect (CS), clock (SK), data

input (DI) and data output (DO) signals. This interface is compat-

ible to many of standard Microcontrollers and Microprocessors.

FM93CS56 offers programmable write protection to the memory

array using a special register called Protect Register. Selected

memory locations can be protected against write by programming

this Protect Register with the address of the first memory location

to be protected (all locations greater than or equal to this first

address are then protected from further change). Additionally, this

address can be “permanently locked” into the device, making all

future attempts to change data impossible. In addition this device

features “sequential read”, by which, entire memory can be read

in one cycle instead of multiple single byte read cycles. There are

10 instructions implemented on the FM93CS56, 5 of which are for

memory operations and the remaining 5 are for Protect Register

operations. This device is fabricated using Fairchild Semiconduc-

tor floating-gate CMOS process for high reliability, high endurance

and low power consumption.

“LZ” and “L” versions of FM93CS56 offer very low standby current

making them suitable for low power applications. This device is offered

in both SO and TSSOP packages for small space considerations.

INSTRUCTION

ADDRESS

DECODER

PROTECT

DATA IN/OUT REGISTER

DATA OUT BUFFER

READ/WRITE AMPS

EEPROM ARRAY

16 BITS

CONTROL LOGIC

GENERATORS

WRITE ENABLE

INSTRUCTION

COMPARATOR

AND CLOCK

DECODER

AND

I Wide V

I Programmable write protection

I Sequential register read

I Typical active current of 200µA

I No Erase instruction required before Write instruction

I Self timed write cycle

I Device status during programming cycles

I 40 year data retention

I Endurance: 1,000,000 data changes

I Packages available: 8-pin SO, 8-pin DIP, 8-pin TSSOP

10µA standby current typical

1µA standby current typical (L)

0.1µA standby current typical (LZ)

2.7V - 5.5V

HIGH VOLTAGE

GENERATOR

PROGRAM

TIMER

AND

PRE

www.fairchildsemi.com

July 2000

Related parts for FM93C56LN

FM93C56LN Summary of contents

Page 1

... SO and TSSOP packages for small space considerations INSTRUCTION DI REGISTER ADDRESS REGISTER DECODER DO © 2000 Fairchild Semiconductor International FM93CS56 Rev. C.1 I Wide V 2. Programmable write protection I Sequential register read I Typical active current of 200µA 10µA standby current typical 1µA standby current typical (L) 0.1µ ...

Page 2

FM93CS56 Rev. C PRE GND CS Chip Select SK Serial Data Clock DI Serial Data Input DO Serial Data Output GND ...

Page 3

Ambient Storage Temperature All Input or Output Voltages with Respect to Ground Lead Temperature (Soldering, 10 sec.) ESD rating I Operating Current CCA I Standby Current CCS I Input Leakage IL I Output Leakage OL V Input Low Voltage IL ...

Page 4

Ambient Storage Temperature All Input or Output Voltages with Respect to Ground Lead Temperature (Soldering, 10 sec.) ESD rating page 3 for V = 4.5V to 5.5V Operating Current CCA I Standby Current CCS L LZ (2.7V to ...

Page 5

This is an active high input pin to FM93CS56 EEPROM (the device) and is generated by a master that is controlling the device. A high level on this pin selects the device and a low level deselects the device. All ...

Page 6

A typical Microwire cycle starts by first selecting the device (bringing the CS signal high). Once the device is selected, a valid Start bit (“1”) should be issued to properly recognize the cycle. Following this, the 2-bit opcode of appropriate ...

Page 7

Write Disable (WDS) instruction disables all programming opera- tions and is recommended to follow all programming operations. Executing this instruction after a valid write instruction would protect against accidental data disturb due to spurious noise, glitches, inadvertent writes etc. Input ...

Page 8

Table1. After inputting the last bit of address (A0 bit), CS signal must be brought low before the next rising edge of the SK clock. This falling edge of the CS initiates the ...

Page 9

SYNCHRONOUS DATA TIMING CS t CSS SK t PRES PRE t PES PE t DIS Valid Input DI DO (Data Read (Status Read) NORMAL READ CYCLE (READ) PRE Star t ...

Page 10

WRITE ENABLE CYCLE (WEN) PRE ...

Page 11

WRITE ALL CYCLE (WRALL) PRE Star t Bit DO 93CS56: Address bits patter n -> 0-1-x-x-x-x-x-x; (x -> Don't Care, can Data bits patter n PROTECT REGISTER READ CYCLE (PRREAD) ...

Page 12

PROTECT REGISTER CLEAR CYCLE (PRCLEAR) PRE Star t Bit DO 93CS56: Address bits patter n -> 1-1-1-1-1-1-1-1 PROTECT REGISTER WRITE CYCLE (PRWRITE) PRE Star t Bit DO 93CS56: Address bits ...

Page 13

CLEARING READY STATUS PRE High - ...

Page 14

All lead tips Typ. All Leads FM93CS56 Rev. C.1 0.189 - 0.197 (4.800 ...

Page 15

Pin #1 IDENT 0.0433 Max (1.1) 0.0256 (0.65) Typ. Notes: Unless otherwise specified 1. Reference ...

Page 16

... Fairchild's products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of Fairchild Semiconductor Corporation. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support ...

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