MC68HC705J2P Motorola, MC68HC705J2P Datasheet

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MC68HC705J2P

Manufacturer Part Number
MC68HC705J2P
Description
HCMOS MICROCONTROLLER UNIT
Manufacturer
Motorola
Datasheet
MOTOROLA
SEMICONDUCTOR
TECHNICAL DATA
Technical Summary
8-Bit Microcontroller
The M68HC11 K-series microcontroller units (MCUs) are high-performance derivatives of the
MC68HC11F1 and have several additional features. The MC68HC11K0, MC68HC11K1,
MC68HC11K3, MC68HC11K4 and MC68HC711K4 comprise the series. These MCUs, with a nonmul-
tiplexed expanded bus, are characterized by high speed and low power consumption. Their fully static
design allows operation at frequencies from 4 MHz to dc.
This document contains information concerning standard, custom-ROM, and extended-voltage devic-
es. Standard devices include those with disabled ROM (MC68HC11K1), disabled EEPROM
(MC68HC11K3), disabled ROM and EEPROM (MC68HC11K0), or EPROM replacing ROM
(MC68HC711K4). Custom-ROM devices have a ROM array that is programmed at the factory to cus-
tomer specifications. Extended-voltage devices are guaranteed to operate over a much greater voltage
range (3.0 Vdc to 5.5 Vdc) at lower frequencies than the standard devices. Refer to the device ordering
information tables for details concerning these differences.
1 Features
• M68HC11 CPU
• Power Saving STOP and WAIT Modes
• 768 Bytes RAM (All Saved During Standby)
• 24 Kbytes ROM or EPROM
• 640 Bytes Electrically Erasable Programmable Read Only Memory (EEPROM)
• Optional Security Feature Protects Memory Contents
• On-Chip Memory Mapping Logic Allows Expansion to Over 1 Mbyte of Address Space
• PROG Mode Allows Use of Standard EPROM Programmer (27C256 Footprint)
• Nonmultiplexed Address and Data Buses
• Four Programmable Chip Selects with Clock Stretching (Expanded Modes)
• Enhanced 16-Bit Timer with Four-Stage Programmable Prescaler
— Three Input Capture (IC) Channels
— Four Output Compare (OC) Channels
— One Additional Channel, Selectable as Fourth IC or Fifth OC
• 8-Bit Pulse Accumulator
• Four 8-Bit or Two 16-Bit Pulse Width Modulation (PWM) Timer Channels
• Real-Time Interrupt Circuit
• Computer Operating Properly (COP) Watchdog
• Clock Monitor
• Enhanced Asynchronous Nonreturn to Zero (NRZ) Serial Communications Interface (SCI)
• Enhanced Synchronous Serial Peripheral Interface (SPI)
• Eight-Channel 8-Bit Analog-to-Digital (A/D) Converter
• Seven Bidirectional Input/Output (I/O) Ports (54 Pins)
• One Fixed Input-Only Port (8 Pins)
• Available in 84-Pin Plastic Leaded Chip Carrier (PLCC), 84-Pin Windowed Ceramic Leaded Chip
Carrier (CLCC), and 80-Pin Quad Flat Pack (QFP)
This document contains information on a new product. Specifications and information herein are subject to change without notice.
© MOTOROLA INC., 1997
Order this document
by MC68HC11KTS/D
M68HC11 K Series

Related parts for MC68HC705J2P

MC68HC705J2P Summary of contents

Page 1

... Available in 84-Pin Plastic Leaded Chip Carrier (PLCC), 84-Pin Windowed Ceramic Leaded Chip Carrier (CLCC), and 80-Pin Quad Flat Pack (QFP) This document contains information on a new product. Specifications and information herein are subject to change without notice. © MOTOROLA INC., 1997 Order this document by MC68HC11KTS/D ...

Page 2

... C – 105 C – 125 C – – 105 C – 125 C – – 105 C – 125 C 80-Pin QFP – ( – mm) – 105 C – – 105 C MOTOROLA 2 CONFIG Description $DF BUFFALO ROM $DD No ROM $DD No ROM $DD No ROM $DC No ROM, No EEPROM $DC No ROM, No EEPROM $DC ...

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... MHz Frequency MC Order Number 2 MHz MC68HC711K4CFS2 3 MHz MC68HC711K4CFS3 4 MHz MC68HC711K4CFS4 2 MHz MC68HC711K4VFS2 3 MHz MC68HC711K4VFS3 4 MHz MC68HC711K4VFS4 2 MHz MC68HC711K4MFS2 3 MHz MC68HC711K4MFS3 4 MHz MC68HC711K4MFS4 MC Order Number MC68L11K4FN1 MC68L11K4FN3 MC68L11K1FN1 MC68L11K1FN3 MC68L11K0FN1 MC68L11K0FN3 MC68L11K3FN1 MC68L11K3FN3 MC68L11K4FU1 MC68L11K4FU3 MC68L11K1FU1 MC68L11K1FU3 MC68L11K0FU1 MC68L11K0FU3 MC68L11K3FU1 MC68L11K3FU3 MOTOROLA 3 ...

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... Table 3 Custom ROM Device Ordering Information Package Temperature 84-Pin PLCC – – 105 C – 125 C – – 105 C – 125 C 80-Pin QFP – – 105 C – – 105 C MOTOROLA 4 Description Frequency Custom ROM 2 MHz 3 MHz 4 MHz Custom ROM 2 MHz 3 MHz 4 MHz Custom ROM 2 MHz 3 MHz ...

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... Pins 20, 22, and 25 are used only during factory testing and should not be connected to external circuitry PPE applies only to devices with EPROM. Figure 1 Pin Assignments for 84-Pin PLCC/CLCC M68HC11 K Series MC68HC11KTS/D 1 MC68HC11K SERIES 74 PD2/MISO 73 PD1/TxD 72 PD0/RxD 71 MODA/LIR 70 MODB/V STBY 69 RESET 68 XTAL 67 EXTAL 66 XOUT PC7/DATA7 PC6/DATA6 61 60 PC5/DATA5 59 PC4/DATA4 58 PC3/DATA3 57 PC2/DATA2 56 PC1/DATA1 55 PC0/DATA0 54 IRQ MOTOROLA 5 ...

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... PD4/SCK 2 PD5/SS 3 PA7/PAI/OC1 4 PA6/OC2/OC1 5 PA5/OC3/OC1 6 PA4/OC4/OC1 7 PA3/OC5/IC4/OC1 8 PA2/IC1 9 PA1/IC2 10 PA0/IC3 PB7/ADDR15 14 PB6/ADDR14 15 PB5/ADDR13 16 PB4/ADDR12 17 PB3/ADDR11 18 PB2/ADDR10 19 PB1/ADDR9 20 Figure 2 Pin Assignments for 80-Pin TQFP MOTOROLA 6 MC68HC11K SERIES 60 PF0/ADDR0 59 PF1/ADDR1 58 PF2/ADDR2 57 PF3/ADDR3 56 PF4/ADDR4 55 PF5/ADDR5 54 PF6/ADDR6 53 PF7/ADDR7 PE0/AN0 48 PE1/AN1 47 PE2/AN2 46 PE3/AN3 45 PE4/AN4 44 PE5/AN5 43 PE6/AN6 ...

Page 7

... CSIO PH4 PW4 PH3 PW3 PH2 PWM PW2 PH1 PW1 PH0 SS PD5 SCK PD4 SPI MOSI PD3 MISO PD2 PD1 TxD SCI RxD PD0 MEMORY PG7 EXPANSION PG6 XA18 PG5 XA17 PG4 PG3 XA16 XA15 PG2 XA14 PG1 XA13 PG0 MOTOROLA 7 ...

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... Examples of Memory Expansion Using Chip Selects .....................................................35 5 Resets and Interrupts 6 Parallel Input/Output 7 Serial Communications Interface 8 Serial Peripheral Interface 9 Analog-to-Digital Converter 10 Main Timer 10.1 Real-Time Interrupt ...................................................................................................................70 11 Pulse Accumulator 12 Pulse-Width Modulation Timer 12.1 PWM Boundary Cases ..............................................................................................................78 MOTOROLA 8 TABLE OF CONTENTS Page M68HC11 K Series MC68HC11KTS/D ...

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... MOTOROLA 9 ...

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... Timer Control 2 TFLG2 Timer Interrupt Flag 2 TI4/O5 Timer Input Capture 4/Output Compare 5 TMSK1 Timer Interrupt Mask 1 TMSK2 Timer Interrupt Mask 2 TOC1–TOC4 Timer Output Compare MOTOROLA 10 $0064–$0067 $006C–$006F $0063 $0068–$006B $0061 $0062 S $0070, $0071 $0072 ...

Page 11

... HPRIO —Highest Priority I-Bit Interrupt and Miscellaneous Bit RBOOT* SMOD* MDA* RESET *The reset values of RBOOT, SMOD, and MDA depend on the mode selected at power up. M68HC11 K Series MC68HC11KTS PSEL4 PSEL3 PSEL2 PSEL1 PSEL0 $003C Bit 0 0 Single Chip 0 Expanded 0 Bootstrap 0 Special Test MOTOROLA 11 ...

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... In single-chip modes this bit determines whether the E clock drives out from the chip driven out from the chip pin is driven low. Refer to the following table. Mode IRVNE Out of Reset Single Chip 0 Expanded 0 Boot 0 Special Test 1 MOTOROLA 12 Mode Single Chip Expanded Bootstrap Special Test — IRVNE* LSBF ...

Page 13

... Controls the frequency of the clock driven out of the XOUT pin XDV XOUT = EXTAL [1:0] Divided M68HC11 K Series MC68HC11KTS/D Frequency at Frequency at EXTAL = 8 MHz EXTAL = 12 MHz 8 MHz 12 MHz 2 MHz 3 MHz 1.3 MHz 2 MHz 1 MHz 1.5 MHz Frequency at EXTAL = 16 MHz 16 MHz 4 MHz 2.7 MHz 2 MHz MOTOROLA 13 ...

Page 14

... EXT $A000 $FFFF SINGLE EXPANDED BOOTSTRAP CHIP NOTE: ROM/EPROM can be enabled in special test mode by setting ROMON bit in the config register after reset. MOTOROLA 14 128-BYTE REGISTER BLOCK x000 (CAN BE REMAPPED TO ANY x07F 4K PAGE BY THE INIT REGISTER) x080 EXT 768 BYTES RAM ...

Page 15

... PORTC DDC1 DDC0 DDRC PD1 PD0 PORTD DDD1 DDD0 DDRD PE1 PE0 PORTE 0 0 CFORC 0 0 OC1M 0 0 OC1D 9 Bit 8 TCNT (High) 1 Bit 0 TCNT (Low) 9 Bit 8 TIC1 (High) 1 Bit 0 TIC1 (Low) 9 Bit 8 TIC2 (High) 1 Bit 0 TIC2 (Low) 9 Bit 8 TIC3 (High) MOTOROLA 15 ...

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... EE3 EE2 $0038 LIRDV CWOM $0039 ADPU CSEL IRQE $003A Bit 7 6 $003B ODD EVEN LVPI $003C RBOOT SMOD MDA $003D RAM3 RAM2 RAM1 $003E TILOP 0 OCCR $003F ROMAD 1 CLKX $0040 to $0055 $0056 MXGS2 MXGS1 W2SZ1 $0057 W2A15 W2A14 W2A13 MOTOROLA ...

Page 17

... Bit 0 PWDTY2 1 Bit 0 PWDTY3 1 Bit 0 PWDTY4 SBR9 SBR8 SCBDH SBR1 SBR0 SCBDL PE PT SCCR1 RWU SBK SCCR2 FE PF SCSR1 0 RAF SCSR2 0 0 SCDRH R1/T1 R0/T0 SCDRL Reserved Reserved PH1 PH0 PORTH DDH1 DDH0 DDRH PG1 PG0 PORTG DDG1 DDG0 DDRG MOTOROLA 17 ...

Page 18

... ELAT bit. 2. Write data to the desired address. 3. Turn on programming voltage to the EPROM array by setting the EPGM bit in EPROG register. 4. Delay for more, as appropriate. 5. Clear the EPGM bit in EPROG to turn off the programming voltage. MOTOROLA 18 ) applied to this pin protects all 768 bytes of RAM ...

Page 19

... MC6HC11KTS/D before verifying the data that was just programmed PPE CAUTION pin, the IRQ/CE pin must be pulled high to avoid acci- PPE ELAT EXCOL EXROW — STBY pin during PPE pin has a high voltage detect circuit $002B 1 Bit 0 — EPGM 0 0 MOTOROLA 19 , ...

Page 20

... EXROW can be written in special modes only. Bits [2:1] —Not implemented Always read zero EPGM —EPROM Programming Voltage Enable EPGM can be read any time and can only be written when ELAT = Programming voltage to EPROM array disconnected 1 = Programming voltage to EPROM array connected MOTOROLA 20 M68HC11 K Series MC6HC11KTS/D ...

Page 21

... MC68HC711K4 PE7/AN7 PH0/PW1 PH1/PW2 PH2/PW3 PH3/PW4 PH4/CSIO PH5/CSGP1 PH6/CSGP2 PH7/CSPROG EXTAL XTAL XOUT E TESTxx (3) MODA/LIR MODB/V STBY RESET NOTE 2 UNUSED INPUTS GND GND GND GND GND GND NOTE 1 GND GND GND GND GND UNUSED NOTE 3 OUTPUTS GND GND NOTE 4 GND MOTOROLA 21 ...

Page 22

... Care must be taken to ensure that EEPROM resources will not be needed by any routines in the code during the 10 ms program/erase time. PPROG —EEPROM Programming Control Bit 7 6 ODD EVEN RESET MOTOROLA 22 CAUTION LVPI BYTE ROW ERASE ...

Page 23

... M68HC11 K Series MC6HC11KTS/D DD returns to a safe operating voltage or if LVPEN bit in DD ROW Action 0 Bulk Erase (All 640 Bytes) 1 Row Erase (16 Bytes) 0 Byte Erase 1 Byte Erase PTCON BPRT3 BPRT2 NOTE has fallen below a safe operating $0035 1 Bit 0 BPRT1 BPRT0 1 1 MOTOROLA 23 ...

Page 24

... Unused bits always read as ones. In normal modes (SMOD = 0), CONFIG bits can only be written using the EEPROM programming se- quence, and are neither readable nor active until latched via the next reset. In special modes (SMOD = 1), CONFIG bits can be written at any time. MOTOROLA 24 Block Protected Block Size $xF80– ...

Page 25

... Although the security feature can easily be disabled when in bootstrap mode, the bootloader firmware residing in bootstrap ROM checks to see if the NOSEC bit is clear. If NOSEC is clear (security enabled), the bootloader program performs the following: M68HC11 K Series MC6HC11KTS CLKX PAREN NOSEC NOCOP — — — — $003F 1 Bit 0 ROMON EEON — — MOTOROLA 25 ...

Page 26

... At this time, devices with the security enhancement are only available as one-time-programmable (OTP) MCUs in non-windowed packages. Once they have been programmed and secured, they will not function in bootstrap mode. For more information refer to M68HC11 Reference Manual (M68HC11RM/AD). MOTOROLA 26 M68HC11 K Series MC6HC11KTS/D ...

Page 27

... CPU 64-Kbyte address range. The MM- SIZ register sets the size of the windows in use and selects whether the on-board general-purpose chip selects are active for CPU addresses or for expansion addresses. M68HC11 K Series MC68HC11KTS/D MOTOROLA 27 ...

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... General-purpose chip select based on 64 Kbyte CPU address 1 = General-purpose chip select based on expansion address W2SZ[1:0] — Window 2 Size These bits select the size of memory expansion window 2. Refer to the table following W1SZ[1:0]. Bits [3:2] — Not implemented Always read zero MOTOROLA 28 Window Size 16 Kbytes ADDR[13:0] XA14 ...

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... NOTE X1A16 X1A15 X1A14 X1A13 X2A16 X2A15 X2A14 X2A13 $0057 1 Bit 0 W1A13 — $0000 $0000 $4000 $4000 $8000 $8000 $8000 $8000 $0058–$0059 1 Bit 0 — MM1CR — MM2CR 0 0 MOTOROLA 29 ...

Page 30

... Kbyte memory space or in the expanded memory space. Chip select signals are a shared func- tion of port H. When an MCU pin is not used for chip select functions it can be used for general-purpose I/O. The following table contains a summary of the attributes of each chip select that can be controlled by user software. MOTOROLA 30 M68HC11 K Series MC68HC11KTS/D ...

Page 31

... G2DPC in GPCS2C allows CSGP2 and CSPROG to be connected to an internal OR gate and driven out the CSPROG pin. MXGS2 in MMSIZ allows CSGP2 to follow either 64K CPU addresses or 512K expansion addresses. MXGS1 in MMSIZ allows CSGP1 to follow either 64K CPU addresses or 512K expansion addresses. MOTOROLA 31 ...

Page 32

... IOEN IOPL RESET IOEN —I/O Chip Select Enable 0 = CSIO disabled 1 = CSIO enabled IOPL —I/O Chip Select Polarity Select 0 = CSIO active low 1 = CSIO active high MOTOROLA 32 Priority GPCS1 GPCS1 GPCS2 GPCS1 GCSPR = 1 On-Chip Registers On-Chip RAM Bootloader ROM On-Chip EEPROM On-Chip ROM/EPROM ...

Page 33

... Bit [A:B] Clock Stretch 0 0 None Cycle Cycles Cycles G1A16 G1A15 G1A14 G1A13 Address Range $0000–$FFFF $8000–$FFFF $C000–$FFFF $E000–$FFFF $005A Bit 0 1 Normal Modes 0 Special Modes $005C 1 Bit 0 G1A12 G1A11 0 0 MOTOROLA 33 ...

Page 34

... GPCS2A —General-Purpose Chip Select 2 Address Bit 7 6 G2A18 G2A17 RESET G2A[18:11] —General-Purpose Chip Select 2 Address Selects the Starting Address of General-Purpose Chip Select 2 Range. Refer to G2SZA–G2SZD table. GPCS2C —General-Purpose Chip Select 2 Control Bit 7 6 — G2DPC RESET MOTOROLA G1POL G1AV G1SZA G1SZB Size (Bytes) 0 Disabled ...

Page 35

... Disabled None ADDR[15:11 ADDR[15:12 ADDR[15:13 ADDR[15:14 ADDR15 None 1 128 K None 0 256 K None 1 512 K None 0 Follow Window 1 None 1 Follow Window 2 None Default to 512 K None Valid Bits (MXGS2 = 1) None G2A[18:11] G2A[18:12] G2A[18:13] G2A[18:14] G2A[18:15] G2A[18:16] G2A[18:17] G2A18 None None None None MOTOROLA 35 ...

Page 36

... In addition, a second window consisting of 16 banks of 16 Kbytes each uses the second chip select signal. Window 1 contains 64 Kbytes of expanded memory pages, window 2 contains a total of 256 Kbytes of expanded memory. A total of five expansion address lines are used. Register values par- ticular to this example are given below the diagram. MOTOROLA 36 WINDOW 1 $04000 ...

Page 37

... GPCS2A = $00 GEN. PURPOSE CHIP SELECT 2 FROM $00000 GPCS2C = $08 256 KBYTE RANGE (16 X 16K) $0A000 $0C000 $0E000 BANK 5 BANK 6 BANK 7 XA[15:13]= XA[15:13]= XA[15:13]= 1:0:1 1:1:0 1:1:1 $0BFFF $0DFFF $0FFFF $3C000 • • • • • • • BANK 15 XA[17:14]= 1:1:1:1 $3FFFF MOTOROLA 37 ...

Page 38

... SCI status register to check for receive errors, then to read the received data from the SCI data register. These two steps satisfy the automatic clearing mechanism without requiring any special instructions. Refer to the following table for a list of interrupt and reset vector assignments. MOTOROLA 38 M68HC11 K Series MC68HC11KTS/D ...

Page 39

... I PAOVI 16 I TOI 15 I I4/O5I 14 I OC4I 13 I OC3I 12 I OC2I 11 I OC1I 10 I IC3I 9 I IC2I 8 I IC1I 7 I RTII 6 I None 5 X None 4 None None * None None * None NOCOP 3 None CME 2 None None 1 $0039 1 Bit 0 CR1* CR0 MOTOROLA 39 ...

Page 40

... SMOD, and MDA reset depend on power-up initialization mode and can only be written in special mode. RBOOT —Read Bootstrap ROM Refer to 2 Operating Modes. SMOD —Special Mode Select Refer to 2 Operating Modes. MDA —Mode Select A Refer to 2 Operating Modes. MOTOROLA 40 XTAL = 12.0 MHz Timeout Timeout –0 ms, +10.9 ms 16.384 ms 10 ...

Page 41

... Timer Output Compare Timer Output Compare 5/Input Capture Timer Overflow 0 1 Pulse Accumulator Overflow 1 0 Pulse Accumulator Input Edge 1 1 SPI Serial Transfer Complete 0 0 SCI Serial System 0 1 Reserved (Default to IRQ Reserved (Default to IRQ Reserved (Default to IRQ Reserved (Default to IRQ) MOTOROLA 41 ...

Page 42

... Note that even when PA7 is configured as an output, the pin still drives the pulse accumulator input. DDRA —Data Direction Register for Port A Bit 7 6 DDA7 DDA6 RESET DDA[7:0] —Data Direction for Port Corresponding pin configured for input 1 = Corresponding pin configured for output MOTOROLA 42 Output Pins Bidirectional Pins — 8 — 8 — 8 — 6 — ...

Page 43

... PC2 PC5 PC4 PC3 PC2 DATA4 DATA3 DATA2 DDC5 DDC4 DDC3 DDC2 $0004 1 Bit 0 PB1 PB0 PB1 PB0 I I ADDR9 ADDR8 $0002 1 Bit 0 DDB1 DDB0 0 0 $0006 1 Bit 0 PC1 PC0 PC1 PC0 0 0 DATA1 DATA0 $0007 1 Bit 0 DDC1 DDC0 0 0 MOTOROLA 43 ...

Page 44

... If the SPI system is enabled and expects any of bits [4: input that bit will be an input regardless of the state of the associated DDR bit. If any of bits [4:2] are expected to be outputs that bit will be an output only if the associated DDR bit is set. MOTOROLA ...

Page 45

... Refer to 7 Serial Communications Interface. ILT —Idle Line Type Refer to 7 Serial Communications Interface. PE —Parity Enable Refer to 7 Serial Communications Interface. M68HC11 K Series MC68HC11KTS MSTR CPOL CPHA SPR1 WAKE ILT $0028 Bit 0 SPR0 0 Boot Mode 0 Other Modes $0072 Bit Boot Mode 0 Other Modes MOTOROLA 45 ...

Page 46

... PH7 to be configured as CSPROG. DDRH —Data Direction Register for Port H Bit 7 6 DDH7 DDH6 RESET DDH[7:0] —Data Direction for Port Bits set to zero to configure corresponding I/O pin for input only 1 = Bits set to one to configure corresponding I/O pin for output MOTOROLA PE5 PE4 PE3 PE2 I I ...

Page 47

... M68HC11 K Series MC68HC11KTS/D NOTE PG5 PG4 PG3 PG2 XA18 XA17 XA16 XA15 DDG5 DDG4 DDG3 DDG2 PGAR4 PGAR3 PGAR2 NOTE $007E 1 Bit 0 PG1 PG0 I I XA14 XA13 $007F 1 Bit 0 DDG1 DDG0 0 0 $002D 1 Bit 0 PGAR1 PGAR0 0 0 MOTOROLA 47 ...

Page 48

... Pin Pull-Up Enable Valid only when PAREN = 1. Refer to PAREN bit in the CONFIG register description Port x pin on-chip pull-up devices disabled 1 = Port x pin on-chip pull-up devices enabled FPPUE and BPPUE have no effect in expanded mode because port F and port B are address outputs. MOTOROLA — ...

Page 49

... The enhanced baud rate generator is shown in the following diagram. Refer to Table 7 for standard val- ues. 13-BIT COUNTER EXTAL 13-BIT COMPARE SCBDH/L SCI BAUD CONTROL Figure 9 SCI Baud Generator Circuit Diagram M68HC11 K Series MC68HC11KTS/D INTERNAL PHASE 2 CLOCK RESET SYNCH = 2 RECEIVER BAUD RATE CLOCK TRANSMITTER 16 BAUD RATE CLOCK MOTOROLA 49 ...

Page 50

... TRANSMITTER BAUD RATE SCDR Tx BUFFER CLOCK 10 (11) - BIT Tx SHIFT REGISTER H ( SCCR1 SCI CONTROL 1 SCI Rx SCI INTERRUPT REQUESTS REQUEST Figure 10 SCI Transmitter Block Diagram MOTOROLA 50 (WRITE ONLY) 8 FORCE PIN DIRECTION (OUT) TRANSMITTER CONTROL LOGIC SCSR INTERRUPT STATUS TDRE TIE TC TCIE SCCR2 SCI CONTROL 2 ...

Page 51

... PARITY DETECT SCSR1 SCI STATUS 1 RDRF RIE IDLE ILIE OR RIE SCCR2 SCI CONTROL 2 10 (11) - BIT MSB ALL ONES RWU R8 T8 – – – – – – $x076 SCDRH Tx/Rx DATA HIGH $x077 SCDRL Tx/Rx DATA LOW (READ-ONLY) INTERNAL DATA BUS MOTOROLA 51 ...

Page 52

... K 13 38.4 K — SCCR1 —SCI Control 1 Bit LOOPS WOMS — RESET MOTOROLA SBR12 SBR11 SBR10 SBR9 SBR4 SBR3 SBR2 SBR1 BR)] Crystal Frequency (EXTAL) 12 MHz Dec Value Hex Value $08E0 3409 $0D51 $0682 ...

Page 53

... SCI interrupt requested when RDRF flag or the OR status flag is set ILIE —Idle Line Interrupt Enable 0 = IDLE interrupts disabled 1 = SCI interrupt requested when IDLE status flag is set TE —Transmitter Enable 0 = Transmitter disabled 1 = Transmitter enabled M68HC11 K Series MC68HC11KTS RIE ILIE $0073 1 Bit 0 RWU SBK 0 0 MOTOROLA 53 ...

Page 54

... NF is set if majority sample logic detects anything other than a unanimous decision. Clear NF by reading SCSR1 and then reading SCDR Unanimous decision 1 = Noise detected FE —Framing Error FE is set when a zero is detected where a stop bit was expected. Clear the FE flag by reading SCSR1 and then reading SCDR Stop bit detected 1 = Zero detected MOTOROLA RDRF IDLE OR NF ...

Page 55

... R/T[7:0] —Receiver/Transmitter Data Bits [7:0] SCI data is double buffered in both directions. M68HC11 K Series MC68HC11KTS — — — — — — — — R5/T5 R4/T4 R3/T3 R2/T2 $0075 1 Bit 0 — RAF 0 0 $0076, $0077 1 Bit 0 — — SCDRH (High) R1/T1 R0/T0 SCDRL (Low) MOTOROLA 55 ...

Page 56

... SPI baud rate clock divider. INTERNAL MCU CLOCK DIVIDER 128 SPI CLOCK (MASTER) SELECT OPTIONS REGISTER 2 SPI CONTROL SPSR SPI STATUS REGISTER SPI INTERRUPT REQUEST MOTOROLA 56 MSB LSB 8-BIT SHIFT REGISTER READ DATA BUFFER CLOCK CLOCK LOGIC MSTR SPE SPIE ...

Page 57

... SAMPLE INPUT (CPHA = 1) DATA OUT MSB SS (TO SLAVE) This figure shows transmission order when LSBF = 0 default. If LSBF = 1, data is transferred in reverse order (LSB first). M68HC11 K Series MC68HC11KTS MSTR CPOL CPHA Figure 13 SPI Transfer Format NOTE $0028 1 Bit 0 SPR1 SPR0 LSB 2 1 LSB MOTOROLA 57 ...

Page 58

... SS pulled low in master mode Bits [3:0] —Not implemented Always read zero SPDR —SPI Data Bit 7 6 Bit 7 6 SPI is double buffered in, single buffered out. MOTOROLA 58 Table 8 SPI Clock Rate Selects Frequency at Frequency MHz (Baud MHz (Baud) 1.0 MHz 500 kHz 125 kHz 62 ...

Page 59

... SPI data transferred LSB first SPR2 —SPI Clock (SCK) Rate Select Adds a divide by four prescaler to SPI clock chain. Refer to SPCR register. XDV[1:0] —XOUT Clock Divide Select Refer to 2 Operating Modes. M68HC11 K Series MC68HC11KTS — IRVNE LSBF SPR2 0 — $0038 1 Bit 0 XDV1 XDV0 0 0 MOTOROLA 59 ...

Page 60

... The A/D converter can operate in single or multiple conversion modes. Multiple conversions are per- formed in sequences of four. Sequences can be performed on a single channel group of chan- nels. Dedicated lines V and MOTOROLA 60 8-BIT CAPACITIVE DAC WITH SAMPLE AND HOLD SUCCESSIVE APPROXIMATION REGISTER AND CONTROL ADCTL A/D CONTROL ...

Page 61

... CHANNEL CHANNEL AND UPDATE ADDR3 64 DIFFUSION AND POLY COUPLER 400 nA ~ – 0.7 V JUNCTION LEAKAGE BIT 2 BIT 1 LSB CYC CYC CYC CYC END REPEAT SEQUENCE IF SCAN = 1 SET CCF FLAG CONVERT FOURTH CHANNEL AND UPDATE ADDR4 96 128 E CYCLES * ~ 20 pF DAC CAPACITANCE V RL MOTOROLA 61 ...

Page 62

... ADR[4:1] —A/D Results $0031 Bit 7 6 $0032 Bit 7 6 $0033 Bit 7 6 $0034 Bit 7 6 MOTOROLA SCAN MULT Channel Signal AN0 0 1 AN1 1 0 AN2 1 1 AN3 0 0 AN4 0 1 AN5 1 0 AN6 1 1 AN7 0 0 Reserved ...

Page 63

... Refer to 5 Resets and Interrupts CME —Clock Monitor Enable Refer to 5 Resets and Interrupts FCME —Force Clock Monitor Enable Refer to 5 Resets and Interrupts CR[1:0] —COP Timer Rate Select Refer to 10 Main Timer M68HC11 K Series MC68HC11KTS IRQE* DLY* CME FCME $0039 1 Bit 0 CR1* CR0 MOTOROLA 63 ...

Page 64

... CR[1:0] COP Watchdog Timeout Rates (Period Length 16.384 65.536 262. 1.049 s Timeout Tolerance (–0 ms/+...) 16.4 ms MOTOROLA 64 Table 10 Timer Summary Common System Frequencies 12.0 MHz 3.0 MHz Main Timer Count Rates (Period Length) 333 ns 21.845 ms 1.333 s 87.381 ms 2.667 s 174.76 ms 5.333 s 349. ...

Page 65

... INTERRUPT REQUESTS (FURTHER QUALIFIED BY I-BIT IN CCR) PIN FUNCTIONS 8 PA7/ OC1/ BIT-7 PAI 7 PA6/ OC2/ BIT-6 OC1 6 PA5/ OC3/ BIT-5 OC1 5 PA4/ BIT-4 OC4/ OC1 4 PA3 OC5/ BIT-3 IC4/ OC1 PA2/ 3 BIT-2 IC1 PA1/ 2 BIT-1 IC2 PA0/ 1 BIT-0 IC3 PORT A PIN CONTROL MOTOROLA 65 ...

Page 66

... Bit TCNT resets to $0000. In normal modes, TCNT is read only. TIC1–TIC3 —Timer Input Capture $0010 Bit $0011 Bit $0012 Bit $0013 Bit $0014 Bit $0015 Bit TICx not affected by reset MOTOROLA FOC3 FOC4 FOC5 OC1M5 OC1M4 OC1M3 OC1D5 OC1D4 OC1D3 ...

Page 67

... Bit 8 High TOC1 Bit 0 Low Bit 8 High TOC2 Bit 0 Low Bit 8 High TOC3 Bit 0 Low Bit 8 High TOC4 Bit 0 Low $001E–$001F 9 Bit 8 High 1 Bit 0 Low $0020 1 Bit 0 OM5 OL5 0 0 $0021 1 Bit 0 EDG3B EDG3A 0 0 MOTOROLA 67 ...

Page 68

... Timer overflow interrupt disabled 1 = Timer overflow interrupt enabled RTII —Real-Time Interrupt Enable 0 = RTIF interrupts disabled 1 = Interrupt requested when RTIF is set to one. PAOVI —Pulse Accumulator Overflow Interrupt Enable Refer to 11 Pulse Accumulator. PAII —Pulse Accumulator Interrupt Enable Refer to 11 Pulse Accumulator. MOTOROLA OC4I I4/O5I IC1I ...

Page 69

... Always read zero PAEN —Pulse Accumulator System Enable Refer to 11 Pulse Accumulator. PAMOD —Pulse Accumulator Mode Refer to 11 Pulse Accumulator. M68HC11 K Series MC68HC11KTS/D NOTE PR[1:0] Prescaler PAIF — — PEDGE — I4/ $0025 1 Bit 0 — — $0026 1 Bit 0 RTR1 RTR0 0 0 MOTOROLA 69 ...

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... RTR[1:0] Selected Table 13 Real-Time Interrupt Rates (Frequency) RTR[1:0] Rate Selected MOTOROLA 70 13 rate clock compensated so that it is inde- Period Length E = 2.0 MHz 4.096 ms E 8.192 ms 16.384 ms 32.768 2.0 MHz 13 244.141 Hz 14 122.070 Hz 61.035 30.518 3.0 MHz E = 4.0 MHz 2.731 ms 2.048 ms 5.461 ms 4 ...

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... TFLG2 INTERRUPT STATUS PAI EDGE PAEN 2:1 CLOCK MUX DATA BUS PAEN INTERNAL DATA BUS 16.0 MHz 4.0 MHz 250 ns 16.0 s 4.096 ms PAOVI 1 PAOVF INTERRUPT REQUESTS PAII 2 PAIF DISABLE FLAG SETTING OVERFLOW PACNT 8-BIT COUNTER ENABLE MOTOROLA 71 ...

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... Refer to 10 Main Timer. PAOVF —Pulse Accumulator Overflow Flag Set when PACNT changes from $FF to $00 PAIF —Pulse Accumulator Input Edge Flag Set each time a selected active edge is detected on the PAI input line Bits [3:0] —Not implemented Always read zero MOTOROLA PAOVI PAII — ...

Page 73

... I4/O5 —Input Capture 4/Output Compare 5 Refer to 10 Main Timer. RTR[1:0] —Real-Time Interrupt Rate Refer to 10 Main Timer. PACNT —Pulse Accumulator Counter Bit 7 6 Bit 7 6 Can be read and written. M68HC11 K Series MC68HC11KTS PEDGE — I4/ $0026 1 Bit 0 RTR1 RTR0 0 0 $0027 1 Bit 0 1 Bit 0 MOTOROLA 73 ...

Page 74

... MHz, PWM periods greater than one minute are possible. In 16-bit mode, duty cycle resolution of almost 15 parts per million can be achieved (at a PWM frequen about 60 Hz). In the same system, a PWM frequency of 1 kHz corresponds to a duty cycle reso- lution of 0.025%. MOTOROLA 74 M68HC11 K Series MC68HC11TS/D ...

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... PWDTY4 PWM OUTPUT PWDTY PWPER CLOCK S 2 CLOCK A PWEN1 CLOCK PWEN2 SELECT CON12 CNT1 CNT2 PPOL1 Q PH0/ MUX BIT 0 PW1 Q Q PH1/ MUX BIT 1 PW2 Q PPOL2 PORT H PIN CONTROL PPOL3 Q PH2/ MUX BIT 2 PW3 Q Q PH3/ MUX BIT 3 PW4 Q PPOL4 MOTOROLA 75 ...

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... Always reads zero PCKB[3:1] —Prescaler for Clock B Determines the rate for clock B PWPOL —Pulse-Width Modulation Timer Polarity Bit 7 6 PCLK4 PCLK3 RESET PCLK4 —Pulse-Width Channel 4 Clock Select 0 = Clock B is source 1 = Clock S is source MOTOROLA PCKA2 PCKA1 — PCKB3 PCKA[2:1] Value of Clock A ...

Page 77

... Bit $0067 Bit RESET PWCNT1–PWCNT4 Begins count using whichever clock was selected M68HC11 K Series MC68HC11TS — — PWEN4 PWEN3 $0062 1 Bit $0063 1 Bit 0 PWEN2 PWEN1 0 0 $0064–$0067 Bit 0 PWCNT1 Bit 0 PWCNT2 Bit 0 PWCNT3 Bit 0 PWCNT4 0 MOTOROLA 77 ...

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... The following conditions always cause the corresponding output to be high: PWDTYx = $00, PWPERx > $00, and PPOLx = 0 PWDTYx PWPERx, and PPOLx = 1 PWPERx = $00 and PPOLx = 1 The following conditions always cause the corresponding output to be low: PWDTYx = $00, PWPERx > $00, and PPOLx = 1 PWDTYx PWPERx, and PPOLx = 0 PWPERx = $00 and PPOLx = 0 MOTOROLA ...

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... M68HC11 K Series MC68HC11KTS/D MOTOROLA 79 ...

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... Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur ...

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