SAK-C167CR-4RM Generation Mechanisms For The Cpu Clock - Infineon Technologies AG

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SAK-C167CR-4RM

Manufacturer Part Number
SAK-C167CR-4RM
Description
16 Bit Single-Chip Microcontroller
Manufacturer
Infineon Technologies AG
Datasheet
The specification of the external timing (AC Characteristics) therefore depends on the
time between two consecutive edges of the CPU clock, called “TCL” (see
Phase Locked Loop Operation
f
OSC
f
CPU
Direct Clock Drive
f
OSC
f
CPU
Prescaler Operation
f
OSC
f
CPU
Figure 9

Generation Mechanisms for the CPU Clock

f
The CPU clock signal
CPU
different mechanisms. The duration of TCLs and their variation (and also the derived
external timing) depends on the used mechanism to generate
be regarded when calculating the timings for the C167CR.
Note: The example for PLL operation shown in
The used mechanism to generate the basic CPU clock is selected by bitfield CLKCFG
in register RP0H.7-5.
Upon a long hardware reset register RP0H is loaded with the logic levels present on the
upper half of PORT0 (P0H), i.e. bitfield CLKCFG represents the logic levels on pins
P0.15-13 (P0H.7-5).
Table 10
associates the combinations of these three bits with the respective clock
generation mode.
Data Sheet
can be generated from the oscillator clock signal
Figure 9
49
C167CR
C167SR
Figure
9).
TCL
TCL
TCL
TCL
TCL
TCL
MCT04338
f
OSC
f
. This influence must
CPU
refers to a PLL factor of 4.
V3.2, 2001-07
via

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