SAK-C167CR-4RM Valid For: Latched Cs, Ale Low - Infineon Technologies AG

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SAK-C167CR-4RM

Manufacturer Part Number
SAK-C167CR-4RM
Description
16 Bit Single-Chip Microcontroller
Manufacturer
Infineon Technologies AG
Datasheet
Table 16
External Bus Cycle Timing (Operating Conditions apply)
Parameter
Output delay from CLKOUT falling edge
Valid for: address, BHE, early CS, write data out, ALE
Output delay from CLKOUT rising edge

Valid for: latched CS, ALE low

Output delay from CLKOUT rising edge
Valid for: WR low (no RW delay), RD low (no RW
delay)
Output delay from CLKOUT falling edge
Valid for: RD/WR low (with RW delay), RD high (with
RW delay)
Input setup time to CLKOUT falling edge
Valid for: read data in
Input hold time after CLKOUT falling edge
1)
Valid for: read data in
Output hold time after CLKOUT falling edge
Valid for: address, BHE, early CS
Output hold time after CLKOUT edge
Valid for: write data out
Output delay from CLKOUT falling edge
Valid for: WR high
Turn off delay after CLKOUT edge
Valid for: write data out
Turn on delay after CLKOUT falling edge
Valid for: write data out
1)
Read data are latched with the same (internal) clock edge that triggers the address change and the rising edge
of RD. Therefore the read data may be removed immediately after the rising edge of RD. Address changes
before the end of RD have also no impact on (demultiplexed) read cycles.
2)
Due to comparable propagation delays (at comparable capacitive loads) the address does not change before
WR goes high. The minimum output delay (
3)
Not 100% tested, guaranteed by design and characterization.
Data Sheet
Symbol
tc
10
tc
11
tc
12
tc
13
tc
14
tc
15
tc
17
2)
3)
tc
18
tc
19
3)
tc
20
3)
tc
21
tc
) is therefore the actual value of
17min
58
C167CR
C167SR
Limits
Unit
min.
max.
CC -2
11
ns
CC -2
6
ns
CC -2
8
ns
CC -2
6
ns
SR 14
ns
SR 0
ns
CC -2
6
ns
CC -2
ns
CC -2
4
ns
CC –
7
ns
CC -5
ns
tc
.
19
V3.2, 2001-07

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