MC14508BCP Motorola, MC14508BCP Datasheet

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MC14508BCP

Manufacturer Part Number
MC14508BCP
Description
Dual 4-bit latch
Manufacturer
Motorola
Datasheet

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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Dual 4-Bit Latch
N–channel enhancement mode devices in a single monolithic structure. The
part consists of two identical, independent 4–bit latches with separate Strobe
(ST) and Master Reset (MR) controls. Separate Disable inputs force the
outputs to a high impedance state and allow the devices to be used in time
sharing bus line applications.
holding register, or general digital logic functions where low power
dissipation and/or high noise immunity is desired.
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
REV 3
1/94
MAXIMUM RATINGS*
V in , V out
Symbol
MC14508B
344
I in , I out
The MC14508B dual 4–bit latch is constructed with MOS P–channel and
These complementary MOS latches find primary use in buffer storage,
Motorola, Inc. 1995
V DD
3–State Output
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable–of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load over the Rated Temperature Range
X = Don’t Care
T stg
P D
T L
Plastic “P and D/DW” Packages: – 7.0 mW/ _ C From 65 _ C To 125 _ C
Ceramic “L” Packages: – 12 mW/ _ C From 100 _ C To 125 _ C
MR
0
0
0
0
0
0
1
X
DIS
MR
ST
D n
ST
DC Supply Voltage
Input or Output Voltage (DC or Transient)
Input or Output Current (DC or Transient),
per Pin
Power Dissipation, per Package†
Storage Temperature
Lead Temperature (8–Second Soldering)
X
X
1
1
1
1
1
0
(TO OTHER THREE LATCHES)
Disable
0
0
0
0
0
0
0
1
(Voltages Referenced to V SS )
Parameter
D3
X
X
X
0
0
0
0
1
TRUTH TABLE
CIRCUIT DIAGRAM
D2
X
X
X
0
0
0
1
0
D1
X
X
X
0
0
1
0
0
D0
X
X
X
0
1
0
0
0
Q3
0
0
0
0
1
0
– 0.5 to V DD + 0.5
High Impedance
– 0.5 to + 18.0
– 65 to + 150
Q2
Value
Latched
0
0
0
1
0
0
500
260
10
Q1
0
0
1
0
0
0
Q0
V DD
V SS
0
1
0
0
0
0
Unit
mW
mA
_ C
_ C
V
V
Q n
T A = – 55 to 125 C for all packages.
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBDW
10
13
14
15
16
18
20
22
MOTOROLA CMOS LOGIC DATA
MC14508B
1
2
3
4
6
8
BLOCK DIAGRAM
MR
ST
DIS
D0
D1
D2
D3
V DD = PIN 24
V SS = PIN 12
MR
ST
DIS
D0
D1
D2
D3
Q0
Q1
Q2
Q3
Q0
Q1
Q2
Q3
DW SUFFIX
CASE 751E
CERAMIC
CASE 623
CASE 709
L SUFFIX
P SUFFIX
PLASTIC
Plastic
Ceramic
SOIC
SOIC
5
7
9
11
17
19
21
23

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MC14508BCP Summary of contents

Page 1

... C 260 Latched High Impedance MC14508B L SUFFIX CERAMIC CASE 623 P SUFFIX PLASTIC CASE 709 DW SUFFIX SOIC CASE 751E ORDERING INFORMATION MC14XXXBCP Plastic MC14XXXBCL Ceramic MC14XXXBDW SOIC – 125 C for all packages. BLOCK DIAGRAM DIS DIS PIN PIN 12 MOTOROLA CMOS LOGIC DATA ...

Page 2

... For proper operation and V out should be constrained to the range V SS Unused inputs must always be tied to an appropriate logic voltage level (e.g., either Unused outputs must be left open. MOTOROLA CMOS LOGIC DATA (Voltages Referenced – ...

Page 3

... MOTOROLA CMOS LOGIC DATA ...

Page 4

... THL MR PULSE ST GENERATOR DISABLE ST3 D2 D3 ST4 20 ns DISABLE t PLZ Q3 OUTPUT t PHZ Figure 2. 3–State AC Test Circuit and Waveforms MOTOROLA CMOS LOGIC DATA MASTER RESET t PHL Q n OUTPUT Figure 1. AC Waveforms Test Q0 t PHZ ST1 Q1 t PLZ t PZL Q2 1 PZH Q3 1.0 k ...

Page 5

... QUAD LATCH (3–STATE) (3–STATE) 4–LINE DATA BUS EXAMPLE 2 3–STATE 4–BIT LATCH MC MC 14508B 14508B 4–LINE DATA BUS MC14519B 4–LINE DATA BUS A B 3–STATE 4–BIT LATCH I OD 1/2 MC14508B 1/2 MC14508B 1/2 MC14508B BUS LINES DATA BUS MOTOROLA CMOS LOGIC DATA ...

Page 6

... SEATING G D PLANE MOTOROLA CMOS LOGIC DATA OUTLINE DIMENSIONS L SUFFIX CERAMIC DIP PACKAGE CASE 623–05 ISSUE M B SEATING PLANE SUFFIX PLASTIC DIP PACKAGE CASE 709–02 ISSUE NOTES: 1. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 2. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE ...

Page 7

... Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur ...

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