SAK-C167CS-LM

Manufacturer Part NumberSAK-C167CS-LM
Description16-Bit Single-Chip Microcontroller
ManufacturerInfineon Technologies AG
SAK-C167CS-LM datasheet
 
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Due to this adaptation to the input clock the frequency of
f
it is locked to
. The slight variation causes a jitter of
OSC
duration of individual TCLs.
The timings listed in the AC Characteristics that refer to TCLs therefore must be
calculated using the minimum TCL that is possible under the respective circumstances.
The actual minimum value for TCL depends on the jitter of the PLL. As the PLL is
constantly adjusting its output frequency so it corresponds to the applied input frequency
(crystal or oscillator) the relative deviation for periods of more than one TCL is lower than
for one single TCL (see formula and
× TCL the minimum value is computed using the corresponding
N
For a period of
deviation D
:
N
× TCL)
× TCL
N
N
(
=
min
= number of consecutive TCLs and 1 ≤
N
where
So for a period of 3 TCLs @ 25 MHz (i.e.
and (3TCL)
= 3TCL
min
NOM
This is especially important for bus cycles using waitstates and e.g. for the operation of
timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train
generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter
is neglectible.
Note: For all periods longer than 40 TCL the N = 40 value can be used (see
Max. jitter
D
N
±30
±26.5
This approximated formula is valid for
ns
N
1
40 and 10 MHz
±20
±10
±1
1
5
10
Figure 12
Approximated Maximum Accumulated PLL Jitter
Data Sheet
Figure
12).
[ns] = ± (13.3 +
- D
; D
NOM
N
N
≤ 40.
N
N
= 3): D
3
f
- 1.288 ns = 58.7 ns (@
f
40 MHz.
CPU
20
57
C167CS-4R
C167CS-L
f
is constantly adjusted so
CPU
f
which also effects the
CPU
× 6.3) /
N
f
[MHz],
CPU
× 6.3) / 25 = 1.288 ns,
3
= (13.3 +
= 25 MHz).
CPU
Figure
10 MHz
16 MHz
20 MHz
25 MHz
33 MHz
40 MHz
40
MCD04413B
V2.2, 2001-08
12).
N