SAK-C167CS-LM

Manufacturer Part NumberSAK-C167CS-LM
Description16-Bit Single-Chip Microcontroller
ManufacturerInfineon Technologies AG
SAK-C167CS-LM datasheet
 
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Page 65/81:

A/D Converter Computation Table

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5)
As the default basic clock after reset is
a valid factor as early as possible. A timeframe of approx. 6000 CPU clock cycles is sufficient to ensure a
proper reset calibration. This corresponds to minimum 300 instructions (worst case: external MUX bus with
maximum waitstates). This is required for
During the reset calibration conversions can be executed (with the current accuracy). The time required for
these conversions is added to the total reset calibration time.
6)
During the conversion the ADC’s capacitance must be repeatedly charged or discharged. The internal
resistance of the reference voltage source must allow the capacitance to reach its respective voltage level
within each conversion step. The maximum internal resistance results from the programmed conversion
timing.
7)
Not 100% tested, guaranteed by design and characterization.
8)
During the sample time the input capacitance
internal resistance of the analog source must allow the capacitance to reach its final voltage level within
After the end of the sample time
Values for the sample time
t
S
Sample time and conversion time of the C167CS’s A/D Converter are programmable.
Table 14
should be used to calculate the above timings.
f
The limit values for
must not be exceeded when selecting ADCTC.
BC
Table 14

A/D Converter Computation Table

ADCON.15|14
A/D Converter
(ADCTC)
Basic Clock
f
00
/ 4
CPU
f
01
/ 2
CPU
f
10
/ 16
CPU
f
11
/ 8
CPU
Converter Timing Example:
f
Assumptions:
CPU
f
Basic clock
BC
t
Sample time
S
t
Conversion time
C
Data Sheet
f
=
f
/ 4 the ADC’s prescaler (ADCTC) must be programmed to
BC
CPU
f
> 33 MHz and is recommended for
CPU
C
can be charged/discharged by the external source. The
AIN
t
, changes of the analog input voltage have no effect on the conversion result.
S
depend on programming and can be taken from
ADCON.13|12
f
(ADSTC)
BC
00
01
10
11
t
= 25 MHz (i.e.
= 40 ns), ADCTC = ‘00’, ADSTC = ‘00’.
CPU
f
=
/ 4 = 6.25 MHz, i.e.
CPU
× 8 = 1280 ns.
t
=
BC
= (1280 + 6400 + 80) ns = 7.8 µ s.
t
t
t
=
+ 40
+ 2
S
BC
CPU
61
C167CS-4R
C167CS-L
f
> 25 MHz.
CPU
Table
14.
Sample time
t
S
× 8
t
BC
× 16
t
BC
× 32
t
BC
× 64
t
BC
t
= 160 ns.
BC
V2.2, 2001-08
t
.
S