MM74HC03J Fairchild Semiconductor, MM74HC03J Datasheet

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MM74HC03J

Manufacturer Part Number
MM74HC03J
Description
Manufacturer
Fairchild Semiconductor
Datasheet
© 2005 Fairchild Semiconductor Corporation
MM74HC08M
MM74HC08MX_NL
MM74HC08SJ
MM74HC08MTC
MM74HC08MTCX-NL
MM74HC08N
MM74HC08
Quad 2-Input AND Gate
General Description
The MM74HC08 AND gates utilize advanced silicon-gate
CMOS technology to achieve operating speeds similar to
LS-TTL gates with the low power consumption of standard
CMOS integrated circuits. The HC08 has buffered outputs,
providing high noise immunity and the ability to drive 10
LS-TTL loads. The 74HC logic family is functionally as well
as pin-out compatible with the standard 74LS logic family.
All inputs are protected from damage due to static dis-
charge by internal diode clamps to V
Ordering Code:
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. (Tape and Reel not available in N14A)
Pb-Free package per JEDEC J-STD-020B.
Connection Diagram
Order Number
Package
Number
MTC14
MTC14
M14A
M14A
M14D
N14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Pb-Free 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
CC
and ground.
DS005297
Top View
Features
Typical propagation delay: 7 ns (t
Fanout of 10 LS-TTL loads
Quiescent power consumption: 2 A maximum at room
temperature
Low input current: 1 A maximum
Package Description
September 1983
Revised January 2005
PHL
), 12 ns (t
www.fairchildsemi.com
PLH
)

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MM74HC03J Summary of contents

Page 1

... Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. (Tape and Reel not available in N14A) Pb-Free package per JEDEC J-STD-020B. Connection Diagram © 2005 Fairchild Semiconductor Corporation Features Typical propagation delay Fanout of 10 LS-TTL loads ...

Page 2

Absolute Maximum Ratings (Note 2) Supply Voltage ( Input Voltage ( Output Voltage (V ) OUT Clamp Diode Current ( Output Current, per pin (I ) OUT DC ...

Page 3

AC Electrical Characteristics 5V pF Symbol Parameter t Maximum Propagation PHL Delay, Output HIGH-to-LOW t Maximum Propagation PLH Delay, Output LOW-to-HIGH AC Electrical Characteristics 2.0V ...

Page 4

Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow www.fairchildsemi.com Package Number M14A 4 ...

Page 5

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D 5 www.fairchildsemi.com ...

Page 6

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide www.fairchildsemi.com Package Number MTC14 6 ...

Page 7

Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right ...

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