MC145402L Motorola, MC145402L Datasheet
MC145402L
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MC145402L Summary of contents
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... SELECTOR LATCH REGISTER SUCCESSIVE TRANSMIT TRANSMIT APPROXIMATION SHIFT LATCH REGISTER REGISTER Order this document by MC145402/D MC145402 16 L SUFFIX 1 CERAMIC PACKAGE CASE 620 ORDERING INFORMATION MC145402L Ceramic Package PIN ASSIGNMENT out 15 2 RDD RCE PDI RDC TDC CCI 5 TDD 11 MSI 6 TDE TDF ...
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... Typ Max Unit 10 10 — 16 kHz — 21.3 — 64 — 512 kHz — 4096 kHz 3.27 — Vp 9.5 — dBm Min Max Unit 3.5 — V — 1.5 V — 1.0 A — 4.9 — V 4.3 — — 0.1 V — 0.4 MOTOROLA ...
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... Input Current AC Input Impedance Input Capacitance Output Voltage Range Power Supply Rejection Ratio (100 mV RMS – 50 kHz) Crosstalk out and RDD to TDD Referenced to 0 dBm0 @ 1.02 kHz Slew Rate Settling Time (Full Scale) MOTOROLA ( 5 – 5 Coder (A/D) Min Typ Max 13 — ...
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... MSI 4.1 MHz — 150 ns — 150 ns 0 100 ns — — ns 100 — 20 — — ns 100 — 100 — ns 100 — — — ns 100 — 60 — ns 100 — ns MOTOROLA ...
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... TDE t su6 t su1 t su2 TDC TDD MSI t su4 CCI CCI LAST RCE t su8 RDC t su10 RDD MOTOROLA su5 t su9 B11 B10 Figure 1. AC Timing Diagram su7 t wL CCI LAST t su3 LAST BIT CLOCK B1 B0 MC145402 5 ...
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... A logic 1 on this pin formats the data as follows: SM ... LSSS (see Fig- ure 3). RDD data is not affected by the state of this pin and if a “digital loopback” is needed (TDD data looped back into RDD), this pin should be high. MOTOROLA ...
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... CCI cycles following the rising edge of MSI. This may be achieved by setting MSI = TDE = RCE having a duration of 16 data clock cycles, and TDC = RDC MOTOROLA frequency. Figure 6 shows a circuit that generates this clock- ing configuration; see Application Circuits section. SIGNAL TO DISTORTION RATIO Figures 4 and 5 show graphs of typical signal to distortion ratios versus signal level for the MC145402 ...
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... Therefore, the calibration level, or transmission level point (TLP), for this part is 6.30 dBm (600 ), which is 1.6 Vrms based on the reference voltage of 3.27 V. MOTOROLA ...
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... Figure 2. MC145402 Full and Short Cycle Timing MOTOROLA MC145402 9 ...
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... MC145402 10 Figure 3. MC145402 Digital Data Timing MOTOROLA ...
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... COMPARED TO 9–13 BIT IDEAL D/A; MSI = 8 kHz; 70 MEASURED THROUGH A LOW–PASS FILTER WITH A BANDWIDTH – 60 – 50 Figure 5. MC145402 Decoder (D/A) Signal to Noise Plus Distortion Ratio MOTOROLA f MSI /2 – 40 – 30 – 20 – 10 INPUT LEVEL (dBm0) (1020 Hz REFERENCED TO 600 ) f MSI /2 – 40 – 30 – 20 – 10 ...
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... MC145402 12 Figure 6. Typical MC145402 Configuration MOTOROLA ...
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... V 1/2 MC74HC74 CLK DSP56000 SCK SC2 CLK 1/2 MC74HC74 SRD STD V SS Figure 7. The MC145402, 13–Bit Linear Codec, Interfaced to a Motorola DSP56000, MOTOROLA 32 f sample f sample + 5 V 1/2 MC74HC73 256 CLK kHz 1.024 MHz CLK 1/2 MC74HC73 8 kHz ...
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... C — 0.165 — 4.19 D 0.015 0.021 0.39 0.53 0.050 BSC 1.27 BSC E 0.055 0.070 1.40 1.77 F 0.100 BSC 2.54 BSC G 0.009 0.011 0.23 0.27 J — 0.200 — 5.08 K 0.300 BSC 7.62 BSC 0.015 0.035 0.39 0.88 N MOTOROLA ...
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... MOTOROLA This page intentionally left blank. MC145402 15 ...
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... Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters, including “ ...