D17P137ACT NEC, D17P137ACT Datasheet
D17P137ACT
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PD17134A SUBSERIES www.DataSheet4U.com 4-BIT SINGLE-CHIP MICROCONTROLLER © 1993 PD17134A PD17135A PD17136A PD17137A PD17P136A PD17P137A Document No. U11607EJ3V0UM00 (3rd edition) Date Published December 1996 N Printed in Japan ...
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... HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction connection is provided to the input pins possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry ...
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... Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • Product release schedule • ...
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... The export of this product from Japan is prohibited without governmental license. To export or re-export this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. The information in this document is subject to change without notice. ...
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Page Throughout www.DataSheet4U.com 111 p. 149 p. 169 p. 179 p. 190 p. ...
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Target Purpose Use www.DataSheet4U.com Legend PREFACE : This manual is intended for user engineers who understand the functions of each product in the PD17134A subseries and try to design application systems using the subseries. : The purpose of this manual ...
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Related Documents : The following documents are provided for the PD17134A subseries. The numbers listed in the table are the document numbers. Product name Document name Brochure Data sheet User’s manual Application note IE-17K (Ver. 1.6) user’s manual www.DataSheet4U.com IE-17K-ET ...
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CHAPTER 1 GENERAL DESCRIPTION ................................................................................................. 1 1.1 FUNCTION LIST ........................................................................................................................................ 2 1.2 ORDERING INFORMATION ..................................................................................................................... 3 1.3 BLOCK DIAGRAM .................................................................................................................................... 4 1.4 PIN CONFIGURATION (TOP VIEW) ........................................................................................................ 5 CHAPTER 2 PIN FUNCTIONS ............................................................................................................... 9 www.DataSheet4U.com 2.1 PIN FUNCTIONS ....................................................................................................................................... 9 ...
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CHAPTER 6 STACK .............................................................................................................................. 35 6.1 STACK CONFIGURATION ...................................................................................................................... 35 6.2 FUNCTIONS OF THE STACK ................................................................................................................ 35 6.3 ADDRESS STACK REGISTERS (ASRs) ............................................................................................... 36 6.4 INTERRUPT STACK REGISTERS (INTSKs) ........................................................................................ 36 6.5 STACK POINTER (SP) AND INTERRUPT STACK REGISTERS ........................................................ ...
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CHAPTER 8 GENERAL REGISTER (GR) ........................................................................................... 67 8.1 GENERAL REGISTER CONFIGURATION ............................................................................................ 67 8.2 FUNCTIONS OF THE GENERAL REGISTER ....................................................................................... 67 CHAPTER 9 REGISTER FILE (RF) ...................................................................................................... 69 9.1 REGISTER FILE CONFIGURATION ...................................................................................................... 69 9.1.1 9.1.2 9.2 FUNCTIONS OF THE ...
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COMPARISON JUDGEMENTS .............................................................................................................. 96 11.6.1 “Equal to” Judgement ................................................................................................................ 96 11.6.2 “Not Equal to” Judgement ......................................................................................................... 97 11.6.3 “Greater Than or Equal to” Judgement .................................................................................... 97 11.6.4 “Less Than” Judgement ............................................................................................................ 98 11.7 ROTATIONS ............................................................................................................................................. 99 11.7.1 Rotation to ...
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CHAPTER 14 INTERRUPT FUNCTIONS ............................................................................................ 149 14.1 INTERRUPT SOURCE TYPES AND VECTOR ADDRESSES ............................................................ 150 14.2 HARDWARE COMPONENTS OF THE INTERRUPT CONTROL CIRCUIT ....................................... 151 14.3 INTERRUPT SEQUENCE ..................................................................................................................... 158 14.3.1 14.3.2 14.3.3 14.4 MULTI-INTERRUPT ............................................................................................................................... 163 14.5 PROGRAM EXAMPLE ...
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INSTRUCTIONS .................................................................................................................................... 198 19.5.1 Addition Instructions ................................................................................................................ 198 19.5.2 Subtraction Instructions ........................................................................................................... 209 19.5.3 Logical Operation Instructions ................................................................................................ 216 19.5.4 Judgment Instructions ............................................................................................................. 221 19.5.5 Comparison Instructions .......................................................................................................... 223 19.5.6 Rotation Instructions ................................................................................................................ 226 19.5.7 Transfer Instructions ................................................................................................................ 227 ...
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Figure No. 3-1 Program Counter ...................................................................................................................................... 17 3-2 Value of the Program Counter after Instruction Execution .................................................................... 18 3-3 Value in the Program Counter after Reset ............................................................................................. 18 3-4 Value in the Program Counter during Execution addr ...
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Figure No. 9-1 Register File Configuration ...................................................................................................................... 69 9-2 Relationship Between the Register File and Data Memory ................................................................... 70 9-3 Accessing the Register File Using the PEEK and POKE Instructions .................................................. 72 9-4 Control Register Configuration ................................................................................................................ 75 10-1 Allocation ...
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Figure No. 14-1 Interrupt Control Register ...................................................................................................................... 152 14-2 Interrupt Processing Procedure ............................................................................................................ 158 14-3 Return from Interrupt Processing .......................................................................................................... 159 14-4 Interrupt Accepting Timing (When INTE = 1, IP 14-5 Example of Multi-interrupt ..................................................................................................................... 163 15-1 Block Diagram for ...
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Table No. 2-1 Processing of Unused Pins ..................................................................................................................... 14 4-1 Program Memory Configuration .............................................................................................................. 23 4-2 Vector Address for the PD17134A Subseries ...................................................................................... 24 6-1 Operation of Stack Pointer ...................................................................................................................... 37 6-2 Operation of the Instructions CALL, RET, and RETSK ...
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Table No. 17-1 Hardware Status at Reset ..................................................................................................................... 180 18-1 Pins Used for Writing/Verifying Program Memory ................................................................................ 189 18-2 Differences Between Mask ROM Version and One-Time PROM Version .......................................... 190 18-3 Setting Operation Modes ....................................................................................................................... 190 20-1 Mask Option Definition ...
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The PD17134A subseries is a 4-bit single-chip microcontroller employing the 17K architecture and containing an 8-bit A/D converter (4 channels), a timer (3 channels zero cross detector, a power-on reset circuit, and a serial interface. The PD17P136A and ...
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FUNCTION LIST Item ROM configuration ROM capacity RAM capacity Stack Number of I/O port A/D converter Timer www.DataSheet4U.com Serial interface AC zero cross detection function Interrupt System clock Instruction execution time Standby Power-on/ power-down reset Supply voltage Package Note ...
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... ORDERING INFORMATION Part number PD17134ACT- PD17135ACT- PD17136ACT- PD17137ACT- PD17P136ACT PD17P137ACT PD17134AGT- PD17135AGT- PD17136AGT- www.DataSheet4U.com PD17137AGT- PD17P136AGT PD17P137AGT Remark : ROM code number CHAPTER 1 GENERAL DESCRIPTION Package 28-pin plastic shrink DIP (400 mil) 28-pin plastic shrink DIP (400 mil) 28-pin plastic shrink DIP (400 mil) ...
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BLOCK DIAGRAM V DD POWER-ON/ POWER-DOWN RESET P0A 0 P0A 1 P0A 2 P0A 3 P0B 0 P0B 1 P0B 2 P0B 3 www.DataSheet4U.com P0C /ADC 0 0 P0C /ADC 1 1 P0C /ADC 2 2 P0C /ADC 3 ...
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... GND INT OSC , OSC 0 1 P0A to P0A 0 3 P0B to P0B 0 3 P0C to P0C 0 3 P0D to P0D 0 3 P1A to P1A 0 3 CHAPTER 1 GENERAL DESCRIPTION , PD17135ACT- , PD17136ACT- , PD17P137ACT- , PD17135AGT- , PD17136AGT- , PD17P137AGT ADC P0C /ADC P0C /ADC P0C /ADC P0C /ADC P0B 6 3 P0B ...
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... GND 14 : Connect to GND via pull-down resistor one by one. RESET pin is also used for system reset input before setting program memory write/verify mode. Therefore, RESET pin should be set to the same electric potential later than that ONE-TIME PROM WRITING/VERIFYING not connect anything. : Connect to V directly ...
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CLK : Clock input for address updating Data input/output 0 7 GND : Ground MD -MD : Operation mode select 0 3 RESET : Reset input V : Power supply Program voltage application PP ...
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... GND 15 INT 16 RESET Notes 1. The MD 2. The PD17P136A and 17P137A do not have a pull-up resistor connected by mask option. CHAPTER 2 PIN FUNCTIONS Function Supplies power and reference voltage for the A/D converter ADC Note1 /MD Constitute port 0C, serve as analog input pins of A converter, or select operating mode when program memory ...
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... DD Notes 1. The V pin is valid only with the PD17P136A and 17P137A The PD17P136A and 17P137A do not have a pull-up resistor connected by mask option. 3. The CLK pin is valid only with the PD17P136A and 17P137A. 10 CHAPTER 2 PIN FUNCTIONS Function Used as port 1B, or programming voltage supply pin in program memory write/verify mode. • ...
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PIN INPUT/OUTPUT CIRCUIT Below are simplified diagrams of the input/output circuits for each pin. (1) P0A -P0A 0 3 Data www.DataSheet4U.com Output disable (2) P0C /ADC 0 0 Data Output disable Input disable CHAPTER 2 PIN FUNCTIONS , P0B ...
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P0D -P0D , P1A -P1A Data Output disable www.DataSheet4U.com Note The PD17P136A and 17P137A do not have a pull-up resistor as mask option. (4) P1B 0 Note The PD17P136A and 17P137A do not have a pull-up ...
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INT (6) RESET www.DataSheet4U.com Note The PD17P136A and 17P137A do not have a pull-up resistor as mask option. CHAPTER 2 PIN FUNCTIONS Input buffer Input buffer Note Mask option 8 ...
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... When connecting a pull-up or pull-down resistor with a high resistance to a port pin, make sure that noise is not superimposed on the pin. Generally, the resistance of the pull-up or pull-down resistor is about several k , though it varies depending on the application circuit ...
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... This is especially true if the wiring length of the RESET or P1B superimposed on the wiring. Therefore, perform wiring so that noise may not be superimposed, by keeping the wiring length as short as possible. If noise is inevitable, take noise preventive measures by using an external component as illustrated below. www.DataSheet4U.com • Connect a diode with low V V and RESET/P1B DD Diode with ...
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The program counter is used to specify an address in program memory. 3.1 PROGRAM COUNTER CONFIGURATION Figure 3-1 shows the configuration of the program counter. The program counters of the PD17134A and PD17135A are 10-bit binary counters. The program counters ...
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Figure 3-2. Value of the Program Counter after Instruction Execution Program counter Instruction At reset BR addr CALL addr BR @AR CALL @AR (MOVT DBF, @AR) RET www.DataSheet4U.com RETSK RETI During interrupt Remark The shaded part is effective only in ...
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An indirect branch instruction causes the address in the address counter to be placed in the program counter. Figure 3-5. Value in the Program Counter during Execution @AR Instruction MSB AR10 www.DataSheet4U.com Remark The shaded part is ...
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Figure 3-7. Value in the Program Counter during Execution of an Indirect Subroutine Call MSB PC10 PC9 www.DataSheet4U.com AR10 AR9 Remark The shaded part is effective only in the case of PD17136A/17137A/17P136A/17P137A. 3.2.4 During Execution of Return Instructions (RET, RETSK, ...
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During Execution of Skip Instructions (SKE, SKGE, SKLT, SKNE, SKT, SKF) When skip conditions are met and a skip instruction (SKE, SKGE, SKLT, SKNE, SKT, SKF) is executed, the instruction immediately following the skip instruction is treated as a ...
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The program organization of the PD17134A subseries is shown in Table 4-1. www.DataSheet4U.com Program memory stores the program and the constant data table. The first area of the program memory is assigned to reset start and interrupt vector addresses. The ...
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... Flow of the Program The program is usually stored in program memory starting from address 0000H and executed sequentially one address at a time. However, if for some reason a different kind of program executed, it will be necessary to change the flow of the program. In this case, the branch instruction (BR instruction) is used. ...
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Direct branch A direct branch (BR addr) instruction branches a value of operand (addr address. (In the case of the PD17134A and PD17135A, the most significant bit must address is specified outside of ...
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Direct subroutine call When using a direct subroutine call (CALL addr), the 11-bit instruction operand is used to specify a program memory address of the branched subroutine. (In the case of the PD17134A and PD17135A, the most significant bit ...
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Table Reference Table reference is used to reference constant data in program memory. The table reference instruction (MOVT DBF, @AR) is used to store the contents of the program memory address specified by the address register in the data ...
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Constant data table Example 1 shows an example of code used to reference a constant data table. Example 1. Program to read data in a constant data table. OFFSET ROMREF: www.DataSheet4U.com TABLE: 28 CHAPTER 4 PROGRAM MEMORY (ROM) MEM ...
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Branch address table Example 2 shows an example of code used to reference a branch address table. Example 2. Program to branch to the address of the branch address table. OFFSET ROMREF: www.DataSheet4U.com TABLE: CHAPTER 4 PROGRAM MEMORY (ROM) ...
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Data memory stores data such as operation and control data. Data can be read from or written to data memory with an instruction during normal operation. 5.1 DATA MEMORY CONFIGURATION Figure 5-1 shows the configuration of data memory. Data memory ...
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System Register (SYSREG) The system register (SYSREG) consists of the 12 nibbles allocated at addresses 74H to 7FH in data memory. The system register (SYSREG) is allocated independently of the banks. This means that each bank has the same ...
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General Register (GR) The general register consists of 16 nibbles specified by an arbitrary row address in an arbitrary bank in data memory. This arbitrary row address in an arbitrary bank is specified by the register pointer (RP) in ...
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General Data Memory General data memory is all the data memory not used by the port and system registers (SYSREG). In other words, general data memory consists of 112 nibbles in BANK0. 5.1.6 Unmounted Data Memory There is no ...
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The stack is a register used to save information such as the program return address and the contents of the system register during execution of subroutine calls or interrupts. 6.1 STACK CONFIGURATION Figure 6-1 shows the stack configuration. The stack ...
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ADDRESS STACK REGISTERS (ASRs) Five 11-bit address stack registers (ASRs) are provided as shown in Figure 6-1. The functions of these registers are as follows: • Store a return address when the CALL addr or CALL @AR instruction is ...
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STACK POINTER (SP) AND INTERRUPT STACK REGISTERS The stack pointer is a 3-bit binary counter that specifies the addresses of the five address stack registers as shown in Figure 6-1, and is assigned to address 01H of the register ...
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STACK OPERATION Stack operation during execution of each instruction is explained in 6.6.1 to 6.6.3. 6.6.1 On Execution of Instructions CALL, RET, RETSK Table 6-2 shows operation of the stack pointer (SP), address stack register, and the program counter ...
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Operation on Execution of Interrupt Receipt and RETI Instruction Table 6-4 shows stack operation during interrupt receipt and RETI instruction. Instruction Receipt of interrupt RETI www.DataSheet4U.com 6.7 STACK NESTING LEVELS AND THE PUSH AND POP INSTRUCTIONS During execution of ...
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The system register (SYSREG), located in data memory, is used for direct control of the CPU. 7.1 SYSTEM REGISTER CONFIGURATION Figure 7-1 shows the allocation address of the system register in data memory. As shown in Figure 7-1, the system ...
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Address 74H 75H Address register Name (AR) Symbol AR3 AR2 Bit www.DataSheet4U.com Data Note Initial value ...
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ADDRESS REGISTER (AR) 7.2.1 Address Register Configuration Figure 7-3 shows the configuration of the address register. As shown in Figure 7-3, the address register consists of the 16 bits in address 74H to 77H (AR3 to AR0) of the ...
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Indirect branch instruction (BR @AR) When the BR @AR instruction is executed, the program branches to the address in program memory specified by the value in the address register. (4) Indirect subroutine call (CALL @AR) When the CALL @AR ...
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WINDOW REGISTER (WR) 7.3.1 Window Register Configuration Figure 7-5 shows the configuration of the window register. As shown in Figure 7-5, the window register (WR) consists of four bits allocated at address 78H of the system register. The contents ...
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BANK REGISTER (BANK) 7.4.1 Bank Register Configuration Figure 7-7 shows the configuration of the bank register. The bank register consists of four bits at address 79H (BANK) of the system register. However, since the three high-order bits are always ...
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INDEX REGISTER (IX) AND DATA MEMORY ROW ADDRESS POINTER (MEMORY POINTER: MP) 7.5.1 Index Register (IX used for address modification of the data memory. The difference between IX and MP is that IX modifies an address specified ...
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Figure 7-9. Modification of Data Memory Address by Index Register and Memory Pointer IXE MPE BANK 0 0 BANK 0 1 www.DataSheet4U.com BANK BANK : Bank register IX : Index register IXE : ...
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IXE = 0 and MPE = 0 (No Data Memory Modification) As shown in Table 7-9, data memory addresses are not affected by the index register and the data memory row address pointer. (1) Data memory manipulation instructions Example ...
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Example 3. Execution of “MOV m, @r” when general register is in row address 0 R00B M034 As shown in Figure 7-10, when the above instructions are executed, the contents of data memory stored at address 3EH is transferred to ...
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IXE = 0 and MPE = 1 (Diagonal Indirect Data Transfer) As shown in Figure 7-9, the indirect data transfer bank and row address specified by @r become the data memory row address pointer value only when general register ...
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Execution of “MOV m, @r” when general register is in row address 0 R00B M034 As shown in Figure 7-11, when the above instructions are executed, the data stored in address 6EH is transferred to data memory location M034. ...
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IXE = 1 and MPE = 0 (Index Modification) As shown in Figure 7-9, when a data memory manipulation instruction is executed, any bank or address in data memory specified by m can be modified using the index register. ...
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Figure 7-12. Operation Example When IXE = 1 and MPE = www.DataSheet4U.com 7 Addresses in Example 1 ADD R003, M061 Data memory address M General register address R Index modification 54 ...
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Example 2. Indirect data transfer using the general register (Execution of “MOV @r, m”) R005 MEM M034 MEM www.DataSheet4U.com As shown in Figure 7-13, when the above instructions are executed, the contents of data memory address 35H is transferred to ...
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Example 3. Clearing data memory of 00H-0FH to 0 M000 MEM MOV MOV MOV LOOP: OR MOV INC AND www.DataSheet4U.com SKE BR 4. Processing an array As shown in Figure 7-14, when an operation A(N) is executed to element A ...
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GENERAL REGISTER POINTER (RP) 7.6.1 General Register Pointer Configuration Figure 7-15 shows the configuration of the general register pointer. www.DataSheet4U.com As shown in Figure 7-15, the general register pointer consists of seven bits; four bits in system register address ...
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Functions of the General Register Pointer The general register pointer is used to specify the location of the general register in data memory. For the general register, see CHAPTER 8 GENERAL REGISTER (GR). The general register consists of 16 ...
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PROGRAM STATUS WORD (PSWORD) 7.7.1 Program Status Word Configuration Figure 7-17 shows the configuration of the program status word. www.DataSheet4U.com As shown in Figure 7-17, the program status word consists of five bits; the least significant bit of system ...
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Functions of the Program Status Word The flags of the program status word are used for setting conditions for arithmetic operations and data transfer instructions and for reflecting the status of operation results. Figure 7-18 shows an outline of ...
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Index Enable Flag (IXE) The IXE flag is used to specify index modification on the data memory address when a data memory manipulation instruction is executed. When the IXE flag is set operation is performed ...
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Binary-Coded Decimal Flag (BCD) The BCD flag is used for BCD operations. When the BCD flag is set (BCD = 1), all arithmetic operations will be performed in BCD. When the BCD flag is reset (BCD = 0), arithmetic ...
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... Reserved words for the system register are allocated in address 74H to 7FH. They are defined by the symbols (AR3, AR2, ..., PSW) shown in Figure 7-2. As shown in Example 2, if these reserved words are used not necessary to define symbols. www.DataSheet4U.com For information concerning reserved words, see CHAPTER 20 ASSEMBLER RESERVED WORDS. ...
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Example 3. F0003 Expanded macro OR 4. SET1 Expanded macro OR www.DataSheet4U.com CLR2 Z, CY Expanded macro AND CLR2 Z, BCD Expanded macro AND AND 64 CHAPTER 7 SYSTEM REGISTER (SYSREG) FLG 0.00.3 ; Flag symbol definition SET1 F0003 ; ...
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Handling of System Register Addresses Fixed dealing with system register area fixed at 0 (see Figure 7-2), there are a few points for which caution should be taken with regard to device, emulator and assembler operation. ...
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The general register (GR) is allocated in data memory. It can therefore be used directly for arithmetic operations and transferring data. 8.1 GENERAL REGISTER CONFIGURATION Figure 8-1 shows the configuration of the general register. As shown in Figure 8-1, 16 ...
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The general register pointer (RP) can be used to specify any row address in address locations BANK0 and BANK1. However, note that row addresses BANK1 are unmounted www.DataSheet4U.com memory locations and should ...
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The register file is a register used mainly for specifying conditions for peripheral hardware. 9.1 REGISTER FILE CONFIGURATION 9.1.1 Configuration of the Register File Figure 9-1 shows the configuration of the register file. As shown in Figure 9-1, the register ...
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Figure 9-2. Relationship Between the Register File and Data Memory www.DataSheet4U.com 9.2 FUNCTIONS OF THE REGISTER FILE 9.2.1 Functions of the Register File The register file is mainly used as a control register for specifying conditions for peripheral hardware. This ...
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Register File Manipulation Instructions Reading and writing data from and to the register file is done using the window register (WR: address 78H) located in the system register. Reading and writing of data is performed using the following dedicated ...
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Figure 9-3. Accessing the Register File Using the PEEK and POKE Instructions www.DataSheet4U.com 9.3 CONTROL REGISTER Figure 9-4 shows the configuration of the control register. As shown in ...
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... NOTES CONCERNING USE OF THE REGISTER FILE 9.4.1 Notes Concerning Operation of the Control Register (Read-Only and Unused Registers necessary to take note of the following notes concerning device operation and use of the 17K Series assembler (AS17K) and in-circuit emulator (IE-17K or IE-17K-ET) with regard to the read-only (R) and unused registers in the control register (register file addresses 00H to 3FH) ...
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Caution should especially be taken with regard to the following point: • When using a symbol to define the control register as an address in data memory, it needs to be defined as addresses 80H to BFH of BANK0. Since ...
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Column address Row address Item Symbol 0 (8) When reset Read/ www.DataSheet4U.com Write Symbol (9) When reset Read/ Write Symbol ...
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Note The value of the INT flag changes every moment according to the status of the INT pin. 76 ...
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The data buffer consists of four nibbles allocated in addresses 0CH to 0FH in BANK0. The data buffer acts as a data storage area for the CPU peripheral circuit (address register, serial interface, timer 0, timer1, basic internal timer, and ...
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FUNCTIONS OF THE DATA BUFFER The data buffer has two separate functions. The data buffer is used for data transfer with peripheral hardware. The data buffer is also used for reading constant data (table reference) in program memory. Figure ...
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Data Buffer and Peripheral Hardware Table 10-1 shows data transfer with peripheral hardware using the data buffer. Each unit of peripheral hardware has an individual address (called its peripheral address). By using this peripheral address and the dedicated instructions ...
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Data Transfer with Peripheral Hardware Data can be transferred between the data buffer and peripheral hardware 16-bit units. Instruction execution time for a single PUT or GET instruction is the same regardless of whether 8 or ...
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Table Reference By using the MOVT instruction, constant data in program memory (ROM) can be read into the data buffer. The MOVT instruction is explained below. MOVT DBF, @AR: The contents of the program memory being specified by the ...
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The ALU is used for performing arithmetic operations, logical operations, bit judgements, comparison judgements, and rotations on 4-bit data. 11.1 ALU BLOCK CONFIGURATION Figure 11-1 shows the configuration of the ALU block. As shown in Figure 11-1, the ALU block ...
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Temporary register A www.DataSheet4U.com Address 7EH Name Bit b Flag BCD BCD flag FF 84 CHAPTER 11 ARITHMETIC AND LOGIC UNIT (ALU) Figure 11-1. ALU Configuration Data bus Temporary Status register B flip-flop ALU • Arithmetic operations • Logical operations ...
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CHAPTER 11 ARITHMETIC AND LOGIC UNIT (ALU) 85 ...
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ALU function Instruction Arithmetic Addition ADD r, m operations ADD m, #n4 ADDC r, m ADDC m, #n4 Subtraction SUB r, m www.DataSheet4U.com SUB m, #n4 SUBC r, m SUBC m, #n4 Logical Logical operations OR OR ...
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ALU Function Arithmetic operation www.DataSheet4U.com Logical operation Bit judgement Comparison Rotation CHAPTER 11 ARITHMETIC AND LOGIC UNIT (ALU) Table 11-1. List of ALU Instructions (2/2) Difference in operation because of program status word (PSWORD) Value of Value of Operation BCD ...
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Functions of Temporary Registers A and B Temporary registers A and B are needed for processing of 4-bit data at a time. These registers are used for temporary storage of the first and second data operands of an instruction. ...
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Operations in 4-Bit Binary When the BCD flag is set to 0, arithmetic operations are performed in 4-bit binary. 11.2.5 Operations in BCD When the BCD flag is set to 1, decimal correction is performed for arithmetic operations performed ...
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Operations in the ALU Block When arithmetic operations, logical operations, bit judgements, comparison judgements or rotations in a program are executed, the first data operand is stored in temporary register A and the second data operand is stored in ...
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ARITHMETIC OPERATIONS (ADDITION AND SUBTRACTION IN 4-BIT BINARY AND BCD) As shown in Table 11-3, arithmetic operations consist of addition, subtraction, addition with carry, and subtraction with borrow. These instructions are ADD, ADDC, SUB, and SUBC. The ADD, ADDC, ...
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Addition and Subtraction When CMP = 0 and BCD = 1 BCD operations are performed. The result of the operation is stored in the general register or data memory. When the result of the operation is greater than 1001B ...
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LOGICAL OPERATIONS As shown in Table 11-4, logical operations consist of logical OR, logical AND, and logical XOR. Accordingly, the logical operation instructions are OR, AND, and XOR. The OR, AND, and XOR instructions can be performed on either ...
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BIT JUDGEMENTS As shown in Table 11-6, there are both TRUE (1) and FALSE (0) bit judgement instructions. The TRUE (1) and FALSE (0) bit judgements use SKT and SKF instruction, respectively The SKT and SKF instructions can only ...
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FALSE (0) Bit Judgement The FALSE (0) bit judgement instruction (SKF m, #n) is used to determine whether or not the bits specified the 4 bits of data memory m are FALSE (0). When all bits ...
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COMPARISON JUDGEMENTS As shown in Table 11-7, there are comparison judgement instructions for determining if one value is “equal to”, “not equal to”, “greater than or equal to”, or “less than” another. The SKE instruction is used to determine ...
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Equal to” Judgement The “not equal to” judgement instruction (SKNE m, #n4) is used to determine if immediate data and the contents of a location in data memory are not equal. This instruction causes the next instruction to ...
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Than” Judgement The “less than” judement instruction (SKLT m, #n4) is used to determine if the contents of a location in data memory is a value less than that of the immediate data operand. If the value in ...
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ROTATIONS There are rotation instructions for rotation to the right and for rotation to the left. The RORC instruction is used for rotation to the right. The RORC instruction can only be used with the general register. Rotation using ...
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Rotation to the Left Rotation to the left is performed by using the addition instruction, “ADDC r, m”. Example MOV PSW, MOV R1, MOV R2, MOV R3, ADDC R3, R3 ADDC R2, R2 ADDC R1, R1 SKF CY OR ...
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PORT 0A (P0A Port 4-bit input/output port with an output latch mapped into address 70H of BANK0 in data memory. The output format is CMOS push-pull output. Input or output can be specified in ...
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PORT 0B (P0B , P0B 0 Port 4-bit input/output port with an output latch mapped into address 71H of BANK0 in data memory. The output format is CMOS push-pull output. Input or output can ...
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PORT 0C (P0C Port 4-bit input/output port with an output latch mapped into address 72H of BANK0 in data memory. The output format is CMOS push-pull output. Input or output can be specified in ...
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PORT 0D (P0D /SCK, P0D 0 Port 4-bit input/output port with an output latch mapped into address 73H of BANK0 in data memory. The output format is N-ch open-drain output. The mask option can ...
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Input port Output port An internal clock is selected as a shift clock. SCK An external clock is selected as a shift clock TM0OUT www.DataSheet4U.com Caution Using the serial interface causes the output latch for the P0D contents ...
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PORT CONTROL REGISTER 12.7.1 Input/Output Switching by Group I/O Ports which switch input/output in 4-bit unit are called group I/O. Port 0A, port 0B, and port 1A are used as group I/O. The register shown in the figure below ...
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Input/Output Switching by Bit I/O Ports which switch input/output in 1-bit unit are called bit I/O. Port 0C and port 0D are used as bit I/O. The register shown in the figure below is used for input/output switching. RF: ...
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RF: 2BH Read/write Initial value when reset www.DataSheet4U.com 108 CHAPTER 12 PORTS Figure 12-2. Port Control Register of Bit I/O (2/2) Bit 3 Bit 2 Bit 1 Bit 0 P0DBIO3 P0DBIO2 P0DBIO1 P0DBIO0 R Read = R, ...
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Specifying Pull-Up Resistor Incorporation Using Software Pull-up resistor incorporation can be specified in 4-bit units using P0AGPU and P0BGPU (address 0CH) in the register file. RF: 0CH Read/write Initial value when reset www.DataSheet4U.com CHAPTER 12 PORTS Figure 12-3. Specifying ...
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TIMERS/COUNTERS (TM0 AND TM1) The PD17134A subseries has two channels of 8-bit timers/counters: timer 0 (TM0) and timer 1 (TM1). These two timers can be used in combination as a 16-bit timer by using the count up signal ...
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AC zero cross Interrupt detection circuit control control register register (RF : 1DH) (RF : 0FH) ZCROSS www.DataSheet4U.com AC zero cross detection circuit INT Timer 0 count up Internal reset 112 CHAPTER 13 PERIPHERAL HARDWARE Figure 13-1. Configuration of the ...
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RF : 11H Read/write Initial value when reset www.DataSheet4U.com CHAPTER 13 PERIPHERAL HARDWARE Figure 13-2. Timer 0 Mode Register Bit 2 Bit 1 Bit 0 Bit 3 TM0RES TM0CK1 TM0CK0 TM0EN R Remark TM0RES is automatically ...
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Bit 12H TM1EN Read/write Initial value when reset www.DataSheet4U.com 114 CHAPTER 13 PERIPHERAL HARDWARE Figure 13-3. Timer 1 Mode Register Bit 2 Bit 1 Bit 0 TM1RES TM1CK1 TM1CK0 R TM1CK1 TM1RES Remark ...
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Operation of 8-Bit Timers/Counters (1) Count register The count register of timers 0 and 8-bit up counter whose initial value is 00H, and is incremented each time a count pulse has been input. The count register ...
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Setting Count Value to Modulo Register A value is set to the modulo register by using the PUT instruction via DBF (data buffer). The peripheral address of the modulo register of timer 0 is assigned to 02H, and that ...
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Reading Value of Count Register The values of the count registers of timers 0 and 1 are read simultaneously by using the GET instruction via DBF (data buffer). The values of the count registers of timers 0 and 1 ...
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Setting of Interval Time The time interval at which the comparator outputs the coincidence signal is determined by the value set to the modulo register. The set value N of the modulo register is calculated from interval time T ...
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Error of Interval Time The interval time may include an error –1.5 count, especially if the value set value of the modulo register is low. (1) Error when count register is cleared to 0 during counting ...
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Error when counting is started from count stop status (maximum error: –1.5 count) The count register of the 8-bit timer is cleared setting the TMnRES flag to 1. However, the divider circuit that generates a count ...
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... P0D 3 The P0D /TM0OUT pin is an N-ch open-drain output pin and can be connected to a pull-up resistor by mask option the pull-up resistor is not connected, the P0D The internal timer 0 output flip-flop starts operating as soon as TM0EN has been set make sure that timer 0 output always starts from the initial status, set TM0RES to 1 and reset the flip-flop before starting counting ...
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BASIC INTERVAL TIMER (BTM) The PD17134A subseries has a 7-bit basic interval timer. This basic interval timer has the following functions. (1) Generates reference time. (2) Selects and counts wait time when standby mode is released. (3) Serves as ...
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Registers Controlling Basic Interval Timer The basic interval timer is controlled by the BTM mode register and watchdog timer mode register. Figures 13-10 and 13-11 show the configuration of the respective registers 13H Read/write Initial value when ...
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RF : 03H Bit 3 WDTRES Read/write Initial value at reset www.DataSheet4U.com 13.2.3 Operation of Basic Interval Timer The basic interval timer is a 7-bit binary counter that always counts up by using a count pulse specified by the BTM ...
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Watchdog Timer Function The basic interval timer can also be used as a watchdog timer to detect a program hang-up. (1) Function of watchdog timer The watchdog timer is a counter that generates a reset signal at fixed intervals. ...
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CHAPTER 13 PERIPHERAL HARDWARE ...
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Program example of watchdog timer Program Example www.DataSheet4U.com JOB1: Reset BTM before its count value reaches to 128 Notes 1. Interrupt processing by BTM cannot be performed in the method to reset counter before BTM overflows. 2. Although the ...
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A/D CONVERTER PD17134A subseries contains an 8-bit resolution A/D converter with 4-channel analog input (P0C ADC ). 3 The A/D converter uses the successive approximation method. The following two operation modes are available: (1) Successive mode: 8-bit A/D conversion ...
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Functions of A/D Converter (1) ADC – ADC 0 These pins are used to input 4-channel analog voltage to the A/D converter. The A/D converter contains a sample hold circuit. Analog input voltage is internally retained during A/D conversion. ...
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RF: 21H Bit 3 ADCSOFT Read/write Initial value when reset www.DataSheet4U.com 130 CHAPTER 13 PERIPHERAL HARDWARE Figure 13-14. A/D Converter Control Register (1/2) Bit 2 Bit 1 Bit 0 0 ADCCMP ADCEND Read = R, write = W R/W R ...
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RF Read/write Initial value when reset www.DataSheet4U.com RF: 22H Read/write Initial value when reset CHAPTER 13 PERIPHERAL HARDWARE Figure 13-14. A/D Converter Control Register (2/2) Bit 3 Bit 2 Bit 1 Bit ADCSTRT R/W ...
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Setting Values in the 8-bit Data Register (ADCR) A value is set in the 8-bit data register via the data buffer (DBF) using the PUT instruction in the same way as for comparison voltage setting in the single mode. ...
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Reading Values from the 8-bit Data Register (ADCR) A value is read from the 8-bit data register (ADCR) via the data buffer (DBF) using the GET instruction. The 8-bit data register (ADCR) of the A/D converter has peripheral address ...
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A/D Converter Operation The A/D converter operates in two modes: successive mode and single mode. The mode can be switched by setting the ADCSOFT flag. Figure 13-17. Relationship between the Analog Input Voltage and Digital Conversion Result www.DataSheet4U.com FFH ...
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Successive mode (a) Outline of successive mode In the successive mode, the A/D converter performs conversion in 8-bit units by means of successive approximation, and the result of the conversion is automatically stored to an 8-bit data register (ADCR). ...
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Figure 13-18. Using the Successive Mode for the A/D Converter www.DataSheet4U.com 136 CHAPTER 13 PERIPHERAL HARDWARE Set the successive mode (ADCSOFT = 0) Set the port input disable flag of the pin used for analog input (Set P0CnIDI to 1. ...
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... Caution Sampling is executed eight times while A/D conversion is performed once. Therefore, if the analog input voltage changes substantially during A/D conversion, conversion is not performed accurately. To obtain the accurate conversion result necessary to keep changes in the analog input voltage as small as possible during A/D conversion. ...
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Note Includes GET instruction to read data from ADCR. (2) Single Mode (a) Overview of single mode In the single mode, data in the 8-bit data register (ADCR) is compared with voltage subjected to D/A conversion and with an ...
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CHAPTER 13 PERIPHERAL HARDWARE Figure 13-20. Using the Single Mode for the A/D Converter Set single mode (ADCSOFT = 1) Disable port input for pin to be used for analog input (Set P0CnIDI to 1) Select analog input channel ...
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Single mode operation (comparison) timing Figure 13-21. Single Mode Operation (Comparison) Timing Set comparison data in ADCR. www.DataSheet4U.com Undefined ADCEND Previous data ADCCMP In the single mode, comparison is started when compare data is set to ADCR (by executing ...
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... This serial interface provides three signal lines: serial clock input pin (SCK), serial data output pin (SO), and serial data input pin (SI). It allows 8 bits to be sent or received in synchronization with clocks. It can be connected to peripheral input/output devices using any method with a mode compatible to that used by the PD7500 series or 75X series ...
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LSB P0D /SI 2 Shift register (SIOSFR) P0D /SO 1 www.DataSheet4U.com P0D /SCK 0 P0DBIO0 P0DBIO1 Note The output latch of the shift register is shared with P0D therefore, the status of the output latch of the shift register is ...
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Serial Interface Operation Modes Two modes can be used for the serial interface. If the serial interface function is selected, the P0D takes in data in synchronization with the serial clock. • 8-bit transmission reception mode (simultaneous transmission ...
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Clock synchronization 8-bit transmission and reception mode (SO pin output high impedance) The P0D /SO pin goes into a high-impedance state when SIOHIZ = 1. If supply of the serial clock is started 1 by writing “1” to SIOTS ...
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RF: 02H Read/write Initial value when reset www.DataSheet4U.com CHAPTER 13 PERIPHERAL HARDWARE Figure 13-25. Serial Interface Control Register (1/2) Bit 3 Bit 2 Bit 1 Bit 0 SIOTS SIOHIZ SIOCK1 SIOCK0 Read = R, write = W R ...
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RF: 0BH Bit 3 TM0OSEL Read/write Initial value when reset www.DataSheet4U.com 146 CHAPTER 13 PERIPHERAL HARDWARE Figure 13-25. Serial Interface Control Register (2/2) Bit 2 Bit 1 Bit SIOEN Read = R, write = W R/W 0 ...
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Setting Values in the Shift Register Values are set in the shift register via the data buffer (DBF) using the PUT instruction. The peripheral address of the shift register is 01H. When sending a value to the shift register ...
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Reading Values from the Shift Register A value is read from the shift register via the data buffer (DBF) using the GET instruction. The shift register has peripheral address 01H and only the low-order 8 bits (DBF1, DBF0) are ...
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The PD17134A subseries has four internal interrupt functions and one external interrupt function. It can be used in various applications. The interrupt control circuit of the PD17134A subseries has the features listed below. This circuit enables very high-speed interrupt processing. ...
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INTERRUPT SOURCE TYPES AND VECTOR ADDRESSES For every interrupt in the PD17134A subseries, when the interrupt is accepted, a branch occurs to the vector address associated with the interrupt source. This method is called the vectored interrupt method. Table ...
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HARDWARE COMPONENTS OF THE INTERRUPT CONTROL CIRCUIT The flags of the interrupt control circuit are explained below. (1) Interrupt Request Flag and the Interrupt Enable Flag The interrupt request flag (IRQ is executed, the flag is automatically cleared to ...
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RF: 0FH Bit 3 Read/write Initial value when reset 0 www.DataSheet4U.com RF: 1FH Bit 3 0 Read/write Initial value when reset 0 152 CHAPTER 14 INTERRUPT FUNCTIONS Figure 14-1. Interrupt Control Register (1/6) Bit 2 Bit 1 Bit 0 0 ...
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RF: 3FH Read/write Initial value when reset www.DataSheet4U.com RF: 3EH Read/write Initial value when reset CHAPTER 14 INTERRUPT FUNCTIONS Figure 14-1. Interrupt Control Register (2/6) Bit 3 Bit 2 Bit 1 Bit IRQ Read = R, ...
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RF: 3DH Read/write Initial value when reset www.DataSheet4U.com RF: 3CH Bit 3 Read/write Initial value when reset 154 CHAPTER 14 INTERRUPT FUNCTIONS Figure 14-1. Interrupt Control Register (3/6) Bit 3 Bit 2 Bit 1 Bit IRQTM1 ...
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RF: 3BH Read/write Initial value when reset www.DataSheet4U.com CHAPTER 14 INTERRUPT FUNCTIONS Figure 14-1. Interrupt Control Register (4/6) Bit 3 Bit 2 Bit 1 Bit IRQSIO Read = R, write = W R ...
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RF: 2FH IPBTM Read/write Initial value when reset www.DataSheet4U.com 156 CHAPTER 14 INTERRUPT FUNCTIONS Figure 14-1. Interrupt Control Register (5/6) Bit 3 Bit 2 Bit 1 Bit 0 IPTM1 IPTM0 IP Read = R, write = W R ...
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RF: 2EH Read/write Initial value when reset www.DataSheet4U.com CHAPTER 14 INTERRUPT FUNCTIONS Figure 14-1. Interrupt Control Register (6/6) Bit 3 Bit 2 Bit 1 Bit IPSIO Read = R, write = W R ...
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INTERRUPT SEQUENCE 14.3.1 Receiving an Interrupt When an interrupt is accepted, interrupt processing starts after the instruction cycle of the instruction being executed is completed. The program flow is transferred to a vector address. However interrupt occurs ...
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Return from the Interrupt Routine Execute the RETI instruction to return from the interrupt processing routine. During the RETI instruction cycle, processing in the figure below occurs. www.DataSheet4U.com Caution The INTE flag is not set for the RETI instruction. ...
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Interrupt Accepting Timing Figure 14-4 shows a timing chart that illustrates how interrupts are accepted. The PD17134A subseries xecutes one instruction in 16 clocks instruction cycle. One instruction cycle consists of four states M3, ...
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If interrupt occurs before M2 of MOVT instruction Machine cycle M0 Instruction IRQ www.DataSheet4U.com (5) If interrupt occurs before M2’ of MOVT instruction Machine cycle M0 Instruction IRQ··· (6) If interrupt occurs before instruction Machine cycle ...
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Figure 14-4. Interrupt Accepting Timing (When INTE = 1, IP (8) If interrupt occurs during skip of skip instruction (treated as NOP) Machine cycle M0 M1 Instruction Skip instruction IRQ www.DataSheet4U.com Remarks 1. The INT cycle is for preparation of ...
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MULTI-INTERRUPT Multi-interrupt is a method that executes interrupt processing of other interrupt source B and C during the interrupt processing for an interrupt source A as shown in Figure 14-5. Nesting level at this time is also called interrupt ...
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As shown in Figure 14-5, INTE flag is cleared automatically and becomes interrupt disable state when interrupt has been achieved. Therefore, when executing multi-interrupt processing, execute EI instruction during interrupt processing. Caution Maximum number of interrupt levels is 3. When ...
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INT_JOB: www.DataSheet4U.com WAIT_END: KEY_NO: CHAPTER 14 INTERRUPT FUNCTIONS NOP ; Loop which executes waiting for 100 MHz NOP ; instruction) ; (count value at WAIT) ADD WAITCNT, #01 ; SKE WAITCNT, # ...
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The INT pin is the interrupt signal input pin and timer count clock input pin. It also used zero cross detector input pin. This pin can be selected by writing 1 in ZCROSS (RF: 1DH bit 0). ...
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V AC input waveform ( A ) Zero cross detection signal ( B ) www.DataSheet4U.com Note The range of the input voltage when the INT pin is used as the input pin of the AC zero cross circuit is ...
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OVERVIEW OF THE STANDBY FUNCTION The PD17134A subseries has a standby function to reduce the current consumption. The standby function can be used in two modes which can be selected as the application requires: STOP and HALT modes. In ...
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HALT MODE 16.2.1 Setting HALT Mode The HALT mode is set when the HALT instruction is executed. Operand the HALT instruction specifies the condition under which the HALT mode is released ...
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By RESET input RESET Operation mode www.DataSheet4U.com (b) By IRQ IRQ Operation mode (c) By IRQ IRQ Operation mode CHAPTER 16 STANDBY FUNCTION Figure 16-1. Releasing HALT Mode HALT instruction executed HALT Mode System reset status WAIT: Wait time ...
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HALT Mode Setting Conditions (1) Forced releasing by IRQTM1 Release by external clock Release by internal clock (2) Release by interrupt request flag (IRQ www.DataSheet4U.com • Peripheral hardware used to release HALT mode is enabled to operate in advance. ...
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Example 1. Correct program (Setting of IRQ www.DataSheet4U.com 2. Incorrect program (Setting of IRQ CHAPTER 16 STANDBY FUNCTION . . . . . ) . . . . . CLR1 IRQ NOP ; Describe NOP instruction immediately before HALT instruction. ...
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STOP MODE 16.3.1 Setting of STOP Mode The STOP mode is set by executing the STOP instruction. The operand the STOP instruction specifies the condition under which the STOP mode released. ...
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Releasing STOP mode by RESET input RESET Operation mode www.DataSheet4U.com (b) Releasing STOP mode by IRQ IRQ Operation mode (c) Releasing STOP mode by IRQ IRQ Operation mode CHAPTER 16 STANDBY FUNCTION Figure 16-2. Releasing STOP Mode STOP instruction ...
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STOP Mode Setting Conditions When STOP mode released by IRQ Releasing by IRQ Releasing by IRQSIO www.DataSheet4U.com Releasing by IRQTM0 176 CHAPTER 16 STANDBY FUNCTION • Selects edge of signal to be input from INT pin ...
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Caution Be sure to include a NOP instruction before the STOP instruction. By doing so, a time of one instruction is created between the IRQ a result, clearing IRQ IRQ immediately before the STOP instruction, the CLR1 IRQ STOP instruction, ...
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The PD17134A subseries is reset in the following four ways. (1) By RESET input (2) Power-ON/power-down reset that resets the microcontroller on power application or when supply voltage drops (3) Watchdog timer that resets the microcontroller in case of a ...
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RESET FUNCTION The reset function is used to initialize the device operation. How the device is initialized differs depending on the type of reset effected. www.DataSheet4U.com Hardware Program counter I/O mode Port Output latch Other than DBF General-purpose data ...
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RF : 10H V www.DataSheet4U.com RESET 17.2 RESETTING Operation when system reset is caused by the RESET pin is shown in the figure below. If the RESET pin is set from low to high, system clock oscillation starts and an ...