M30291FCTHP Renesas Electronics Corporation., M30291FCTHP Datasheet

no-image

M30291FCTHP

Manufacturer Part Number
M30291FCTHP
Description
RENESAS MCU M16C FAMILY / M16C/Tiny SERIES
Manufacturer
Renesas Electronics Corporation.
Datasheet
REJ09B0101-0112
16
Rev. 1.12
Revision Date: Mar.30, 2007
All information contained in these materials, including products and product specifications,
represents information on the product at the time of publication and is subject to change by
Renesas Technology Corp. without notice. Please review the latest information published
by Renesas Technology Corp. through various means, including the Renesas Technology
Corp. website (http://www.renesas.com).
M16C FAMILY / M16C/Tiny SERIES
M16C/29
Hardware Manual
RENESAS MCU
www.renesas.com
Group

Related parts for M30291FCTHP

M30291FCTHP Summary of contents

Page 1

REJ09B0101-0112 16 All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Technology Corp. without notice. Please review the latest information published ...

Page 2

This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in ...

Page 3

General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If ...

Page 4

How to Use This Manual 1. Purpose and Target Readers This manual is designed to provide the user with an understanding of the hardware functions and electrical characteristics of the MCU intended for users designing application systems incorporating ...

Page 5

Notation of Numbers and Symbols The notation conventions for register names, bit names, numbers, and symbols used in this manual are described below. (1) Register Names, Bit Names, and Pin Names Registers, bits, and pins are referred to in ...

Page 6

Register Notation The symbols and terms used in register diagrams are described below. XXX Register Bit Symbol XXX0 XXX1 XXX4 XXX5 XXX6 XXX7 *1 Blank: Set ...

Page 7

List of Abbreviations and Acronyms Abbreviation ACIA bps CRC DMA DMAC GSM Hi-Z IEBus I/O IrDA LSB MSB NC PLL PWM SFR SIM UART VCO All trademarks and registered trademarks are the property of their respective owners. IEBus is ...

Page 8

Quick Reference to Pages Classified by Address _____________________ B-1 1. Overview ____________________________________________________ 1 1.1 Features ........................................................................................................................... 1 1.1.1 Applications ................................................................................................................ 1 1.1.2 Specifications ............................................................................................................. 2 1.2 Block Diagram .................................................................................................................. 4 1.3 Product List ....................................................................................................................... 6 1.4 Pin Assignments ............................................................................................................. 12 ...

Page 9

Resets _____________________________________________________ 35 5.1 Hardware Reset .............................................................................................................. 35 5.1.1 Hardware Reset 1 .................................................................................................... 35 5.1.2 Brown-Out Detection Reset (Hardware Reset 2) ..................................................... 35 5.2 Software Reset ............................................................................................................... 36 5.3 Watchdog Timer Reset ................................................................................................... 36 5.4 Oscillation Stop Detection Reset ...

Page 10

Interrupts ___________________________________________________ 70 9.1 Type of Interrupts ............................................................................................................ 70 9.1.1 Software Interrupts ................................................................................................... 71 9.1.2 Hardware Interrupts ................................................................................................. 72 9.2 Interrupts and Interrupt Vector ........................................................................................ 73 9.2.1 Fixed Vector Tables .................................................................................................. 73 9.2.2 Relocatable Vector Tables ........................................................................................ 74 9.3 ...

Page 11

Timers ___________________________________________________ 101 12.1 Timer A ...................................................................................................................... 103 12.1.1 Timer Mode .......................................................................................................... 106 12.1.2 Event Counter Mode ............................................................................................ 107 12.1.3 One-shot Timer Mode .......................................................................................... 112 12.1.4 Pulse Width Modulation (PWM) Mode ................................................................. 114 12.2 Timer B ...................................................................................................................... 117 12.2.1 ...

Page 12

SI/O3 and SI/O4 ........................................................................................................ 217 14.2.2 CLK Polarity Selection ........................................................................................ 220 14.2.1 SI/Oi Operation Timing ........................................................................................ 220 14.2.3 Functions for Setting an SOUTi Initial Value ....................................................... 221 15. A/D Converter _____________________________________________ 222 15.1 Operating Modes ........................................................................................................ 228 15.1.1 One-Shot ...

Page 13

Bit 2: Slave Address Comparison Flag (AAS) ..................................................... 269 16.5.4 Bit 3: Arbitration Lost Detection Flag (AL) ........................................................... 269 16.5.5 Bit bus Interface Interrupt Request Bit (PIN) ............................................. 270 2 16.5.6 Bit 5: Bus Busy Flag ...

Page 14

Operating Modes ........................................................................................................ 300 17.2.1 CAN Reset/Initialization Mode ............................................................................. 300 17.2.2 CAN Operating Mode ........................................................................................... 301 17.2.3 CAN Sleep Mode ................................................................................................. 301 17.2.4 CAN Interface Sleep Mode .................................................................................. 302 17.2.5 Bus Off State ........................................................................................................ 302 17.3 Configuration of the ...

Page 15

CPU Rewrite Mode ..................................................................................................... 337 20.4.1 EW Mode 0 .......................................................................................................... 338 20.4.2 EW Mode 1 .......................................................................................................... 338 20.5 Register Description ................................................................................................... 339 20.5.1 Flash Memory Control Register 0 (FMR0) ........................................................... 339 20.5.2 Flash Memory Control Register 1 (FMR1) ........................................................... ...

Page 16

Electrical Characteristics _____________________________________ 366 21.1 Normal version ........................................................................................................... 366 21.2 T version ..................................................................................................................... 387 21.3 V Version .................................................................................................................... 408 22. Usage Notes ______________________________________________ 421 22.1 SFRs ........................................................................................................................... 421 22.1.1 For 80-Pin Package ............................................................................................. 421 22.1.2 For 64-Pin Package ............................................................................................. ...

Page 17

A/D Converter ............................................................................................................. 439 22.10 Multi-Master I C bus Interface ................................................................................. 441 2 22.10.1 Writing to the S00 Register ................................................................................ 441 22.10.2 AL Flag ............................................................................................................... 441 22.11 CAN Module ............................................................................................................. 442 22.11.1 Reading C0STR Register ................................................................................... 442 22.11.2 CAN ...

Page 18

Appendix 1. Package Dimensions ________________________________ 453 Appendix 2. Functional Comparison _______________________________ 454 Appendix 2.1 Difference between M16C/28 Group and M16C/29 Group (Normal-ver.) .... 454 Appendix 2.2 Difference between M16C/28 and M16C/29 Group (T-ver./V-ver.) ............... 455 Register Index ________________________________________________ 456 A-11 ...

Page 19

Quick Reference to Pages Classified by Address Register Address 0000 16 0001 16 0002 16 0003 16 Processor mode register 0 0004 16 Processor mode register 1 0005 16 System clock control register 0 0006 16 System clock control register ...

Page 20

Quick Reference to Pages Classified by Address Register Address 0080 16 0081 16 0082 16 CAN0 message box 2: Identifier/DLC 0083 16 0084 16 0085 16 0086 16 0087 16 0088 16 0089 16 CAN0 message box 2: Data field ...

Page 21

Quick Reference to Pages Classified by Address Register Address 0100 16 0101 16 0102 16 CAN0 message box 10: Identifer/DLC 0103 16 0104 16 0105 16 0106 16 0107 16 0108 16 0109 16 CAN0 message box 10: Data field ...

Page 22

Quick Reference to Pages Classified by Address Register Address 0180 16 0181 16 0182 16 0183 16 0184 16 0185 16 0186 16 01B0 16 01B1 16 01B2 16 Flash memory control register 4 01B3 16 01B4 16 Flash memory ...

Page 23

Quick Reference to Pages Classified by Address Register Address 0300 16 TM, WG register 0 0301 16 0302 16 TM, WG register 1 0303 16 0304 16 TM, WG register 2 0305 16 0306 16 TM, WG register 3 0307 ...

Page 24

Quick Reference to Pages Classified by Address Register Address 0380 16 Count start flag Clock prescaler reset flag 0381 16 One-shot start flag 0382 16 Trigger select register 0383 16 Up-down flag 0384 16 0385 16 0386 16 Timer A0 ...

Page 25

M16C/29 Group SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER 1. Overview 1.1 Features The M16C/29 Group of single-chip control MCU incorporates the M16C/60 series CPU core, employing the high-performance silicon gate CMOS technology and sophisticated instructions for a high level of effi- ciency. ...

Page 26

1.1.2 Specifications Table 1.1 lists performance overview of M16C/29 Group 80-pin package. Table 1.2 lists performance overview of M16C/29 Group 64-pin package. Table 1.1 Performance Overview of M16C/29 ...

Page 27

Table 1.2 Performance Overview of M16C/29 Group (64-Pin Package) Item CPU Number of basic instructions Shortest instruction excution time Operation mode Address space Memory capacity Peripheral Port function ...

Page 28

1.2 Block Diagram Figure 1 block diagram of the M16C/29 Group, 80-pin package ...

Page 29

Figure 1 block diagram of the M16C/29 Group, 64-pin package ...

Page 30

1.3 Product List Tables 1.3 to 1.5 list the M16C/29 Group products and Figure 1.3 shows the type numbers, memory sizes and packages. Tables 1.6 to 1.8 list ...

Page 31

Table 1.5 Product List (3) -V Version ...

Page 32

Type No Figure 1.3 Type No., Memory Size, and Package page ...

Page 33

Table 1.6 Product Codes of Flash Memory Version ( ...

Page 34

(1) Flash Memory Version, PLQP0080KB-A (80P6Q-A), Normal-ver. M16C M30290FAHP A U3 XXXXXXX (2) Flash Memory Version, PLQP0064KB-A (64P6Q-A), Normal-ver. 30291FA A U3 XXXXXXX Figure 1.4 Marking Diagrams of ...

Page 35

(1) Flash Memory Version, PLQP0080KB-A (80P6Q-A), V-ver. M16C M30290FAVHP A U3 XXXXXXX (2) Flash Memory Version, PLQP0064KB-A (64P6Q-A), V-ver M30291FAVHP XXXXXXX Figure 1.6 Marking Diagrams of ...

Page 36

1.4 Pin Assignments Figures 1.7 and 1.8 show the pin assignments (top view /AN0 /AN0 /AN0 ...

Page 37

Table 1.12 Pin Characteristics for 80-Pin Package ...

Page 38

Table 1.12 Pin Characteristics for 80-Pin Package (continued ...

Page 39

/AN0 /AN0 /AN0 P10 /AN / P10 /AN / ...

Page 40

Table 1.13 Pin Characteristics for 64-Pin Package ...

Page 41

Table 1.13 Pin Characteristics for 64-Pin Package (continued ...

Page 42

1.5 Pin Description Table 1.14 Pin Description (64-pin and 80-pin packages) Classification Symbol Power supply V V CC, SS Analog power AV CC supply AV SS ____________ Reset ...

Page 43

Table 1.14 Pin Description (64-pin and 80-pin packages) (Continued) Classification Symbol Timer S INPC1 to INPC1 0 7 OUTC1 to OUTC1 0 7 CAN CRX CTX I/O Ports ...

Page 44

Table 1.14 Pin Description (80-pin packages only) (Continued) Classification Symbol Serial I/O CLK4 S IN4 S OUT4 A/D Converter AN0 to AN0 4 7 AN2 to AN2 0 ...

Page 45

Central Processing Unit (CPU) Figure 2.1 shows the CPU registers. The CPU has 13 registers. Of these, R0, R1, R2, R3, A0, A1 and FB comprise a ...

Page 46

2.3 Frame Base Register (FB configured with 16 bits, and is used for FB relative addressing. 2.4 Interrupt Table Register (INTB) INTB is configured with 20 ...

Page 47

Memory Figure 3 memory map of the M16C/29 Group. M16C/29 Group provides 1-Mbyte address space from addresses 00000 to FFFFF 16 FFFFF . For example, ...

Page 48

Special Function Registers (SFRs) SFRs (Special Function Registers) are the control registers of peripheral functions. Table 4.1 to 4.11 list the SFR address map. Table 4.1 SFR ...

Page 49

Table 4.2 SFR Information (2) Register Address 0040 16 CAN0 wakeup interrupt control register 0041 16 CAN0 successful reception interrupt control register 0042 16 CAN0 successful transmission interrupt ...

Page 50

Table 4.3 SFR Information (3) Register Address CAN0 message box 2: Identifier/DLC 0080 16 0081 16 0082 16 0083 16 0084 16 0085 16 CAN0 message box 2 ...

Page 51

Table 4.4 SFR Information (4) Register Address CAN0 message box 6: Identifier/DLC 00C0 16 00C1 16 00C2 16 00C3 16 00C4 16 00C5 16 CAN0 message box 6 ...

Page 52

Table 4.5 SFR Information (5) Register Address CAN0 message box 10: Identifier/DLC 0100 16 0101 16 0102 16 0103 16 0104 16 0105 16 CAN0 message box 10 ...

Page 53

Table 4.6 SFR Information (6) Register Address CAN0 message box 14: Identifier/DLC 0140 16 0141 16 0142 16 0143 16 0144 16 0145 16 CAN0 message box 14 ...

Page 54

Table 4.7 SFR Information (7) Address CAN0 message control register 0 0200 16 CAN0 message control register 1 0201 16 CAN0 message control register 2 0202 16 CAN0 ...

Page 55

Table 4.8 SFR Information (8) Register Address Time measurement, Pulse generation register 0 0300 16 0301 16 Time measurement, Pulse generation register 1 0302 16 0303 16 Time ...

Page 56

Table 4.9 SFR Information (9) Register Address 0340 16 0341 16 Timer A1-1 register 0342 16 0343 16 Timer A2-1 register 0344 16 0345 16 Timer A4-1 register ...

Page 57

Table 4.10 SFR Information (10) Register Address Count start flag 0380 16 Clock prescaler reset flag 0381 16 One-shot start flag 0382 16 Trigger select register 0383 16 ...

Page 58

Table 4.11 SFR Information (11) Register Address A/D register 0 03C0 16 03C1 16 A/D register 1 03C2 16 03C3 16 A/D register 2 03C4 16 03C5 16 ...

Page 59

Resets Hardware reset 1, brown-out detection reset (hardware reset 2), software reset, watchdog timer reset, and oscillation stop detection reset are implemented to reset the MCU. 5.1 ...

Page 60

RESET CC Figure 5.1 Example Reset Circuit 5.2 Software Reset The MCU resets its pins, CPU, and SFRs when the PM03 bit in the PM0 register is ...

Page 61

ROC More than td(P-R) td(ROC) RESET CPU clock Address Figure 5.2 Reset Sequence Table 5.1 Pin Status When RESET Pin Level is “L” Pin name P0 ...

Page 62

5.5 Voltage Detection Circuit Note assumed in 5.5 Voltage Detection Circuit. CC Voltage detection circuit in the M16C/29 Group, T-ver. and V-ver. cannot ...

Page 63

...

Page 64

...

Page 65

5.5.1 Low Voltage Detection Interrupt If the D40 bit in the D4INT register is set to 1 (low voltge detection interrupt enabled), a low voltage detection interrupt request ...

Page 66

Low voltage detection circuit D4INT clock(the VC27 clock with which it operates also in wait mode Noise rejection Low voltage detection Vref - signal (Rejection ...

Page 67

5.5.2. Limitations on Stop Mode When all the conditions below are met, the low voltage detection interrupt is generated and the MCU exits stop mode as soon as ...

Page 68

Processor Mode The MCU supports single-chip mode only. Figures 6.1 and 6.2 show the associated registers. Processor Mode Register ...

Page 69

Processeor Mode Register NOTES: 1. Write to this register after setting the PRC1 bit in the PRCR register ...

Page 70

The internal bus consists of CPU bus, memory bus, and peripheral bus. Bus Interface Unit (BIU) is used to interfere with CPU, ROM/RAM, and perpheral functions by controling ...

Page 71

Clock Generation Circuit The clock generation circuit contains four oscillator circuits as follows: (1) Main clock oscillation circuit (2) Sub clock oscillation circuit (3) Variable on-chip oscillators ...

Page 72

CM10=1(stop mode WAIT instruction R RESET Software reset NMI Interrupt request level judgment output CM00, CM01, CM02, CM04, CM05, CM06, CM07: Bits in ...

Page 73

System Clock Control Register Symbol CM0 Bit Symbol CM00 CM01 CM02 CM03 CM04 CM05 CM06 CM07 NOTES: 1. Write ...

Page 74

System Clock Control Register NOTES: 1. Write to this register after setting the PRC0 bit in the ...

Page 75

Oscillation Stop Detection Register NOTES: 1. Write to this register after setting the PRC0 bit in the PRCR ...

Page 76

Peripheral Clock Select Register NOTE: 1. Write to this register after setting the PRC0 bit in ...

Page 77

PLL Control Register NOTES: 1. Write to this register after setting the PRC0 bit in the PRCR register ...

Page 78

The following describes the clocks generated by the clock generation circuit. 7.1 Main Clock The main clock is generated by the main clock oscillation circuit. This clock is ...

Page 79

7.2 Sub Clock The sub clock is generated by the sub clock oscillation circuit. This clock is used as the clock source for the CPU clock, as well ...

Page 80

7.3 On-chip Oscillator Clock This clock is supplied by a variable on-chip oscillator. This clock is used as the clock source for the CPU and peripheral function clocks. ...

Page 81

NOTE: 1. PLL operation mode can be entered from high speed mode. Figure 7.10 Procedure to Use PLL Clock as CPU Clock Source page ...

Page 82

7.5 CPU Clock and Peripheral Function Clock The CPU clock is used to operate the CPU and peripheral function clocks are used to operate the peripheral functions. 7.5.1 ...

Page 83

7.6 Power Control There are three power control modes. In this chapter, all modes other than wait and stop modes are referred to as normal operation mode. 7.6.1 ...

Page 84

7.6.1.6 On-chip Oscillator Mode The selected on-chip oscillator clock divided by 1 (undivided provides the CPU clock. The on-chip oscillator clock is also ...

Page 85

7.6.2.3 Pin Status During Wait Mode Table 7.5 lists pin status during wait mode. Table 7.5 Pin Status in Wait Mode Pin I/O ports When fC selected CLK ...

Page 86

7.6.3 Stop Mode In stop mode, all oscillator circuits are turned off, so are the CPU clock and the peripheral function clocks. Therefore, the CPU and the peripheral ...

Page 87

Figure 7.11 shows the state transition from normal operation mode to stop mode and wait mode. Figure 7.12 shows the state transition in normal operation mode. Table 7.7 ...

Page 88

Main clock oscillation PLL operation mode PLC07=1 High-speed mode CM11=1 CPU clock: f(PLL) (5) CPU clock: f(X CM07=0 CM06=0 CM17=0 PLC07=0 CM16=0 CM11=0 (5) CM04=1 CM04=0 PLL operation ...

Page 89

Table 7.7 Allowed Transition and Setting High-speed mode, middle-speed mode High-speed mode, 8 middle-speed mode Low-speed mode 2 (8) Low power dissipation -- mode PLL operation mode 2 ...

Page 90

7.7 System Clock Protective Function When the main clock is selected for the CPU clock source, this function protects the clock from modifica- tions in order to prevent ...

Page 91

7.8.1 Operation When CM27 bit = 0 (Oscillation Stop Detection Reset) When main clock stop is detected when the CM20 bit is 1 (oscillation stop, re-oscillation detection func- ...

Page 92

7.8.3 How to Use Oscillation Stop and Re-oscillation Detect Function • The oscillation stop and re-oscillation detect interrupt shares the vector with the watchdog timer inter- rupt. If ...

Page 93

Protection In the event that a program runs out of control, this function protects the important registers so that they will not be rewritten easily. Figure 8.1 ...

Page 94

Interrupts Note The SI/O4 interrupt of peripheral function interrupts is not available in the 64-pin package. The low voltage detection function is not available in M16C/29 T-ver. ...

Page 95

9.1.1 Software Interrupts A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable interrupts. 9.1.1.1 Undefined Instruction Interrupt An undefined instruction interrupt occurs when executing the ...

Page 96

9.1.2 Hardware Interrupts Hardware interrupts are classified into two types — special interrupts and peripheral function interrupts. 9.1.2.1 Special Interrupts Special interrupts are non-maskable interrupts. _______ 9.1.2.1.1 NMI ...

Page 97

9.2 Interrupts and Interrupt Vector One interrupt vector consists of 4 bytes. Set the start address of each interrupt routine in the respective interrupt vectors. When an interrupt ...

Page 98

9.2.2 Relocatable Vector Tables The 256 bytes beginning with the start address set in the INTB register comprise a reloacatable vector table area. Table 9.2 lists the relocatable ...

Page 99

9.3 Interrupt Control The following describes how to enable/disable the maskable interrupts, and how to set the priority in which order they are accepted. What is explained here ...

Page 100

Interrupt Control Register NOTES: 1. This bit can only be reset by writing 0 (Do not write 1 rewrite the ...

Page 101

Interrupt Request Cause Select Register NOTES: 1. When setting this bit to 1 (both edges), make sure the POL bit in ...

Page 102

9.3.1 I Flag The I flag enables or disables the maskable interrupt. Setting the I flag enabled) enables the maskable interrupt. Setting the I flag ...

Page 103

9.4 Interrupt Sequence An interrupt sequence (the device behavior from the instant an interrupt is accepted to the instant the interrupt routine is executed) is described here. If ...

Page 104

9.4.1 Interrupt Response Time Figure 9.6 shows the interrupt response time. The interrupt response or interrupt acknowledge time denotes time from when an interrupt request is generated till ...

Page 105

9.4.3 Saving Registers In the interrupt sequence, the FLG register and PC are saved to the stack. At this time, the 4 high-order bits of the PC and ...

Page 106

The operation of saving registers carried out in the interrupt sequence is dependent on whether the SP at the time of acceptance of an interrupt request, is even ...

Page 107

9.4.4 Returning from an Interrupt Routine The FLG register and PC in the state in which they were immediately before entering the interrupt se- quence are restored from ...

Page 108

Priority level of each interrupt INT1 Timer B2 Timer B0 Timer A3 Timer A1 ICOC interrupt bus interface 2 INT3 INT2 INT0 Timer B1 Timer ...

Page 109

______ 9.6 INT Interrupt _______ INTi interrupt (i triggered by the edges of external inputs. The edge polarity is selected using the IFSRi bit in ...

Page 110

______ 9.7 NMI Interrupt _______ An NMI interrupt request is generated when input on the NMI pin changes state from high to low, after the _______ NMI interrupt ...

Page 111

9.9 CAN0 Wake-up Interrupt CAN0 wake-up interrupt occurs when a falling edge is input to CRX. The CAN0 wake-up interrupt is en- abled when the PortEn bit is ...

Page 112

Table 9.6 PC Value Saved in Stack Area When Address Match Interrupt Request Is Acknowledged Instruction at the address indicated by the RMADi register • 2-byte op-code instruction ...

Page 113

10. Watchdog Timer The watchdog timer is the function of detecting when the program is out of control. Therefore, we recommend using the watchdog timer to improve reliability ...

Page 114

Watchdog Timer Control Register Watchdog Timer Start Register b7 Figure 10.2 WDC Register and WDTS Register 10.1 Count ...

Page 115

11. DMAC Note Do not use SI/O4 interrupt request as a DMA request in the 64-pin package. The DMAC (Direct Memory Access Controller) allows data to be transferred ...

Page 116

Table 11.1 DMAC Specifications Item No. of channels Transfer memory space Maximum No. of bytes transferred (1, 2) DMA request factors Channel priority Transfer unit Transfer address direction ...

Page 117

DMA0 Request Cause Select Register NOTE: 1. The causes of DMA0 requests can be selected by a combination of DMS ...

Page 118

DMA1 Request Cause Select Register NOTES: 1. The causes of DMA1 requests can be selected by a combination of DMS bit ...

Page 119

DMAi Source Pointer ( (b19) (b16)(b15) (b23 NOTE the DSD bit in the DMiCON register is 0 (fixed), this ...

Page 120

11.1 Transfer Cycles The transfer cycle consists of a memory or SFR read (source read) bus cycle and a write (destination write) bus cycle. The number of read ...

Page 121

(1) When the transfer unit bits and the source of transfer is an even address CPU clock Address CPU use bus RD signal WR ...

Page 122

11.2. DMA Transfer Cycles Any combination of even or odd transfer read and write adresses is possible. Table 11.2 shows the number of DMA transfer cycles. Table 11.3 ...

Page 123

11.3 DMA Enable When a data transfer starts after setting the DMAE bit in the DMiCON register ( (enabled), the DMAC operates as ...

Page 124

11.5 Channel Priority and DMA Transfer Timing If both DMA0 and DMA1 are enabled and DMA transfer request signals from DMA0 and DMA1 are de- tected active in ...

Page 125

12. Timers Eight 16-bit timers, each capable of operating independently of the others, can be classified by function as either timer A (five) and timer B (three). The ...

Page 126

1/2 • Main clock f 1 • PLL clock • On-chip oscillator 1/8 clock C32 TB0 IN TB1 ...

Page 127

12.1 Timer A Figure 12.3 shows a block diagram of the timer A. Figures 12.4 to 12.6 show registers related to the timer A. The timer A supports ...

Page 128

Timer Ai Register ( (b15) (b8 Timer mode Event counter mode One-shot timer mode Pulse width modulation mode (16-bit PWM) Pulse width ...

Page 129

One-shot Start Flag NOTES: 1. Make sure the PD7_1 bit in the PD7 register is set to 0 (input mode). ...

Page 130

12.1.1 Timer Mode In timer mode, the timer counts a count source generated internally (see Table 12.1). Figure 12.7 shows TAiMR register in timer mode. Table 12.1 Specifications ...

Page 131

12.1.2 Event Counter Mode In event counter mode, the timer counts pulses from an external device or overflows and underflows of other timers. Timers A2, A3, and A4 ...

Page 132

Timer Ai Mode Register (i (When not using two-phase pulse signal processing NOTES: 1. During ...

Page 133

Table 12.3 Specifications in Event Counter Mode (when processing two-phase pulse signal with timers A2, A3 and A4) Item Count source Count operation Divide ratio Count start condition ...

Page 134

Timer Ai Mode Register (i (When using two-phase pulse signal processing NOTES: 1. ...

Page 135

12.1.2.1 Counter Initialization by Two-Phase Pulse Signal Processing This function initializes the timer count value Z-phase (counter initialization) input during two- phase pulse signal processing. ...

Page 136

12.1.3 One-shot Timer Mode In one-shot timer mode, the timer is activated only once by one trigger. (See Table 12.4) When the trigger occurs, the timer starts up ...

Page 137

Timer Ai Mode Register (i NOTES: 1. Effective when TAiTGH and TAiTGL in the ONSF ...

Page 138

12.1.4 Pulse Width Modulation (PWM) Mode In PWM mode, the timer outputs pulses of a given width in succession (see Table 12.5). The counter functions as either 16-bit ...

Page 139

Timer Ai Mode Register ( NOTES: 1. Effective when bits TAiTGH and TAiTGL in the ...

Page 140

Count source “H” Input signal to TA pin iIN “L” “H” PWM pulse output from TA pin iOUT “L” IR bit in the TAiIC register f : Frequency ...

Page 141

12.2 Timer B Figure 12.15 shows a block diagram of the timer B. Figures 12.16 and 12.17 show registers related to the timer B. Timer B supports the ...

Page 142

Timer Bi Register (i (b15 NOTES: 1.The register must be accessed in 16 bit units. 2. The timer counts pulses from ...

Page 143

12.2.1 Timer Mode In timer mode, the timer counts a count source generated internally (see Table 12.6). Figure 12.18 shows TBiMR register in timer mode. Table 12.6 Specifications ...

Page 144

12.2.2 Event Counter Mode In event counter mode, the timer counts pulses from an external device or overflows and underflows of other timers (see Table 12.7). Figure 12.19 ...

Page 145

12.2.3 Pulse Period and Pulse Width Measurement Mode In pulse period and pulse width measurement mode, the timer measures pulse period or pulse width of an external signal ...

Page 146

Count source “H” Measurement pulse “L” Reload register counter transfer timing Timing at which counter reaches 0000 16 1 TBiS bit 0 TBiIC register bit 0 ...

Page 147

12.2.4 A/D Trigger Mode A/D trigger mode is used together with simultaneous sample sweep mode or delayed trigger mode 0 of A/D conversion to start A/D conversion. It ...

Page 148

Timer Bi Mode Register ( NOTE: 1. When this bit is used in delayed trigger mode 0, ...

Page 149

12.3 Three-phase Motor Control Timer Function Timers A1, A2, A4 and B2 can be used to output three-phase motor drive waveforms. Table 12.10 lists the specifications of the ...

Page 150

Figure 12.25 Three-phase Motor Control Timer Functions Block Diagram page 126 ...

Page 151

Three-phase PWM Control Register NOTES: 1. Write to this register after setting the PRC1 bit in the PRCR register ...

Page 152

Three-phase PWM Control Register NOTES: 1. Write to this register after setting the PRC1 bit in the PRCR register to 1 (write enable). Note also that this register can only ...

Page 153

Three-phase Output Buffer Register(i=0, NOTE: 1. Registers IDB0 and IDB1 values are transferred to the three-phase shift register by a transfer ...

Page 154

Timer Ai, Ai-1 Register (i= (b15) (b8 NOTES: 1. The register must be accessed in 16 bit units. 2. When the timer Ai register is set to 0000 3. Use MOV instruction to write to ...

Page 155

Timer B2 Special Mode Register Bit Symbol NOTES: 1. Write to this register after setting the PRC1 bit ...

Page 156

Timer B2 Register (b15) (b8 NOTE: 1. Access the register by 16 bit units. Trigger Select Register NOTES: 1. Set the corresponding port direction bit to 0 (input mode). ...

Page 157

Timer Ai Mode Register Timer B2 Mode Register ...

Page 158

The three-phase motor control timer function is enabled by setting the INV02 bit in the INVC0 register to 1. When this function is on, timer B2 is used to control the carrier wave, and timers A4, A1 and A2 are ...

Page 159

Sawtooth Waveform as a Carrier Wave Sawtooth wave Signal wave Timer B2 Start trigger signal (1) for timer A4 Timer A4 (1) one-shot pulse U phase (1) output ...

Page 160

Position-Data-Retain Function This function is used to retain the position data synchronously with the three-phase waveform output.There are three position-data input pins for U, V, and W phases. A trigger to retain the position data (hereafter, this trigger is ...

Page 161

12.3.1.2 Position-data-retain Function Control Register Figure 12.36 shows the structure of the position-data-retain function contol register. Position-Data-Retain Function Control Register NOTE: 1.This register is ...

Page 162

Three-phase/Port Output Switch Function When the INVC03 bit in the INVC0 register set to 1 (Timer output enabled for three-phase motor control) and setting the PFCi (i the PFCR register to 0 (I/O port), the three-phase ...

Page 163

Port Function Control Register NOTE: 1. This register is valid only when the INVC03 bit in the INVC0 register is 1 (Three-phase ...

Page 164

Timer S The Timer S (Input Capture/Output Compare : here after, Timer S is referred to as "IC/OC".) is a high- performance I/O port for time measurement and waveform generation. The IC/OC has one 16-bit base timer for free-running ...

Page 165

Figure 13.1 shows the block diagram of the IC/OC. Main clock, PLL clock, On-chip oscillator clock BTS BCK1 to BCK0 Two-phase 10 ...

Page 166

Figures 13.2 to 13.10 show registers associated with the IC/OC base timer, the time measurement func- tion, and the waveform generating function. Base Timer Register b15 b8 (b7) (b0) b7 NOTES: 1. The G1BT register reflects the value of the ...

Page 167

Divider Register Base Timer Control Register NOTS: 1. The base timer ...

Page 168

Base Timer Reset Register b15 b8 (b7) (b0) b7 NOTE: 1. The G1BTRR register reflects the value of the base timer, synchronizing with the count source f Figure 13.4 G1BTRR Register page 144 ...

Page 169

Time Measurement Control Register j (j NOTES: 1. When the PCLK0 bit in the PCLKR register is set ...

Page 170

Waveform Generation Register j (j b15 (b0 (b7) Waveform Generation Control Register j (j NOTES : 1. This setting is enabled only for even channels. In ...

Page 171

Waveform Generation Register j (j b15 (b0 (b7) Figure 13.7 G1PO0 to G1PO7 Registers page 147 ...

Page 172

Function Select Register Function Enable Register NOTES: 1. The G1FE register reflects the base timer value, synchronizing with the count source f 2. When functions for ...

Page 173

Interrupt Request Register NOTE: 1. When writing 0 to each bit in the G1IR register, use the following instruction: AND, BCLR ...

Page 174

Interrupt Enable Register Interrupt Enable Register Figure 13.10 G1IE0 and G1IE1 Registers page 150 ...

Page 175

13.1 Base Timer The base timer is a free-running counter that counts an internally generated count source. Table 13.2 lists specifications of the base timer. Table 13.3 shows ...

Page 176

BCK1 to BCK0 Two-phase pulse input BTS bit in G1BCR1 register Matched with G1BTRR Matched with G1PO0 register Input "L" to INT1 pin Figure 13.11 Base Timer Block Diagram Table 13.3 Base Timer ...

Page 177

State of a counter IT=1 in the G1BCR0 register (Base timer interrupt generated by the bit 14 overflow) b14 overflow signal Base Timer interrupts IT=0 in the G1BCR0 ...

Page 178

When the base timer is reset while the base timer increments the counter P8 (A-phase) 0 Input waveform P8 (B-phase BT1 ( When selects no division with the divider by (n+1) INT1 (Z-phase) Value of counter (2) ...

Page 179

13.1.1 Base Timer Reset Register(G1BTRR) The G1BTRR register provides the capability to reset the base timer when the base timer count value matches the value stored in the ...

Page 180

Interrupt Operation The IC/OC interrupt contains several request causes. Figure 13.18 shows the IC/OC interrupt block dia- gram and Table 13.4 shows the IC/OC interrupt assignation. When either the base timer reset request or base timer overflow request is ...

Page 181

13.4 Time Measurement Function In synchronization with an external trigger input, the value of the base timer is stored into the G1TMj register (j=0 to 7). Table 13.5 ...

Page 182

Table 13.6 Register Settings Associated with the Time Measurement Function Register Bit G1TMCRj CTS1 to CTS0 DF1 to DF0 GT, GOC, GSC PR G1TPRk - G1FS FSCj G1FE IFEj Bit configurations ...

Page 183

When selecting the rising edge as a timer measurement trigger (a) (Bits CTS1 and CTS0 in the G1TMCRj register (j=0 to 7)=01 f BT1 Base timer INPC1j pin ...

Page 184

With the prescaler function (When the G1TPRj register ( set BT1 Base timer INPC1j pin input or trigger signal after passing the digital filter Internal time measurement trigger (1) Prescaler (2) G1IRj ...

Page 185

13.5 Waveform Generating Function Waveforms are generated when the base timer value matches the G1POj (j register value. The waveform generating function has the following three ...

Page 186

Single-Phase Waveform Output Mode Output signal level of the OUTC1j pin becomes high ("H") when the INV bit in the G1POCRj (j register is set to 0(output is not reversed) and the base timer value matches the ...

Page 187

(1) Free-running operation (The RST4, RST2, and RST1 bits in the G1BCR0 and G1BCR1 registers are set to 0) FFFF Base timer 0000 OUTC1j pin G1IRj bit j=0 ...

Page 188

Phase-Delayed Waveform Output Mode Output signal level of the OUTC1j pin is inversed every time the base timer value matches the G1POj register value ( j=0 to 7). Table 13.9 lists specifications of phase-delayed waveform mode. Figure 13.23 shows ...

Page 189

(1) Free-running operation (Bits RST4, RST2, and RST1 in the registers G1BCR0 and G1BCR1 are set to 0) FFFF 16 Base timer m 0000 16 OUTC1j pin G1IRj ...

Page 190

Set/Reset Waveform Output (SR Waveform Output) Mode Output signal level of the OUTC1j pin becomes high ("H") when the INV bit in the G1POCRi (i set to 0 (output is not reversed) and the base timer ...

Page 191

(1) Free-running operation (Bits RST2 and RST1 in the G1BCR0 register and the RST4 bit in the G1BCR1 register are set to 0) FFFF 16 n Base timer ...

Page 192

I/O Port Function Select The value in the G1FE and G1FS registers decides which IC/OC pin input or output pin waveform generating mode, two channels, a set of even channel and odd channel, are ...

Page 193

13.6.1 INPC17 Alternate Input Pin Selection The input capture pin for IC/OC channel 7 can be assigned to one of two package pins. The CH7INSEL bit in the ...

Page 194

14. Serial I/O Note The SI/O4 interrupt of peripheral function interrupt is not available in the 64-pin package. Serial I/O is configured with five channels: UART0 to UART2, ...

Page 195

(UART0) RxD 0 Clock source selection CLK1 to CLK0 1SIO or 2SIO Internal 01 2 CKDIR=0 f 8SIO 32SIO External CKDIR=1 ...

Page 196

PAR 1SP disabled STPS=0 RxDi SP SP STPS=1 2SP 0 0 PAR 2SP STPS=1 enabled SP SP PAR STPS=0 1SP PAR disabled Figure 14.2 Block diagram of UARTi ...

Page 197

reverse RxD data RxD2 reverse circuit Reverse PAR 1SP disabled STPS PAR STPS=1 2SP PAR enabled 0 0 PAR STPS=1 enabled 2SP SP SP PAR ...

Page 198

UARTi Transmit Buffer Register (i (b15) (b8 NOTES: 1. Use MOV instruction to write to this register. UARTi Receive Buffer Register (i=0 to ...

Page 199

UARTi Transmit/receive Mode Register (i= NOTES: 1. Set the corresponding port direction bit for each CLKi pin to ...

Page 200

UARTi Transmit/receive Control Rregister 0 (i NOTES: 1. Set the corresponding port direction bit for each CTSi pin ...

Related keywords