MC54HC595AJ Motorola, MC54HC595AJ Datasheet
MC54HC595AJ
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MC54HC595AJ Summary of contents
Page 1
... The shift register and latch have independent clock inputs. This device also has an asynchronous reset for the shift register. The HC595A directly interfaces with the Motorola SPI serial data port on CMOS MPUs and MCUs. Output Drive Capability: 15 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2 ...
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... Ceramic DIP: – from 100 _ to 125 _ C SOIC Package: – from 125 _ C TSSOP Package: – 6.1 mW from 125 _ C For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D). RECOMMENDED OPERATING CONDITIONS Î Î Î Î ...
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... Current (per Package) Î Î Î Î Î Î Î Î Î Î Î Î Î NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D). AC ELECTRICAL CHARACTERISTICS Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î Î ...
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... High–Impedance State – NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High– Î Î Î Î ...
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... Q A – (Pins 15 Noninverted, 3–state, latch outputs (Pin 9) Noninverted, Serial Data Output. This is the output of the eighth stage of the 8–bit shift register. This output does not have three–state capability. 5 MC54/74HC595A Resulting Function Latch Serial Parallel Register Output Outputs Contents – Enabled ** * Z MOTOROLA ...
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... THL Figure 3. VALID SERIAL 50% INPUT LATCH 50% CLOCK Figure 5. TEST POINT OUTPUT DEVICE UNDER TEST * Includes all probe and jig capacitance Figure 7. MOTOROLA SWITCHING WAVEFORMS V CC RESET GND t PHL OUTPUT SQ H SHIFT CLOCK OUTPUT V CC 50% ENABLE GND OUTPUT Q OUTPUT Q SHIFT CLOCK V CC ...
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... OUTPUT 13 ENABLE LATCH 12 CLOCK SERIAL 14 DATA INPUT A SHIFT 11 CLOCK 10 RESET High–Speed CMOS Logic Data DL129 — Rev 6 EXPANDED LOGIC DIAGRAM MC54/74HC595A PARALLEL DATA OUTPUTS SERIAL 9 DATA OUTPUT SQ H MOTOROLA ...
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... MC54/74HC595A SHIFT CLOCK SERIAL DATA INPUT A RESET LATCH CLOCK OUTPUT ENABLE SERIAL DATA OUTPUT SQ H NOTE: implies that the output high–impedance state. MOTOROLA TIMING DIAGRAM 8 High–Speed CMOS Logic Data DL129 — Rev 6 ...
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... B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.054 0.068 D 0.35 0.49 0.014 0.019 F 0.40 1.25 0.016 0.049 1.27 BSC 0.050 BSC G J 0.19 0.25 0.008 0.009 K 0.10 0.25 0.004 0.009 0.229 0.244 5.80 6.20 R 0.25 0.50 0.010 0.019 MOTOROLA ...
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... Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “ ...