UPD75P108BCW NEC, UPD75P108BCW Datasheet

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... QUALITY GRADE Standard Please refer to “Quality grade on NEC Semiconductor Devices” (Document number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. In this ducument, common parts of one-time PROM products and EPROM products are represented as PROM. ...

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PIN CONFIGURATION (TOP VIEW) 64-pin plastic shrink DIP (750 mil) 64-pin ceramic shrink DIP (with window) P21/PTO1 P20/PTO0 P13/INT3 2 63 P12/INT2 3 62 P11/INT1 4 61 P10/INT0 5 60 PTH03 6 59 PTH02 7 58 PTH01 ...

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QFP (14 20 mm, 1.0 mm pitch) P41 P40 P53 P52 P51 P50 RESET P63 11 P62 12 P61 P60 13 14 P73 15 P72 16 P71 P70 17 18 P83 19 P82 64 636261605958575655545352 ...

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OVERVIEW OF FUNCTIONS Item Basic instructions 43 Minimum instruction 0.95 s, 1.91 s, 15.3 s (4.19 MHz operation) execution time 3-stage switching capability ROM 8064 Internal memory RAM 512 General register 4-bits 3 types of accumulators corresponding to bit length ...

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BASIC INTERVAL TIMER INTBT PROGRAM COUNTER (13) TIMER/EVENT TI0 COUNTER PTO0/P20 #0 INTT0 TIMER/EVENT TI1 COUNTER PTO1/P21 #1 INTT1 ROM PROGRAM SI/P03 MEMORY SERIAL 8064 SO/P02 INTERFACE SCK/P01 INTSIO INT0/P10 INT1/P11 INTER- RUPT INT2/P12 CONTROL INT3/P13 INT4/P00 CLOCK PROGRAM- OUTPUT ...

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... PIN FUNCTIONS .................................................................................................................................... 1.1 PORT PINS ..................................................................................................................................................... 1.2 OTHER PINS ................................................................................................................................................... 1.3 PIN INPUT/OUTPUT CIRCUITS ................................................................................................................... 1.4 RECOMMENDED CONNECTION OF UNUSED PINS ................................................................................. 1.5 CAUTION ON USING P00/INT4 PIN AND RESET PIN .............................................................................. 2. DIFFERENCES BETWEEN PD75P108B AND PD75P116 ................................................................. 12 3. DIFFERENCES BETWEEN MASK VERSION ( PD75108) AND PROM VERSION ( PD75P108B PROM (PROGRAM MEMORY) WRITE AND VERIFY .......................................................................... 14 4 ...

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PIN FUNCTIONS 1.1 PORT PINS Dual- Pin Name Input/Output Function Pin Input P00 INT4 Input/output P01 SCK P02 Input/output SO P03 Input SI P10 INT0 P11 INT1 Input P12 INT2 P13 INT3 P20 PTO0 P21 PTO1 Input/output P22 PCL ...

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... Edge detection vector interrupt input pin (detection edge selectable). Edge detection testable input pin (rising edge detection) Clock output pin System clock oscillation crystal/ceramic connection pin. When an external clock is used, the clock is input to X1 and the inverted clock is input to X2. System reset input pin (low-level active). ...

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PIN INPUT/OUTPUT CIRCUITS The input/output circuits of each pin of the PD75P108B are shown by in abbreviated form. (1) Type A (for Type E) CMOS standard input buffer (2) Type B Schmitt-triggered input with hysteresis characteristic (3) Type D ...

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Type E data output disable This is an input/output circuit made Type D push-pull output and Type A input buffer. (5) Type F data output disable This is an input/output circuit made Type ...

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... Type 1.4 RECOMMENDED CONNECTION OF UNUSED PINS Pin PTH00 to PTH03 TI0 TI1 P00 P01 to P03 P10 to P13 P20 to P23 P30 to P33 P40 to P43 P50 to P53 P60 to P63 P70 to P73 P80 to P83 P90 to P93 P120 to P123 P130 to P133 P140 to P143 RESET Comparator + – ...

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... For example, this problem may occure if the P00/INT4 and RESET pins wiring is too long, causing line noise. To avoid this, try to suppress line noise in wiring. If line noise is still high, try elimminating the noise using the exterior add-on components shown in the Figures below. CONNECT A DIODE WITH LOW VF BETWEEN THE V AND THE PIN. ...

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... Pull-up resistor of ports 12,13 and 14 Power-on reset circuit Power-on reset Power-on Flag Operating voltage range SDIP (Nos 36) QFP (Nos 62) Pin connection SDIP (No. 31) QFP (No. 57) Electrical specification Other Note The PROM and ROM products differ in noise resistance and noise radiation. If you are considering replacement of the PROM product by the ROM product in the transition from preproduction to volume production, this should be evaluated thoroughly with the mask ROM CS product (not ES product) ...

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... P40 to P43 (low-order 4 bits) P50 to P53 (high-order 4 bits Note Pins not used in a program memory write/verify operation should be connected to V down resistor. 4.1 PROGRAM MEMORY WRITE/VERIFY OPERATING MODES The PD75P108B assumes the program memory write/verify mode and +12.5 V are applied respec- ...

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PROGRAM MEMORY WRITE PROCEDURE The program memory writing procedure is shown below. High-speed write is possible. (1) Pull down a pin which is not used to V (2) Supply + the V and V pins ...

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PROGRAM MEMORY READ PROCEDURE The PD75P108B can read the content of the program memory in the following procedure. (1) Pull down a pin which is not used to V (2) Supply + the V and V DD ...

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... SCREENING OF ONE-TIME PROM PRODUCTS Due to the nature of their construction not possible for NEC to fully test one-time PROM products ( PD75P108BCW, PD75P108BGF-3BE) before shipment therefore recommended that screening which per- forms PROM verification be carried out after high-temperature storage under the conditions shown below once the necessary data has been written to the device ...

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ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ( PARAMETER SYMBOL Supply voltage V DD Supply voltage V I1 Input voltage Output voltage V O Output current high Output current low OL ...

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CAPACITANCE ( SYMBOL PARAMETER C Input capacitance IN Output capacitance C OUT I/O capacitance C IO COMPARATOR CHARACTERISTICS (Ta = – PARAMETER SYMBOL Comparison accuracy V ACOMP Threshold ...

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... Do not cross any other signal lines, and keep clear of lines in which a high fluctuating current flows. • Ensure that oscillator capacitor connection points are always at the same potential as V ground in a ground pattern in which a high current flows. • Do not take a signal from the oscillator. ...

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RECOMMENDED CERAMIC RESONATOR PART NAME FREQUENCY (MHz) MANUFACTURER CSAx.xxMG Murata Mfg. Co., CSTx.xxMG Ltd. CSTx.xxMGW Kyocera Corporation KBR-x.xMS CRHFx.xx Toko, Inc. RECOMMENDED CRYSTAL RESONATOR MANUFACTURER PART NAME FREQUENCY (MHz) Kinseki, Ltd. HC-49/U EXTERNAL CAPACITANCE C1 (pF) C2 (pF) 2.00 to ...

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DC CHARACTERISTICS (Ta = – PARAMETER SYMBOL V Other than below IH1 V Ports 0 & 1, TI0 & 1, RESET IH2 Input voltage high V Ports IH3 V X1, X2 IH4 V ...

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... INTL t RESET low level width RSL * The cycle time of the CPU clock ( ) is determined by the oscillator frequency of the connected resonator and the processor clock control register (PCC). The graph on the right shows cycle time t characteris- CY tics against supply voltage V when system clock is DD operated ...

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AC Timing Test Point (Excluding ports 0 & 1, TI0, TI1, X1, X2, RESET) 0.7 V 0.3 V Clock Timing X1 Input TI0, TI1 Input Timing TI0, TI1 24 0 Test Points 0 1/f ...

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Serial Transfer Timing SCK SI t KSO SO Interrupt Input Timing INT0-INT4 RESET Input Timing RESET t KCY 0 KSI SIK 0 Input Data 0 Output Data ...

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DATA MEMORY STOP MODE LOW SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS (Ta = –40 to +85 C) PARAMETER Data retention supply voltage Data retention power supply current *1 Release signal set time Oscillation stabilization wait time * 1. Does not include ...

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DC PROGRAMMING CHARACTERISTICS ( PARAMETER SYMBOL V Except X1 & X2 IH1 Input voltage high V X1, X2 IH2 V Except X1 & X2 IL1 Input voltage low V X1, X2 IL2 Input leakage current I ...

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... MD3 setup time (to MD0 ) Address *2 data output delay time Address *2 data output hold time MD3 hold time (from MD0 ) Data output float delay time from MD3 * 1. Corresponding to PD27C256A symbol. 2. Internal address signal is incremented rise of 4th X1 input, and is not connected to a pin 6.0 0. 12.5 0 SYMBOL ...

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Program Memory Write Timing t VPS VDS P40-P43 Data Input P50-P53 MD0 t M1R t PW MD1 t ...

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CHARACTERISTIC CURVE (REFERENCE VALUE) 10000 1000 100 (Crystal Oscillation Power Supply Voltage V (V) DD PD75P108B ( °C) High-Speed Mode Middle-Speed ...

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(Ceramic Oscillation Power Supply Voltage V (V) DD PD75P108B ( °C) High-Speed Mode Middle-Speed Mode Low-Speed Mode HALT Mode ...

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(Crystal Oscillation Power Supply Voltage V (V) DD PD75P108B ( °C) High-Speed Mode Middle-Speed Mode Low-Speed Mode HALT Mode ...

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(Crystal Oscillation Ambient Temperature Ta (°C) PD75P108B (V = 5V) DD High-Speed Mode Middle-Speed Mode Low-Speed Mode HALT Mode X2 Crystal 4.19 MHz 22 pF ...

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(External Clock 1.5 Middle-Speed Mode 1.0 0 Input Frequency ° PD74HCU04 ...

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(Ports 12, 13 and 14 ( ° 2.7 V ...

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RECOMMENDED SOLDERING CONDITIONS The PD75P108B should be mounted under the conditions recommended in the table below. For details of recommended soldering conditions for the surface mounting type, refer to the information document “Surface Mount Technology Manual” (IEI-1207) For soldering ...

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PACKAGE INFORMATION 64 PIN PLASTIC SHRINK DIP (750 mil NOTE 1) Each lead centerline is located within 0.17 mm (0.007 inch) of its true position (T.P.) at maximum material condition. 2) Item "K" ...

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PIN CERAMIC SHRINK DIP (SEAM WELD) (750 mil NOTES 1) Each lead centerline is located within 0.25 mm (0.01 inch) of its true position (T.P.) at maximum material condition. 2) ltem "K" to ...

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PIN PLASTIC QFP (14 20 NOTE Each lead centerline is located within 0.20 mm (0.008 inch) of its true position (T.P.) at maximum material condition. detail of ...

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... A 64-pin conversion socket EV-9200G-64 is provided. PROM programmar This is a PROM programmar adopter for PD75P108BCW and connects to PG-1500. This is a PROM programmar adopter for PD75P108BGF and connects to PG-1500. Host machine PC-9800 series (MS-DOS™ Ver.3.30 to Ver.5.00A *3) PC/AT™ series (PC-DOS™ Ver.3.10) ...

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... Other Documentations Document Name Package Manual Surface Mount Technology Manual Quality Grade on NEC Semiconductor Devices NEC Semiconductor Device Reliability Quality Control Static Discharge (ESD) Test Semiconductor Device Quality Guarantee Guide Microcomputer Related Product Guide Other Manufacturer Volume Note The above related documentations may be changed without notice. Be sure to use the latest documentations for designations ...

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PD75P108B ...

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APPENDIX C. FONCTIONAL DIFFERENCES AMONG PD751 Product Name PD75104/106/108/112/116 Item 4K/6K/8K/12K/16K ROM (byte) (Mask ROM) RAM ( 4 bits) 320/320/512/512/512 Instruction set Total CMOS input 10 32 (LED can be driver CMOS input/output directly) N-ch open-drain output Withstand Voltage Pull-up ...

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PD75116H/117H 16K/24K (One-time PROM, EPROM) (Mask ROM) 768 75X High-End/expanded High-End 32 (LED can be driver directly : Can be incorporated by mask option No 1.8 to 5.0 V –40 to +60 C 0.95 s 0.95 ...

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PD75P108B 45 ...

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... The devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. If customers intend to use NEC devices for above applications or they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact our sales people in advance. ...