MC68HC705C8ACS

Manufacturer Part NumberMC68HC705C8ACS
DescriptionHCMOS 8-bit microcontroller unit
ManufacturerMotorola
MC68HC705C8ACS datasheet
 

Specifications of MC68HC705C8ACS

CaseDIP-40L  
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idle input or an address mark brings the receiver out of the standby
state. Reset clears the RWU bit.
SBK — Send Break Bit
Setting this read/write bit continuously transmits break codes in the
form of 10-bit or 11-bit groups of logic 0s. Clearing the SBK bit stops
the break codes and transmits a logic 1 as a start bit. Reset clears the
SBK bit.
10.6.4 SCI Status Register
The SCI status register (SCSR) shown in
signal these conditions:
Address:
Read:
Write:
Reset:
MC68HC705C8A — Rev. 3
MOTOROLA
1 = Standby state
0 = Normal operation
1 = Break codes being transmitted
0 = No break codes being transmitted
Transfer of SCDR data to transmit shift register complete
Transmission complete
Transfer of receive shift register data to SCDR complete
Receiver input idle
Receiver overrun
Noisy data
Framing error
$0010
Bit 7
6
5
TDRE
TC
RDRF
1
1
0
= Unimplemented
Figure 10-8. SCI Status Register (SCSR)
Serial Communications Interface (SCI)
Serial Communications Interface (SCI)
SCI I/O Registers
Figure 10-8
contains flags to
4
3
2
1
IDLE
OR
NF
FE
0
0
0
0
U = Unaffected
Technical Data
Bit 0
U
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