MC68HC705C8ACS Motorola, MC68HC705C8ACS Datasheet - Page 66

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MC68HC705C8ACS

Manufacturer Part Number
MC68HC705C8ACS
Description
HCMOS 8-bit microcontroller unit
Manufacturer
Motorola
Datasheet

Specifications of MC68HC705C8ACS

Case
DIP-40L
Resets
Table 5-1. Programmable COP Timeout Period Selection
COP
CM1:CM0
Timeout Rate
15
00
f
2
OP
17
01
f
2
OP
19
10
f
2
OP
21
11
f
2
OP
5.3.3.2 Non-Programmable COP Watchdog
A timeout of the 18-stage ripple counter in the non-programmable COP
watchdog generates a reset. The timeout period is 65.536 ms when
f
OSC
is a direct function of the crystal frequency. The equation is:
Two memory locations control operation of the non-programmable COP
watchdog:
1. Non-programmable COP enable bit (NCOPE) in mask option
NOTE:
Writing a logic 1 to the programmable COP enable bit (PCOPE) in the
COP control register enables the programmable COP watchdog. Setting
the PCOPE bit while the NCOPE bit is programmed to logic 1 enables
both COP watchdogs to operate at the same time.
Technical Data
66
Programmable COP Timeout Period
f
= 4.0 MHz
f
= 3.5795 MHz
OSC
OSC
f
= 2.0 MHz
f
= 1.7897 MHz
OP
OP
16.38 ms
18.31 ms
65.54 ms
73.24 ms
262.14 ms
292.95 ms
1.048 s
1.172 s
= 4 MHz. The timeout period for the non-programmable COP timer
Timeout period =
register 2 (MOR2)
Programming the NCOPE bit in MOR2 to a logic 1 enables the
non-programmable COP watchdog. See
Register
2.
Resets
f
= 2.0 MHz
f
= 1.0 MHz
OSC
OSC
f
= 1.0 MHz
f
= 0.5 MHz
OP
OP
32.77 ms
65.54 ms
131.07 ms
262.14 ms
524.29 ms
1.048 s
2.097 s
4.194 s
262,144
f
OSC
9.5.3 Mask Option
MC68HC705C8A — Rev. 3
MOTOROLA

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