MC68HC705C8ACS

Manufacturer Part NumberMC68HC705C8ACS
DescriptionHCMOS 8-bit microcontroller unit
ManufacturerMotorola
MC68HC705C8ACS datasheet
 

Specifications of MC68HC705C8ACS

CaseDIP-40L  
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ICIE — Input Capture Interrupt Enable Bit
This read/write bit enables interrupts caused by an active signal on
the TCAP pin. Reset clears the ICIE bit.
OCIE — Output Compare Interrupt Enable Bit
This read/write bit enables interrupts caused by an active signal on
the TCMP pin. Reset clears the OCIE bit.
TOIE — Timer Overflow Interrupt Enable Bit
This read/write bit enables interrupts caused by a timer overflow.
Reset clears the TOIE bit.
IEDG — Input Edge Bit
The state of this read/write bit determines whether a positive or
negative transition on the TCAP pin triggers a transfer of the contents
of the timer register to the input capture registers. Reset has no effect
on the IEDG bit.
OLVL — Output Level Bit
The state of this read/write bit determines whether a logic 1 or a
logic 0 appears on the TCMP pin when a successful output compare
occurs. Reset clears the OLVL bit.
Bits 4–2 — Not used; these bits always read 0
MC68HC705C8A — Rev. 3
MOTOROLA
1 = Input capture interrupts enabled
0 = Input capture interrupts disabled
1 = Output compare interrupts enabled
0 = Output compare interrupts disabled
1 = Timer overflow interrupts enabled
0 = Timer overflow interrupts disabled
1 = Positive edge (low-to-high transition) triggers input capture
0 = Negative edge (high-to-low transition) triggers input capture
1 = TCMP goes high on output compare
0 = TCMP goes low on output compare
Capture/Compare Timer
Capture/Compare Timer
Timer I/O Registers
Technical Data
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