P82C42PC Intel Corporation, P82C42PC Datasheet
P82C42PC
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P82C42PC Summary of contents
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... Intel products except as provided in Intel’s Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata COPYRIGHT INTEL CORPORATION 1996 UPI-C42 UPI-L42 One 8-Bit Status and Two Data ...
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UPI-C42 UPI-L42 DIP PLCC QFP Symbol Pin Pin Pin Type TEST TEST XTAL XTAL RESET ...
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Table 1 Pin Description (Continued) DIP PLCC QFP Symbol Pin Pin Pin –P 21– 24 24–27 39– 35– 38 39–42 11 13– 15 PROG ...
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UPI-C42 UPI-L42 UPI-C42 L42 PRODUCT SELECTION GUIDE UPI-C42 Low power CHMOS version of the UPI-42 Device Package ROM 80C42 82C42PC 82C42PD 82C42PE 87C42 UPI-L42 ...
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UPI-42 COMPATIBLE FEATURES 1 Two Data Bus Buffers one for input and one for output This allows a much cleaner Master Slave protocol 2 8 Bits of Status IBF OBF ...
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UPI-C42 UPI-L42 If ‘‘EN DMA’’ has been executed P the DACK (DMA ACKnowledge) pin This pin acts as a chip select input for the Data Bus Buffer registers during DMA transfers EN DMA Op Code 0E5H ...
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This feature is enabled by the A20EN instruction and remains enabled until the de- vice is reset It is important to note that the execu- tion of the A20EN instruction redefines Port 2 ...
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UPI-C42 UPI-L42 Table 2 covers all suspend mode pin states In addi- tion to the suspend power down mode the UPI-C42 will also support the NMOS power down mode as outlined in Chapter 4 of the UPI-42AH users manual Table ...
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This circuitry gives the host direct control of port 2 bit 1 (P2 1) without intervention by the internal CPU When this opcode is executed P2 1 becomes a ded- icated output pin The status of this pin is read-able ...
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UPI-C42 UPI-L42 Figure 6 Quick-Pulse Programming Algorithm Quick-Pulse Programming Algorithm As previously stated the UPI-C42 will be pro- grammed using the Quick-Pulse Programming Algo- rithm developed by Intel to substantially reduce the thorughput time in production programming The Quick-Pulse Programming ...
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Apply access code to appropriate inputs to put the device into security mode c Apply high voltage to EA and Follow the programming procedure as per the Quick-Pulse Programming Algorithm with known data on the databus ...
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UPI-C42 UPI-L42 Test Code Checksum Intel Signature User Signature Test Signature Security Byte UPI-C42 Intel Signature User Defined UPI-C42 OTP EPROM Space ACCESS CODE The following table summarizes the access codes required to invoke the Sync Mode Signature Mode and ...
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SYNC MODE TIMING DIAGRAMS Minimum Specifications SYNC Operation Time XTAL 2 Clock cycles Reset Time t e SYNC NOTE The rising and falling edges of T0 should occur during low state of XTAL 2 clock APPLICATIONS Figure ...
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UPI-C42 UPI-L42 APPLICATIONS (Continued) Figure 9 8048H-UPI-C42 Interface Figure 10 UPI-C42-8243 Keyboard Scanner Figure 11 UPI-C42 80-Column Matrix Printer Interface 14 290414 –10 290414 –11 290414 –13 ...
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ABSOLUTE MAXIMUM RATINGS Ambient Temperature Under Bias Storage Temperature Voltage on Any Pin with Respect to Ground b Power Dissipation DC CHARACTERISTICS Symbol Parameter V Input Low Voltage IL V Input High Voltage ...
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UPI-C42 UPI-L42 DC CHARACTERISTICS Symbol Parameter I I Total Supply Current Active Mode 12 5 MHz Suspend Mode I Standby Power ...
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AC CHARACTERISTICS NOTE All AC Characteristics apply to both the UPI-C42 and UPI-L42 DBB READ Symbol Parameter Setup ...
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UPI-C42 UPI-L42 AC CHARACTERISTICS CLOCK Symbol t UPI-C42 UPI-L42 CY t UPI-C42 UPI-L42 CYC t PWH t PWL NOTE 1 t ...
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AC CHARACTERISTICS PROGRAMMING (UPI-C42 AND UPI-L42 25V 0 25V (87C42 87L42 ONLY) Symbol Parameter t Address Setup Time to RESET AW t Address Hold Time after ...
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UPI-C42 UPI-L42 DRIVING FROM AN EXTERNAL SOURCE NOTE See XTAL1 Configuration Table LC OSCILLATOR MODE L C NOMINAL MHz 120 MHz Each C Should be Approximately 20 pF including ...
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WAVEFORMS READ OPERATION DATA BUS BUFFER REGISTER WRITE OPERATION DATA BUS BUFFER REGISTER CLOCK TIMING UPI-C42 UPI-L42 290414 –22 290414 –23 290414 –24 21 ...
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UPI-C42 UPI-L42 WAVEFORMS (Continued) COMBINATION PROGRAM VERIFY MODE NOTES 1 A must be held low (0V) during program verify modes 0 2 For and V IH IH1 IL IL1 DDH DDL 3 When programming the ...
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WAVEFORMS (Continued) DMA PORT 2 PORT TIMING DURING EXTERNAL ACCESS (EA) On the Rising Edge of SYNC and EA is Enabled Port Data is Valid and can be Strobed On the Trailing Edge of Sync the Program Counter Contents are ...
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UPI-C42 UPI-L42 Mnemonic Description Bytes ACCUMULATOR ADD A Rr Add register to A ADD A Rr Add data memory to A ADD A data Add immediate to A ADDC A Rr Add register to A with carry ADDC A Rr ...
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Table 4 UPI Instruction Set (Continued) Mnemonic Description Bytes CONTROL (Continued) SUSPEND Invoke Suspend Power- down mode NOP No Operation REGISTERS INC Rr Increment register INC Rr Increment data memory DEC Rr Decrement register SUBROUTINE CALL addr Jump to subroutine ...