X76F041A Xicor, X76F041A Datasheet
X76F041A
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X76F041A Summary of contents
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... The X76F041 also features a synchronous response to reset; providing an automatic output of a pre-configured 32-bit data stream conforming to the ISO standard for memory cards. The X76F041 utilizes Xicor’s proprietary Direct Write cell, providing a minimum endurance of 100,000 cycles per sector and a minimum data retention of 100 years. CHIP ...
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X76F041 PIN DESCRIPTION Serial Data Input/Output (SDA) SDA is a true three state serial data input/output pin. During a read cycle, data is shifted out on this pin. During a write cycle, data is shifted in on this pin. In ...
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X76F041 DEVICE OPERATION There are three primary modes of operation for the X76F041; READ, WRITE and CONFIGURATION. The READ and WRITE modes may be performed with or without an 8-byte password. The CONFIGURATION mode always requires an 8-byte password. The ...
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X76F041 Array Control The four 1K arrays, are each programmable to different levels of access and functionality. Each array can be pro- grammed to require or not require the read/write pass- words. The functional options are: • Read and Write ...
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X76F041 The retry register must have a higher value than the retry counter for correct device operation. If the retry counter value is larger than the retry register and the retry counter is enabled, the device will wrap around allowing ...
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X76F041 Stop Condition All communications must be terminated by a stop condi- tion, which is a LOW to HIGH transition of SDA when SCL is HIGH. A stop condition can only be issued after the transmitting device has released the ...
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X76F041 WRITE OPERATION Sector Write The Sector Write mode requires issuing the 3-bit write command followed by the address, password if required and then the data bytes transferred as illustrated in Fig- Figure 6. Sector Write ...
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X76F041 ACK Polling Once a stop condition is issued to indicate the end of the host’s write sequence, the X76F041 initiates the internal nonvolatile write cycle. In order to take advantage of the typical 5ms write cycle, ACK polling can ...
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X76F041 READ OPERATION Random Read with Password Random read with password operations are initiated with a START command followed by the read command and the address of the first byte of the block in which data read: ...
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X76F041 Random Read without Password Random read operations without a password do not require the first byte block initiation address. To perform a random read without password, a START is followed by the read command plus address location of the ...
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X76F041 CONFIGURATION OPERATIONS Configuration commands generally require the configu- ration password. The exception is that programming a new read/write password requires the old read/write password and not the configuration password. In most cases these operations will be performed by the ...
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X76F041 Configuration of Passwords The sequence in figure 14 will change (program) the write, read and configuration passwords. The program- ming of passwords is done twice prior to the nonvolatile write cycle in order to verify that the new password ...
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X76F041 Read Password Reset This mode allows resetting of the READ password to all “0”s in case re-programming is needed and the old pass- word is not known. Write Password Reset This mode allows resetting of the WRITE password to ...
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X76F041 Figure 17. Read/Write Password Reset SDA LINE S Figure 18. Mass Program/Erase ...
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X76F041 RECOMMENDED OPERATING CONDITIONS Temp Min. Commercial 0 C Extended –20 C D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.) Symbol Parameter I V Supply Current (Read) CC1 CC (3) V Supply Current (Write CC2 ...
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X76F041 A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified) Read & Write Cycle Limits Symbol f SCL Clock Frequency SCL TI Noise Suppression Time Constant at SCL & SDA Inputs t SCL HIGH to SDA Data Valid DV t ...
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X76F041 (1) Bus Timing — SDA Driven by the Bus Master SCL SDA (IN) from master Start (2) Bus Timing — SDA Driven by the Slave SCL SDA (OUT) from slave START Condition Timing SCL t STAS1 SDA (IN) from ...
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X76F041 STOP Condition Timing SCL t STPS1 SDA (IN) from master Acknowledge Response from Slave (Same Timing as Data Out) SCL SDA (OUT) from slave (acknowledge) Acknowledge Response from Master SCL SDA (OUT) from master (acknowledge) CS Timing Diagram (Selecting/Deselecting ...
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X76F041 Setup Timing Diagram CC VCC CS SCL CS Deselect RST Timing Diagram — Response to a Synchronous Reset (ISO) RST SCL SDA (low) CS NOTES: (1) The reset operation results in an answer from the part ...
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X76F041 PACKAGING INFORMATION 8-LEAD PLASTIC, 0.200” WIDE SMALL OUTLINE GULLWING PACKAGE TYP “A” (EIAJ SOIC) 0.020 (.508) 0.012 (.305) PIN 1 ID .050 (1.27) BSC .212 (5.38) .203 (5.16) .013 (.330) .004 (.102) 0 REF 8 .035 (.889) .020 (.508) ...
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... Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents, licenses are implied. U.S. PATENTS Xicor products are covered by one or more of the following U.S. Patents: 4,263,664 ...