RTL8201CL REALTEK, RTL8201CL Datasheet
RTL8201CL
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RTL8201CL Summary of contents
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... SNI Timing of Transmission Cycle............. 25 8.2.4 SNI Timing of Reception Cycle .................. 26 8.2.5 MDC/MDIO timing ........................................ 27 8.2.6 Transmission Without Collision .................. 27 8.2.7 Reception Without Error.............................. 28 8.3 Crystal and Transformer Specifications ............ 29 8.3.1 Crystal Specifications .................................. 29 8.3.2 Transformer Specifications ......................... 29 9. Mechanical Dimensions .......................................... 30 10. Revision History...................................................... 31 1 RTL8201CL Rev.1.0 ...
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... Features The Realtek RTL8201CL is a Fast Ethernet Phyceiver with selectable MII or SNI interface to the MAC chip. It provides the following features: ! Supports MII/7-wire SNI (Serial Network Interface) interface ! Supports 10/100Mbps operation ! Supports half/full duplex operation Support of twisted pair or Fiber mode output ! ! IEEE 802.3/802.3u compliant ! Supports IEEE 802 ...
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... Parrallel to Serial Variable Current Baseline wander Correction 3 Level MLT-3 Comparator to NRZI ck Slave PLL data Control Voltage 3 RTL8201CL Descrambler Link pulse 10M Output waveform shaping Receive low pass filter 3 Level Driver Peak Detect Adaptive Equalizer Master PPL 25M RXD RXC 25M TXD ...
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... Pin Assignments 37. ANE 38. DUPLEX 39. SPEED 40. RPTR 41. LDPS 42. RESETB 43. ISOLATE 44. MII/SNIB 45. DGND 46. X1 47. X2 48. DVDD33 2002-03-29 RTL8201CL 4 RTL8201CL 24. RXER /FXEN 23. CRS 22. RXDV 21. RXD0 20. RXD1 19. RXD2 18. RXD3 17. DGND 16. RXC 15. LED4/ PHYAD4 14. DVDD33 13. LED3/ PHYAD3 Rev.1.0 ...
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... Management Data Input/Output: This pin provides the bi-directional signal used to transfer management information. Description Collision Detect Received Serial Data Carrier Sense Receive Clock: Resolved from received data Transmit Serial Data Transmit Clock: Generate by PHY Transmit Enable: For MAC to indicate transmit operation 5 RTL8201CL Rev.1.0 ...
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... Auto-negotiation mode, set low to force mode. This pin can be directly connected to GND or VCC. Set high to put the RTL8201CL into LDPS mode. This pin can be directly connected to GND or VCC. Refer to Section 7.7 for more information. This pin is latched to input during a power on or reset condition. Pull high to set the RTL8201CL into MII mode operation ...
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... LED Interface/PHY Address Config These five pins are latched into the RTL8201CL during power up reset to configure PHY address [0:4] used for MII management register interface. And then, in normal operation after initial reset, they are used as driving pins for status indication LED. The driving polarity, active low or active high, is determined by each latched status of the PHY address [4:0] during power-up reset ...
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... Register Descriptions This section will describe definitions and usage for each of the registers available in the RTL8201CL. 6.1 Register 0 Basic Mode Control Register Address Name Description/Usage 0:<15> Reset This bit sets the status and control registers of the PHY in a default state. This bit is self-clearing ...
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... Register 3 PHY Identifier Register 2 Address Name 3:<15;0> PHYID2 PHY RTL8201 2002-03-29 Description/Usage RTL8201CL will accept management with preamble suppressed. accepts management Description/Usage identifier ID for software Description/Usage identifier ID for software 9 RTL8201CL Default/Attribute The frames Default/Attribute recognize 0000, RO Default/Attribute recognize 8201, RO Rev.1.0 ...
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... TX flow control is supported by Link partner flow control is NOT supported by Link partner 5:<10> Pause flow control is supported by Link partner flow control is NOT supported by Link partner 5:<9> 100Base-T4 is supported by link partner 0 = 100Base-T4 not supported by link partner 2002-03-29 4 Auto-negotiation Description/Usage Description/Usage 10 RTL8201CL Advertisement Default/Attribute <00001>, RW Default/Attribute 0, RO ...
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... Nway to loopback mode. 16:<8;3> Reserved 16:<2> FLAGABD 1 = Auto-neg experienced ability detect state 16:<1> FLAGPDF 1 = Auto-neg experienced parallel detection fault state 16:<0> FLAGLSC 1 = Auto-neg experienced link status check state 2002-03-29 Partner’s binary encoded node Description/Usage Description/Usage 11 RTL8201CL selector <00000>, RO Default/Attribute Default/Attribute Rev.1.0 ...
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... Register 17 Loopback, Bypass, Receiver Error Mask Register(LBREMR) Address Name 17:<15> RPTR Set put the RTL8201CL into repeater mode 17:<14> BP_4B5B Assertion of this bit allows bypassing of the 4B/5B & 5B/4B encoder. 17:<13> BP_SCR Assertion of this bit allows bypassing of the scrambler/descrambler. 17:<12> ...
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... Reserved for internal testing 25:<11:7> PHYAD[4:0] Reflects the PHY address defined by external PHY address configuration pins 25<6:2> Test Reserved for internal testing 25<1> LINK10 1: Link established in 10Base link established in 10Base 25<0> LINK100 1: Link established in 100Base link established in 100Base 2002-03-29 Description/Usage 13 RTL8201CL Default/ Attribute R Rev.1.0 ...
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... Far End Fault Indication (FEFI) in fiber mode 7.1 MII and Management Interface 7.1.1 Data Transition To set the RTL8201CL for MII mode operation, pull MII/SNIB pin high and properly set the ANE, SPEED, and DUPLEX pins. The MII (Media Independent Interface 18-signal interface which is described in IEEE 802.3u supplying a standard interface between PHY and MAC layer. This interface operates in two frequencies – ...
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... RTL8201CL to be set as the PHY address for serial management interface communication. Setting the PHY address to 00000b will put the RTL8201CL into power down mode. The read and write frame structure for the management interface follows. ...
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... The RTL8201CL will default to transmit FLP and wait for the link partner to respond. If the RTL8201CL receives FPL, then the auto-negotiation process will go on receives NLP, then the RTL8201CL will change to 10Mbps and half duplex mode receives a 100Mbps IDLE pattern, it will change to 100Mbps and half duplex mode ...
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... In this mode, power consumption is minimum. Please refer to the section covering Isolation mode and Power Down mode. 2) RPTR pin: Pull high to set the RTL8201CL into repeater mode. This pin is pulled low by default. Please refer to the section covering Repeater mode operation. ...
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... The first three modes are configured through software, and the fourth through hardware. 1) Analog off: Setting bit 11 of register will put the RTL8201CL into analog off state. In analog off state, the RTL8201CL will power down all analog functions such as transmit, receive, PLL, etc. However, the internal 25MHz crystal oscillator will not be powered down ...
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... LDPS mode: Setting bit 12 of register pulling the LDPS pin high will put the RTL8201CL into LDPS (Link Down Power Saving) mode. In LDPS mode, the RTL8201CL will detect the link status to decide whether or not to turn off the transmit function. If the link is off, FLP or 100Mbps IDLE/10Mbps NLP will not be transmitted ...
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... Reset, and Transmit Bias(RTSET) The RTL8201CL can be reset by pulling the RESETB pin low for about 10ms, then pulling the pin high. It can also be reset by setting bit 15 of register and then setting it back to 0. Reset will clear the registers and re-initialize them, and the media interface will first disconnect and restart the auto-negotiation/parallel detection process ...
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... FEFI is an alternative in-band signaling method which is composed of 84 consecutive ‘1’ followed by one ‘0’. From the point of view of the RTL8201CL, when this pattern is detected three times, Reg.1.4 is set, which means the transmit path (the Remote side’s receive path) has a problem ...
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... Condition Minimum 0.5*Vcc -0.5V IOH=-8mA 0.9*Vcc IOL=8mA Vout=Vcc or -10uA GND Vin=Vcc or -1.0uA GND Iout=0mA Vdd-1.16V Vdd-1.81V High Vdd-1.02V 22 RTL8201CL Typical Maximum 3.3V 3.6V 125 C Typical Maximum 3.3V 3. Total Current Consumption Typical Maximum Vcc+0.5V 0.3*Vcc Vcc 0.1*Vcc 10uA 1.0uA 200mA Vdd-0.88V Vdd-1 ...
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... RTL8201CL Typical Maximum 20 26 200 260 20 26 200 260 40 400 400 160 2000 70 140 400 100 170 IH(min) V IL(max IH(min) ...
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... Minimum Typical 100Mbps 14 10Mbps 140 100Mbps 14 10Mbps 140 100Mbps 10Mbps 100Mbps 10 10Mbps 6 100Mbps 10 10Mbps 6 100Mbps 10Mbps 100Mbps 10Mbps 100Mbps 10Mbps 100Mbps 10Mbps RTL8201CL Maximum Unit 200 260 200 260 400 130 ns 600 ns 240 ns 600 ns 150 ns 3200 ns 120 ns 800 ns V IH(min) V ...
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... TXCLK low pulse width 2 t TXCLK period 3 t TXEN, TXD0 setup to TXCLK rising edge 4 t TXEN, TXD0 hold after TXCLK rising edge 5 t Transmit latency 8 TXCLK TXEN TXCLK TXEN TXD0 TPTX+- 2002-03-29 Minimum TXD0 RTL8201CL Typical Maximum 120 IH(min) V IL(max IH(min) V IL(max Unit Rev.1.0 ...
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... RXD0 hold after RXCLK rising edge 5 t Receive frame to CRS high 6 t End of receive frame to CRS low 7 t Decoder acquisition time 8 RXCLK RXD0 RXCLK RXD0 t 6 CRS TPRX+- 2002-03-29 Minimum Typical RTL8201CL Maximum Unit ns ns 120 160 ns 600 1800 ns V IH(min) V IL(max) V IH(min) V IL(max Rev.1.0 ...
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... MDIO valid from MDC rising edge 6 sourced by sourced by RTL8201B 8.2.6 Transmission Without Collision Shown is an example transfer of a packet from MAC to PHY. 2002-03-29 Minimum 160 160 400 MDC MDIO STA t 6 MDIO 27 RTL8201CL Typical Maximum 300 IH(min) V IL(max IH(min) V IL(max) V IH(min) V IL(max) Unit ...
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... Reception Without Error Shown is an example of transfer of a packet from PHY to MAC 2002-03-29 28 RTL8201CL Rev.1.0 ...
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... DC resistance (max) 2002-03-29 25.000 MHz Base wave ±50 ppm ±50 ppm -10℃ ~ +70℃ 30 ohm Max. 0 Max. Mega ohm Min./DC 100V Saunders 250A ±0.0003% Transmit End 1:1 CT 350 uH @ 8mA 0.05-0. 0.4 ohm 29 RTL8201CL Range Receive End 1:1 350 uH @ 8mA 0.05-0. 0.4 ohm Rev.1.0 ...
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... BSC 7.00 BSC PACKAGE OUTLINE DRAWING, FOOTPRINT 2.0mm 0.50 BSC 0.40 0.60 0.80 APPROVE 1.00 REF 0 3 CHECK 0 12 TYP 12 TYP REALTEK SEMI-CONDUCTOR CORP. 30 RTL8201CL TITLE: 48LD LQFP ( 7x7x1.4mm) LEADFRAME MATERIAL: DOC. NO. VERSION 1 PAGE OF DWG NO. SS048 - P1 DATE Sept. 25.2000 Rev.1.0 ...
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... Revision History Realtek Semiconductor Corp. Headquarters 1F, No. 2, Industry East Road IX, Science-based Industrial Park, Hsinchu, 300, Taiwan, R.O.C. Tel : 886-3-5780211 Fax : 886-3-5776047 WWW: www.realtek.com.tw 2002-03-29 31 RTL8201CL Rev.1.0 ...