MC74HC368N Motorola, MC74HC368N Datasheet

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MC74HC368N

Manufacturer Part Number
MC74HC368N
Description
Hex 3-state noninverting buffer
Manufacturer
Motorola
Datasheet
Product Preview
Hex 3-State Inverting Buffer
with Separate 2-Bit and
4-Bit Sections
High–Performance Silicon–Gate CMOS
are compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
active–low Output Enable. When either of the enables is high, the affected
buffer outputs are placed into high–impedance states. The HC368A has
inverting outputs.
This document contains information on a product under development. Motorola reserves the right to change or
discontinue this product without notice.
1/97
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Motorola, Inc. 1997
The MC74HC368A is identical in pinout to the LS368. The device inputs
This device is arranged into 2–bit and 4–bit sections, each having its own
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 A
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Chip Complexity: 80 FETs or 20 Equivalent Gates
OUTPUT ENABLE 1
OUTPUT ENABLE 2
15
1
A0
A1
A2
A3
A4
A5
LOGIC DIAGRAM
12
10
14
2
4
6
1
PIN 16 = V CC
PIN 8 = GND
13
11
3
5
7
9
Y0
Y1
Y2
Y3
Y4
Y5
REV 0
MC74HC368A
ENABLE 1
OUTPUT
MC74HCXXXAN
MC74HCXXXAD
MC74HCXXXADT
X = don’t care
Z = high–impedance
Enable 1,
Enable 2
ORDERING INFORMATION
GND
A0
Y0
A1
Y1
A2
Y2
FUNCTION TABLE
PIN ASSIGNMENT
H
L
L
Inputs
1
2
3
4
5
6
7
8
A
H
X
L
PLASTIC PACKAGE
TSSOP PACKAGE
SOIC PACKAGE
CASE 751B–05
CASE 948F–01
CASE 648–08
16
15
14
13
12
10
11
DT SUFFIX
9
N SUFFIX
D SUFFIX
16–LEAD
16–LEAD
16–LEAD
Output
Plastic
SOIC
TSSOP
Y
H
Z
V CC
OUTPUT
ENABLE 2
A5
Y5
A4
Y4
A3
Y3
L

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MC74HC368N Summary of contents

Page 1

... In Compliance with the Requirements Defined by JEDEC Standard No. 7A Chip Complexity: 80 FETs or 20 Equivalent Gates LOGIC DIAGRAM OUTPUT ENABLE 1 15 OUTPUT ENABLE 2 This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice. 1/97 Motorola, Inc. 1997 PIN PIN 8 = GND 1 REV 0 ...

Page 2

... Plastic DIP: – from 125 _ C SOIC Package: – from 125 _ C TSSOP Package: – 6.1 mW from 125 _ C For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D). RECOMMENDED OPERATING CONDITIONS Î Î Î Î ...

Page 3

... For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D). 2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D). ...

Page 4

... MC74HC368A TEST POINT OUTPUT DEVICE UNDER TEST * Includes all probe and jig capacitance Figure 3. A OUTPUT ENABLE MOTOROLA TEST CIRCUITS OUTPUT DEVICE UNDER TEST * Includes all probe and jig capacitance LOGIC DETAIL TO OTHER BUFFERS 4 TEST POINT CONNECT WHEN 1 k TESTING t PLZ AND t PZL . ...

Page 5

... B 3.80 4.00 0.150 0.157 C 1.35 1.75 0.054 0.068 D 0.35 0.49 0.014 0.019 F 0.40 1.25 0.016 0.049 1.27 BSC 0.050 BSC G J 0.19 0.25 0.008 0.009 K 0.10 0.25 0.004 0.009 5.80 6.20 0.229 0.244 R 0.25 0.50 0.010 0.019 MOTOROLA ...

Page 6

... Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “ ...

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