MC74HC112N Motorola, MC74HC112N Datasheet

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MC74HC112N

Manufacturer Part Number
MC74HC112N
Description
Dual J-K flip-flop with set and reset
Manufacturer
Motorola
Datasheet
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Dual J-K Flip-Flop with
Set and Reset
High–Performance Silicon–Gate CMOS
compatible with standard CMOS outputs; with pullup resistors, they are
compatible with LSTTL outputs.
nous Set and Reset inputs.
10/95
Motorola, Inc. 1995
The MC74HC112 is identical in pinout to the LS112. The device inputs are
Each flip–flop is negative–edge clocked and has active–low asynchro-
The HC112 is identical in function to the HC76, but has a different pinout.
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2 to 6 V
Low Input Current: 1 A
High Noise Immunity Characteristic of CMOS Devices
In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
Similar in Function to the LS112 Except When Set and Reset are Low
Simultaneously
Chip Complexity: 100 FETs or 25 Equivalent Gates
CLOCK 2
CLOCK 1
RESET 1
RESET 2
SET 1
SET 2
K1
K2
J1
J2
LOGIC DIAGRAM
14
13
11
15
10
12
4
2
1
3
PIN 16 = V CC
PIN 8 = GND
9
5
6
7
Q1
Q1
Q2
Q2
1
REV 6
* Both outputs will remain low as long as Set and
Set
Reset are low, but the output states are unpre-
dictable if Set and Reset go high simultaneously.
H
H
H
H
H
H
H
H
L
L
16
16
16
CLOCK 1
Reset Clock
MC74HC112
1
H
H
H
H
H
H
H
H
MC74HCXXXN
MC74HCXXXD
MC74HCXXXDT
SET 1
L
L
ORDERING INFORMATION
GND
1
1
Q1
Q1
Q2
K1
J1
FUNCTION TABLE
PIN ASSIGNMENT
Inputs
X
X
X
H
L
1
2
3
4
5
6
7
8
X
X
X
H
H
X
X
X
J
L
L
PLASTIC PACKAGE
TSSOP PACKAGE
SOIC PACKAGE
CASE 751B–05
16
15
14
13
12
10
CASE 948F–01
11
CASE 648–08
9
DT SUFFIX
N SUFFIX
D SUFFIX
K
X
X
X
H
H
X
X
X
L
L
Plastic
SOIC
TSSOP
V CC
RESET 1
RESET 2
CLOCK 2
K2
J2
SET 2
Q2
No Change
No Change
No Change
No Change
L*
Outputs
Q
H
H
L
L
Toggle
L*
Q
H
H
L
L

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MC74HC112N Summary of contents

Page 1

... J1 15 RESET 1 10 SET CLOCK RESET 2 PIN PIN 8 = GND 10/95 Motorola, Inc. 1995 Set Both outputs will remain low as long as Set and Reset are low, but the output states are unpre- dictable if Set and Reset go high simultaneously. 1 REV 6 MC74HC112 N SUFFIX PLASTIC PACKAGE 16 CASE 648– ...

Page 2

... Current (per Package) Î Î Î Î Î Î Î Î Î Î Î Î Î NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D). MOTOROLA Î Î Î Î Î Î Î Î Î ...

Page 3

... NOTES: 1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D). 2. Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D). ...

Page 4

... PLH t PHL 90 50% 10% t TLH t THL Figure 1. VALID 50 50% CLOCK Figure 3. 15, 14 RESET 2, CLOCK 4, 10 SET MOTOROLA SWITCHING WAVEFORMS V CC SET OR GND RESET CLOCK V CC GND V CC GND * Includes all probe and jig capacitance EXPANDED LOGIC DIAGRAM 50% GND t PHL 50% ...

Page 5

... B 3.80 4.00 0.150 0.157 C 0.054 0.068 1.35 1.75 D 0.35 0.49 0.014 0.019 F 0.40 1.25 0.016 0.049 1.27 BSC 0.050 BSC G J 0.008 0.009 0.19 0.25 K 0.10 0.25 0.004 0.009 5.80 6.20 0.229 0.244 R 0.25 0.50 0.010 0.019 MOTOROLA ...

Page 6

... Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters, including “ ...

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