ISP1760BE Philips Semiconductors, ISP1760BE Datasheet
ISP1760BE
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ISP1760BE Summary of contents
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ISP1760 Hi-Speed Universal Serial Bus host controller for embedded applications Rev. 01 — 8 November 2004 1. General description The ISP1760 is a Hi-Speed Universal Serial Bus (USB) Host Controller with a generic processor interface. It integrates one Enhanced Host ...
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... Philips Semiconductors Generic processor interface (nonmultiplexed and variable latency) with a configurable 32-bit or 16-bit external data bus; the processor interface can be defined as variable-latency or SRAM type (memory mapping) Slave DMA support for reducing the load of the host system CPU during the data ...
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... Philips Semiconductors 4. Ordering information Table 1: Type number Package ISP1760BE 9397 750 13257 Product data sheet Ordering information Name Description LQFP128 plastic low profile quad flat package; 128 leads; body 1.4 mm Rev. 01 — 8 November 2004 ISP1760 Embedded Hi-Speed USB host controller © ...
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... Philips Semiconductors 5. Block diagram 47, 49, 51, 52 78, 80 DATA[15:0]/DATA[31:0] 82, 84, 86, 87 98, 100 to 103, 105 17 A[17:1] 106 CS_N 107 RD_N 108 WR_N 112 IRQ 114 DREQ DACK 116 USB FULL-SPEED AND LOW SPEED DATA PATH PORT ROUTING OR CONTROL LOGIC + HOST AND HUB PORT STATUS ...
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... CC(5V0) V CC(5V0) GND V REG(3V3) V CC(I/O) XTAL1 XTAL2 CLKIN GND 9397 750 13257 Product data sheet 1 ISP1760BE 38 Pin description [1] [2] Pin Type Description 1 AI port 3 analog (5 V input) and digital overcurrent input; if not used, connect reference input for analog OC detector; connect a 100 nF ...
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... Philips Semiconductors Table 2: Symbol GND RREF1 GND DM1 GND DP1 PSW1_N GND RREF2 GND DM2 GND DP2 PSW2_N GND RREF3 GND DM3 GND DP3 PSW3_N GND DATA0 DATA1 DATA2 V CC(I/O) DATA3 9397 750 13257 Product data sheet Pin description …continued [1] [2] ...
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... Philips Semiconductors Table 2: Symbol DATA4 DATA5 GND DATA6 DATA7 DATA8 V CC(I/O) DATA9 V REG(1V8) DATA10 DATA11 GND DATA12 GND DATA13 DATA14 DATA15 V CC(I/O) 9397 750 13257 Product data sheet Pin description …continued [1] [2] Pin Type Description 42 I/O data bit 4 input and output bidirectional pad, push-pull input, three-state output output drive, 3 ...
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... Philips Semiconductors Table 2: Symbol DATA16 DATA17 DATA18 GND DATA19 DATA20 DATA21 V CC(I/O) DATA22 DATA23 DATA24 GND DATA25 DATA26 DATA27 V CC(I/O) DATA28 9397 750 13257 Product data sheet Pin description …continued [1] [2] Pin Type Description 60 I/O data bit 16 input and output bidirectional pad, push-pull input, three-state output output drive, 3 ...
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... Philips Semiconductors Table 2: Symbol DATA29 DATA30 GND DATA31 TEST A1 V CC(I/ REG(1V8 GND A5 GND CC(I/O) A9 A10 A11 A12 9397 750 13257 Product data sheet Pin description …continued [1] [2] Pin Type Description 77 I/O data bit 29 input and output bidirectional pad, push-pull input, three-state output output drive, 3 ...
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... Philips Semiconductors Table 2: Symbol GND A13 A14 A15 A16 V CC(I/O) A17 CS_N RD_N WR_N GND V BAT_ON_N n.c. IRQ n.c. DREQ V CC(I/O) DACK TEST V REG(1V8) SUSPEND/ WAKEUP_ N 9397 750 13257 Product data sheet Pin description …continued [1] [2] Pin Type Description 99 - digital ground ...
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... Philips Semiconductors Table 2: Symbol TEST GND RESET_N GND TEST TEST TEST OC1_N OC2_N [1] Symbol names ending with underscore N (for example, NAME_N) represent active LOW signals. [ input only output only; I/O = digital input/output open-drain output; AI/O = analog input/output analog input power. 9397 750 13257 ...
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... Philips Semiconductors 7. Functional description 7.1 ISP1760 internal architecture: Advanced Philips Slave Host Controller and hub The EHCI block and the Hi-Speed USB hub block are the main components of the Advanced Philips Slave Host Controller. The EHCI is the latest generation design, with improved data bandwidth. The EHCI in the ISP1760 is adapted from Enhanced Host Controller Interface Specifi ...
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... Philips Semiconductors Fig 3. Internal hub. 7.2 Host Controller buffer memory block 7.2.1 General considerations The internal addressable Host Controller buffer memory is 63 kbytes. The 63-kbyte effective memory size is the result of subtracting the size of registers (1 kbyte) from the total addressable memory space defined in the ISP1760 (64 kbytes). This is the optimized value for achieving the highest performance with a minimal cost ...
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... Philips Semiconductors The total amount of memory allocated to the payload determines the maximum transfer size specifi PTD—a larger internal memory size results in less CPU interruption for transfer programming. This means less time spent in context switching, resulting in better CPU usage. A larger buffer also implies a larger amount of data can be transferred. The transfer, however, can be done over a longer period of time, to maintain the overall system performance ...
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... Philips Semiconductors The RAM is structured in blocks of PTDs and payloads so that while the USB is executing on an active transfer-based PTD, the processor can simultaneously fill up another block area in the RAM. A PTD and its payload can then be updated on-the-fly without stopping or delaying any other USB transaction or corrupting the RAM data. ...
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... Philips Semiconductors 63 kbytes USB HIGH-SPEED USB BUS HOST AND TRANSACTION TRANSLATOR (FULL-SPEED AND LOW-SPEED) Fig 4. Memory segmentation and access block diagram. Both the CPU interface logic and the USB Host Controller require access to the internal ISP1760 RAM at the same time. The internal arbiter controls these accesses to the internal memory, organized internally on a 64-bit data bus width, allowing a maximum bandwidth of 240 MB/s ...
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... Philips Semiconductors register access must always be completed using two subsequent accesses. In the case of a DMA transfer, the 16-bit or 32-bit data bus width configuration will determine the number of bursts that will complete a certain transfer length. In PIO mode, CS_N, WR_N and RD_N are used to access registers and memory. In DMA mode, the data validation is performed by DACK— ...
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... Philips Semiconductors 7.3.3 PIO mode access—register read cycle The PIO register read access is similar to a general register access not necessary to set a prefetching address before a register read. The ISP1760 register read address will not be automatically incremented during consecutive read accesses, unlike in a series of ISP1760 memory read cycles. The ISP1760 register read address must be correctly specifi ...
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... Philips Semiconductors It is also possible that the system’s DMA will perform a memory-to-memory type of transfer between the system memory and the ISP1760 memory. The ISP1760 will be accessed in the PIO mode. Consequently, memory read operations must be preceded by initializing the Memory register (address 033Ch), as described in will be generated by the ISP1760 on completing the DMA transfer but an internal processor interrupt may be generated to signal that the DMA transfer is completed ...
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... Philips Semiconductors 3. Define the IRQ polarity as active LOW or active HIGH in INTR_POL (bit 2) of the HW Mode Control register. These settings must match the IRQ settings of the host processor. By default, interrupt is level-triggered and active LOW. 4. Program the individual interrupt enable bits in the Interrupt Enable register. The software will need to clear the interrupt status bits in the Interrupt register before enabling individual interrupt enable bits ...
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... Philips Semiconductors With the help of the IRQ Mask AND and IRQ Mask OR registers for each type of transfer—ISO, INT and bulk—software can determine which PTDs get priority and an interrupt will be generated when the AND or OR conditions are met. The PTDs that are set will wait until the respective bits of the remaining PTDs are set and then all PTDs generate an interrupt request to the CPU together ...
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... Philips Semiconductors The PLL block generates all the main internal clocks required for normal functionality of various blocks: 30 MHz, 48 MHz and 60 MHz. No external components are required for the PLL operation. 7.6 Power management The ISP1760 implements a flexible power management scheme, allowing various power saving stages ...
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... Philips Semiconductors Additionally, the Power Down Control register allows the ISP1760 internal blocks to be disabled for lower power consumption as defined in The lowest suspend current that can be achieved is approximately 100 A at room temperature. The suspend current will increase with the increase in temperature, with approximately 300 and typical ...
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... Philips Semiconductors I OC(nom) (1) R Fig 5. Adjusting analog overcurrent detection limit (optional). The digital overcurrent scheme requires using an external power switch with integrated overcurrent detection, such as: LM3526, MIC2526 (2 ports) or LM3544 (4 ports). These devices are controlled by PSWn_N signals corresponding to each port. In the case of overcurrent occurrence, these devices will assert OCn_N signals ...
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... Philips Semiconductors Figure 7 Fig 7. Most commonly used power supply connection. 7.9 Power-on reset (POR) When will be typically 800 ns. The pulse is started when V PORP (1.2 V). To give a better view of the functionality, dips at t2–t3 and t4–t5. If the dip at t4–t5 is too short (that is, < 11 s), the internal POR pulse will not react and will remain LOW ...
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... Philips Semiconductors Fig 9. Clock with respect to the external power-on reset. 9397 750 13257 Product data sheet RESET_N EXTERNAL CLOCK Stable external clock is available at A. Rev. 01 — 8 November 2004 ISP1760 Embedded Hi-Speed USB host controller 004aaa583 A © Koninklijke Philips Electronics N.V. 2004. All rights reserved. ...
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... Philips Semiconductors 8. Registers Table 5 • All registers range from 0000h to 03FFh. These registers can be read or written as double word, that is 32-bit data. In the case of a 16-bit data bus width, two subsequent accesses are necessary to complete the register read or write cycle. • Operational registers range from 0000h to 01FFh. Configuration registers range from 0300h to 03FFh ...
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... Philips Semiconductors Table 5: Address 0340h 0344h 0354h 0374h Interrupt registers 0310h 0314h 0318h 031Ch 0320h 0324h 0328h 032Ch 8.1 EHCI capability registers 8.1.1 CAPLENGTH register (R: 0000h) The bit description of the Capability Length (CAPLENGTH) register is given in Table 6: Bit CAPLENGTH 8.1.2 HCIVERSION register (R: 0002h) Table 7 (HCIVERSION) register ...
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... Philips Semiconductors Bit 23 Symbol Reset 0 Access R Bit 15 Symbol Reset 0 Access R Bit 7 Symbol PRR Reset 0 Access R Table 9: Bit [1] For details on register bit description, refer to Enhanced Host Controller Interface Specification for Universal Serial Bus Rev. 1.0 . 8.1.4 HCCPARAMS register (R: 0008h) The Host Controller Capability Parameters (HCCPARAMS) register is a four-byte register, ...
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... Philips Semiconductors Bit 23 Symbol Reset 0 Access R Bit 15 Symbol Reset 0 Access R Bit 7 Symbol Reset 1 Access R Table 11: Bit [1] For details on register bit description, refer to Enhanced Host Controller Interface Specification for Universal Serial Bus Rev. 1.0 . 8.2 EHCI operational registers 8.2.1 USBCMD register (R/W: 0020h) The USB Command (USBCMD) register indicates the command to be executed by the serial Host Controller ...
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... Philips Semiconductors Table 12: USBCMD register: bit allocation Bit 31 Symbol Reset 0 Access R/W R/W Bit 23 Symbol Reset 0 Access R/W R/W Bit 15 Symbol Reset 0 Access R/W R/W Bit 7 Symbol LHCR Reset 0 Access R/W R/W [1] The reserved bits should always be written with the reset value. ...
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... Philips Semiconductors Table 14: USBSTS register: bit allocation Bit 31 Symbol Reset 0 Access R/W R/W Bit 23 Symbol Reset 0 Access R/W R/W Bit 15 Symbol Reset 0 Access R/W R/W Bit 7 Symbol Reset 0 Access R/W R/W [1] The reserved bits should always be written with the reset value. ...
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... Philips Semiconductors Bit 23 Symbol Reset 0 Access R/W R/W Bit 15 Symbol Reset 0 Access R/W R/W Bit 7 Symbol Reset 0 Access R/W R/W [1] The reserved bits should always be written with the reset value. Table 17: Bit For details on register bit description, refer to Enhanced Host Controller Interface Specification for Universal [1] Serial Bus Rev ...
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... Philips Semiconductors Bit 23 Symbol Reset 0 Access R/W R/W Bit 15 [1] Symbol reserved Reset 0 Access R/W R/W Bit 7 Symbol Reset 0 Access R/W R/W [1] The reserved bits should always be written with the reset value. Table 19: Bit For details on register bit description, refer to Enhanced Host Controller Interface Specification for Universal [1] Serial Bus Rev ...
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... Philips Semiconductors Bit 23 Symbol Reset 0 Access R/W R/W Bit 15 Symbol Reset 0 Access R/W R/W Bit 7 Symbol Reset 0 Access R/W R/W [1] The reserved bits should always be written with the reset value. Table 21: Bit [1] For details on register bit description, refer to Enhanced Host Controller Interface Specification for Universal Serial Bus Rev ...
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... Philips Semiconductors Bit 15 Symbol PIC[1:0] Reset 0 Access R Bit 7 Symbol SUSP FPR Reset 0 Access R/W R/W [1] The reserved bits should always be written with the reset value. Table 23: Bit [1] For details on register bit description, refer to Enhanced Host Controller Interface Specification for Universal Serial Bus Rev ...
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... Philips Semiconductors Table 24: Bit This register represents a direct map of the done status of the 32 PTDs. The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. Reading the Done Map register will clear all the bits that are set to logic 1, and the next reading will refl ...
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... Philips Semiconductors This register represents a direct map of the done status of the 32 PTDs. The bit corresponding to a certain PTD will be set to logic 1 as soon as that PTD execution is completed. Reading the Done Map register will clear all the bits that are set to logic 1, and the next reading will refl ...
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... Philips Semiconductors Table 31: Bit ATL_PTD_SKIP When a bit in the PTD Skip Map is set to logic 1 that PTD will be skipped although its V bit may be set. The information in that PTD is not processed. For example, NextPTDPointer will not affect the order of processing of PTDs. The Skip bit should not be normally set on the position indicated by NextPTDPointer ...
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... Philips Semiconductors Bit 7 Symbol reserved DACK_ POL Reset 0 Access R/W R/W [1] The reserved bits should always be written with the reset value. Table 34: Bit 9397 750 13257 Product data sheet DREQ_ reserved POL R/W R/W HW Mode Control register: bit description Symbol Description ALL_ATX_ All ATX Reset: For debugging purposes (not used normally) ...
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... Philips Semiconductors 8.3.2 Chip ID register (R: 0304h) Read this register to get the ID of the ISP1760. The upper word of the register contains the hardware version number and the lower word contains the chip ID. bit description of the register. Table 35: Bit CHIPID 8.3.3 Scratch register (R/W: 0308h) This register is for testing and debugging purposes only ...
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... Philips Semiconductors Table 38: Bit 8.3.5 DMA Configuration register (R/W: 0330h) The bit allocation of the DMA Configuration register is given in Table 39: DMA Configuration register: bit allocation Bit 31 Symbol Reset 0 Access R/W R/W Bit 23 Symbol Reset 0 Access R/W R/W Bit 15 Symbol ...
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... Philips Semiconductors Table 40: Bit 8.3.6 Buffer Status register (R/W: 0334h) Table 41 Table 41: Buffer Status register: bit allocation Bit 31 Symbol Reset 0 Access R/W R/W Bit 23 Symbol Reset 0 Access R/W R/W Bit 15 Symbol Reset 0 Access R/W R/W Bit 7 Symbol Reset 0 Access R/W R/W [1] The reserved bits should always be written with the reset value ...
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... Philips Semiconductors Table 42: Bit 8.3.7 ATL Done Timeout register (R/W: 0338h) The bit description of the ATL Done Timeout register is given in Table 43: Bit 8.3.8 Memory register (R/W: 033Ch) The Memory register contains the base memory read address and the respective bank. This register needs to be set only before a first memory read cycle. Once written, the address will be latched for the bank and will be incremented for every read of that bank, until a new address for that bank is written to change the address pointer ...
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... Philips Semiconductors Bit 15 Symbol Reset 0 Access R/W R/W Bit 7 Symbol Reset 0 Access R/W R/W [1] The reserved bits should always be written with the reset value. Table 45: Bit 8.3.9 Edge Interrupt Count register (R/W: 0340h) Table 46 Table 46: Edge Interrupt Count register: bit allocation ...
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... Philips Semiconductors Table 47: Bit 8.3.10 DMA Start Address register (W: 0344h) This register defines the start address select for the DMA read and write operations. See Table 48 Table 48: DMA Start Address register: bit allocation Bit 31 Symbol Reset 0 Access W Bit 23 Symbol Reset 0 Access ...
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... Philips Semiconductors Table 50: Power Down Control register: bit allocation Bit 31 Symbol Reset 0 Access R/W R/W Bit 23 Symbol Reset 1 Access R/W R/W Bit 15 Symbol reserved Reset 0 Access R/W R/W Bit 7 [1] Symbol reserved Reset 1 Access R/W R/W [1] The reserved bits should always be written with the reset value. ...
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... Philips Semiconductors Table 51: [1] Bit [1] For a 32-bit operation, the default wake-up counter value For a 16-bit operation, the wake-up counter value is 50 ms. In the 16-bit operation, read and write back the same value on initialization. 8.3.12 Port 1 Control register (R/W: 0374h) The values read from the lower 16 bits and the upper 16 bits of this register are always the same ...
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... Philips Semiconductors Table 52: Port 1 Control register: bit allocation Bit 31 Symbol Reset 0 Access R/W R/W Bit 23 Symbol PORT1_ INIT2 Reset 1 Access R/W R/W Bit 15 Symbol Reset 0 Access R/W R/W Bit 7 Symbol PORT1_ INIT1 Reset 0 Access R/W R/W [1] The reserved bits should always be written with the reset value. ...
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... Philips Semiconductors 8.4 Interrupt registers 8.4.1 Interrupt register (R/W: 0310h) The bits of this register indicate the interrupt source, defining the events that determined the INT generation. Clearing the bits that were set because of the events listed is done by writing back logic 1 to the respective position. All bits must be reset before enabling new interrupt events ...
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... Philips Semiconductors Table 55: Bit 8.4.2 Interrupt Enable register (R/W: 0314h) This register allows enabling or disabling of the IRQ generation because of various events as described in Table 56: Interrupt Enable register: bit allocation Bit 31 Symbol Reset 0 Access R/W R/W Bit 23 Symbol Reset 0 Access R/W R/W 9397 750 13257 ...
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... Philips Semiconductors Bit 15 Symbol Reset 0 Access R/W R/W Bit 7 Symbol INT_IRQ_E CLK READY _E Reset 0 Access R/W R/W [1] The reserved bits should always be written with the reset value. Table 57: Bit 9397 750 13257 Product data sheet [1] reserved R/W R [1] HCSUSP_ reserved R/W ...
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... Philips Semiconductors Table 57: Bit 8.4.3 ISO IRQ Mask OR register (R/W: 0318h) Each bit of this register corresponds to one of the 32 ISO PTDs defined, and is a hardware IRQ mask for each PTD done map. See see Section Table 58: Bit ISO_IRQ_ 8.4.4 INT IRQ Mask OR register (R/W: 031Ch) Each bit of this register (see and is a hardware IRQ mask for each PTD done map ...
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... Philips Semiconductors Table 60: Bit ATL_IRQ_ 8.4.6 ISO IRQ Mask AND register (R/W: 0324h) Each bit of this register corresponds to one of the 32 ISO PTDs defined, and is a hardware IRQ mask for each PTD done map. For details, see Table 61 Table 61: Bit ISO_IRQ_ 8.4.7 INT IRQ Mask AND register (R/W: 0328h) Each bit of this register (see and is a hardware IRQ mask for each PTD done map ...
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... Philips Semiconductors Table 63: Bit ATL_IRQ_ 9. Philips Transfer Descriptor The standard EHCI data structures as described in Enhanced Host Controller Interface Specification for Universal Serial Bus Rev. 1.0 are optimized for the bus master operation that is managed by the hardware state machine. The PTD structures of the ISP1760 are translations of the EHCI data structures that are optimized for the ISP1760, while keeping the architecture of the EHCI data structures the same ...
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... Philips Semiconductors Multiple transfers are scheduled to the shared memory for various endpoints by traversing the next link pointer provided by the EHCI data structure, until it reaches the terminate bit in a microframe schedule is enabled, the Host Controller starts executing from the ISO schedule, before it goes to the INTL schedule, and then to the ATL schedule. ...
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... Philips Semiconductors (1) The NULL pointer terminates goes to the next link. Fig 10. NextPTD traversal rule. 9397 750 13257 Product data sheet Embedded Hi-Speed USB host controller START PTD SCHEDULE follow the next link pointer follow the next link pointer no PTD DONE? horizontal ...
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High-speed bulk IN and OUT, Queue Head Asynchronous (QHA) (patent-pending) Table 64: High-speed bulk IN and OUT, QHA: bit allocation Bit ...
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... Philips Semiconductors Table 65: High-speed bulk IN and OUT, QHA: bit description Bit Symbol DW7 reserved DW6 reserved DW5 reserved DW4 reserved NextPTDPointer [4:0] DW3 reserved Cerr[1: NakCnt[3: reserved 9397 750 13257 Product data sheet Access Description - - - - - - - 0; not applicable for QHA. SW — writes Jump: 0 — ...
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... Philips Semiconductors Table 65: High-speed bulk IN and OUT, QHA: bit description Bit Symbol NrBytesTransferred [14:0] DW2 reserved RL[3:0] 24 reserved DataStartAddress [15: reserved DW1 reserved EPType[1: Token[1: DeviceAddress[6:0] SW — writes EndPt[3:1] DW0 31 EndPt[ Mult[1:0] 9397 750 13257 Product data sheet …continued Access Description HW — writes Number of Bytes Transferred: This fi ...
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... Philips Semiconductors Table 65: High-speed bulk IN and OUT, QHA: bit description Bit Symbol MaxPacketLength [10: NrBytesToTransfer [14: reserved 0 V 9397 750 13257 Product data sheet …continued Access Description SW — writes Maximum Packet Length: This field indicates the maximum number of bytes that can be sent to or received from an endpoint in a single data packet ...
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High-speed isochronous IN and OUT, isochronous Transfer Descriptor (iTD) (patent-pending) Table 66: High-speed isochronous IN and OUT, iTD: bit allocation Bit ...
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... Philips Semiconductors Table 67: High-speed isochronous IN and OUT, iTD: bit description Bit Symbol DW7 ISOIN_7[11: ISOIN_6[11: ISOIN_5[7:0] DW6 ISOIN_5[3: ISOIN_4[11: ISOIN_3[11: ISOIN_2[3:0] DW5 ISOIN_2[7: ISOIN_1[11: ISOIN_0[11:0] DW4 Status7[2: Status6[2: Status5[2: Status4[2: Status3[2: Status2[2: Status1[2: Status0[2: SA[7:0] DW3 9397 750 13257 Product data sheet ...
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... Philips Semiconductors Table 67: High-speed isochronous IN and OUT, iTD: bit description Bit Symbol reserved NrBytesTransferred [14:0] DW2 reserved DataStartAddress [15: Frame[7:0] DW1 reserved EPType[1: Token[1: DeviceAddress[6:0] SW — writes EndPt[3:1] DW0 31 EndPt[ Mult[1: MaxPacketLength [10:0] 9397 750 13257 Product data sheet Access Description HW — writes Babble: Not applicable here ...
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... Philips Semiconductors Table 67: High-speed isochronous IN and OUT, iTD: bit description Bit Symbol NrBytesToTransfer [14: reserved 0 V 9397 750 13257 Product data sheet Access Description SW — writes Number of Bytes Transferred: This field indicates the number of bytes that can be transferred by this data structure used to indicate the depth of the DATA fi ...
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High-speed interrupt IN and OUT, Queue Head Periodic (QHP) (patent-pending) Table 68: High-speed interrupt IN and OUT, QHP: bit allocation Bit ...
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... Philips Semiconductors Table 69: High-speed interrupt IN and OUT, QHP: bit description Bit Symbol Access DW7 INT_IN_7[[11:0] HW — writes INT_IN_6[11:0] HW — writes INT_IN_5[7:0] HW — writes DW6 INT_IN_5[3:0] HW — writes INT_IN_4[11:0] HW — writes INT_IN_3[11:0] HW — writes INT_IN_2[3:0] HW — writes DW5 INT_IN_2[7:0] HW — writes ...
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... Philips Semiconductors Table 69: High-speed interrupt IN and OUT, QHP: bit description Bit Symbol Access — writes reserved - — writes SW — writes Cerr[1:0] HW — writes SW — writes reserved - NrBytes HW — writes Transferred [14:0] DW2 reserved - DataStart SW — writes Address [15: Frame[7:0] SW — writes DW1 ...
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... Philips Semiconductors Table 69: High-speed interrupt IN and OUT, QHP: bit description Bit Symbol Access DeviceAddress SW — writes [6: EndPt[3:1] SW — writes DW0 31 EndPt[0] SW — writes Mult[1:0] SW — writes MaxPacket SW — writes Length[10: NrBytesTo SW — writes Transfer[14: reserved - — sets HW — resets 9397 750 13257 ...
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Start and complete split for bulk, Queue Head Asynchronous Start Split and Start Complete (QHA-SS/SC) (patent-pending) Table 70: Start and complete split for bulk, QHASS/SC: bit allocation Bit ...
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... Philips Semiconductors Table 71: Start and complete split for bulk, QHASS/SC: bit description Bit Symbol DW7 reserved DW6 reserved DW5 reserved DW4 reserved NextPTDPointer [1:0] DW3 reserved Cerr[1: NakCnt[3: reserved NrBytesTransferred [14:0] DW2 reserved 9397 750 13257 Product data sheet Access Description ...
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... Philips Semiconductors Table 71: Start and complete split for bulk, QHASS/SC: bit description Bit Symbol RL[3:0] 24 reserved DataStartAddress [15: reserved DW1 HubAddress[6: PortNumber[6: SE[1:0] 47 reserved EPType[1: Token[1: DeviceAddress [6: EndPt[3:1] DW0 31 EndPt[ reserved MaximumPacket Length[10:0] 9397 750 13257 Product data sheet Access Description SW — writes Reload ...
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... Philips Semiconductors Table 71: Start and complete split for bulk, QHASS/SC: bit description Bit Symbol NrBytesToTransfer [14: reserved 0 V 9397 750 13257 Product data sheet Access Description SW — writes Number of Bytes to Transfer: This field indicates the number of bytes that can be transferred by this data structure used to indicate the depth of the DATA fi ...
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Start and complete split for isochronous, Split isochronous Transfer Descriptor (SiTD) (patent-pending) Table 72: Start and complete split for isochronous, SiTD: bit allocation Bit ...
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... Philips Semiconductors Table 73: Start and complete split for isochronous, SiTD: bit description Bit Symbol DW7 reserved ISO_IN_7[7:0] DW6 ISO_IN_6[7: ISO_IN_5[7: ISO_IN_4[7: ISO_IN_3[7:0] DW5 ISO_IN_2[7: ISO_IN_1[7: ISO_IN_0[7: SCS[7:0] DW4 Status7[2: Status6[2: Status5[2: Status4[2: Status3[2: Status2[2: Status1[2: Status0[2: SA[7:0] 9397 750 13257 Product data sheet ...
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... Philips Semiconductors Table 73: Start and complete split for isochronous, SiTD: bit description Bit Symbol DW3 reserved reserved NrBytesTransferred [11:0] DW2 reserved DataStartAddress [15: Frame[7:0] DW1 HubAddress [6: PortNumber [6: reserved EPType[1: Token[1: Device Address[6: EndPt[3:1] DW0 31 EndPt[ reserved 9397 750 13257 Product data sheet ...
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... Philips Semiconductors Table 73: Start and complete split for isochronous, SiTD: bit description Bit Symbol TT_MPS_Len [10: NrBytesTo Transfer [14: reserved 0 V 9397 750 13257 Product data sheet Access Description SW — writes Transaction Translator Maximum Packet Size Length: This field indicates the maximum number of bytes that can be sent per start split depending on the number of total bytes needed. If the total bytes to be sent for the entire ms is greater than 188 bytes, this fi ...
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Start and complete split for interrupt (patent-pending) Table 74: Start and complete split for interrupt: bit allocation Bit ...
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... Philips Semiconductors Table 75: Start and complete split for interrupt: bit description Bit Symbol Access DW7 reserved - INT_IN_7[7:0] HW — writes DW6 INT_IN_6[7:0] HW — writes INT_IN_5[7:0] HW — writes INT_IN_4[7:0] HW — writes INT_IN_3[7:0] HW — writes DW5 INT_IN_2[7:0] HW — writes INT_IN_1[7:0] HW — writes INT_IN_0[7:0] HW — writes ...
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... Philips Semiconductors Table 75: Start and complete split for interrupt: bit description Bit Symbol Access DW3 — sets HW — resets — writes — writes — writes — writes 0 HW — updates 58 reserved - — writes SW — writes Cerr[1:0] HW — writes SW — writes reserved ...
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... Philips Semiconductors Table 75: Start and complete split for interrupt: bit description Bit Symbol Access SE[1:0] SW — writes 47 reserved - — writes EPType[1:0] SW — writes Token[1:0] SW — writes DeviceAddress SW — writes [6: EndPt[3:1] SW — writes DW0 31 EndPt[0] SW — writes reserved - MaxPacket SW — writes Length[10:0] ...
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... Philips Semiconductors 10. Power consumption Table 76: Number of ports working One port working (high-speed Two ports working (high-speed Three ports working (high-speed Remark: The idle operating current, that is, when the ISP1760 is in operational mode—initialized and without any devices connected mA. The additional current consumption on I devices ...
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... Philips Semiconductors 11. Limiting values Table 77: Absolute maximum ratings In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage CC(I/O) V supply voltage CC(5V0) I latch-up current lu V electrostatic discharge voltage esd T storage temperature stg 12. Recommended operating conditions Table 78: Recommended operating conditions ...
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... Philips Semiconductors 13. Static characteristics Table 79: Static characteristics: digital pins Digital pins: A[17:1], DATA[31:0], CS_N, RD_N, WR_N, DACK, DREQ, IRQ, RESET_N, SUSPEND/WAKEUP_N, CLKIN, OC1_N, OC2_N, OC3_N. OC1_N, OC2_N and OC3_N are used as digital overcurrent pins; V otherwise specified Symbol Parameter V HIGH-level input voltage ...
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... Philips Semiconductors Table 82: Static characteristics: USB interface block (pins DM1 to DM3 and DP1 to DP3 1. 3 +85 C; unless otherwise specified. CC(I/O) amb Symbol Parameter Output levels for high-speed V idle state HSOI V data signaling HIGH HSOH V data signaling LOW HSOL V Chirp J level (differential ...
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... Philips Semiconductors 14. Dynamic characteristics Table 84: Dynamic characteristics: system clock timing Symbol Parameter Crystal oscillator [1] f clock frequency clk External clock input J external clock jitter clock duty cycle V amplitude clk rise time and fall time CR CF [1] Recommended accuracy of the clock frequency is 50 ppm for the crystal and oscillator. The oscillator used depends on V [2] Recommended values for external capacitors when using a crystal are ...
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... Philips Semiconductors Table 87: Dynamic characteristics: full-speed source electrical characteristics +85 C; unless otherwise specified. CC(I/O) amb Symbol Parameter Z driver output resistance for DRV the driver that is not high-speed capable Data timing: see Figure 11 t source jitter for differential FDEOP transition to SEO transition ...
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... Philips Semiconductors 14.1 PIO timing 14.1.1 Register or memory write Fig 12. Register or memory write. Table CC(I/O) Symbol t h11 t h21 t h31 t w11 T cy11 t su11 t su21 t su31 Table CC(I/O) Symbol t h11 t h21 t h31 t w11 T cy11 t su11 t su21 t su31 9397 750 13257 Product data sheet ...
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... Philips Semiconductors 14.1.2 Register read Fig 13. Register read. Table CC(I/O) Symbol t su12 t su22 t w12 t d12 t d22 T cy12 Table CC(I/O) Symbol t su12 t su22 t w12 t d12 t d22 T cy12 9397 750 13257 Product data sheet t su12 A[17:1] address 01 t su22 CS_N t d22 ...
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... Philips Semiconductors 14.1.3 Memory read A[17:1] address = 33C DATA data CS_N WR_N RD_N Fig 14. Memory read. Table CC(I/O) Symbol t p13 T cy13 t d13 t d23 t w13 t su13 t su23 Table CC(I/O) Symbol t p13 T cy13 t d13 t d23 t w13 t su13 t su23 9397 750 13257 ...
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... Philips Semiconductors 14.2 DMA timing In the following sections: • Polarity of DACK is active HIGH • Polarity of DREQ is active HIGH. 14.2.1 Single cycle: DMA read Fig 15. DMA read (single cycle). Table CC(I/O) Symbol t a14 t a24 t d14 t w14 t a34 t a44 Table CC(I/O) ...
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... Philips Semiconductors 14.2.2 Single cycle: DMA write Fig 16. DMA write (single cycle). Table CC(I/O) Symbol Parameter t a15 t a25 t h15 t h25 t su15 t a35 t cy15 t w15 Table CC(I/O) Symbol Parameter t a15 t a25 t h15 t h25 t su15 t a35 t cy15 t w15 9397 750 13257 ...
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... Philips Semiconductors 14.2.3 Multicycle: DMA read Fig 17. DMA read (multicycle burst). Table CC(I/O) Symbol Parameter t a16 t a26 t d16 t w16 T cy16 t a36 t a46 Table 100: DMA read (multicycle burst 3 3 CC(I/O) Symbol Parameter t a16 t a26 t d16 t w16 T cy16 t a36 t a46 9397 750 13257 ...
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... Philips Semiconductors 14.2.4 Multicycle: DMA write Fig 18. DMA write (multicycle burst). Table 101: DMA write (multicycle burst 1. 1. CC(I/O) Symbol Parameter T cy17 t su17 t h17 t a17 t a27 t a37 t h27 t a47 t w17 t a57 Table 102: DMA write (multicycle burst 3 3 CC(I/O) Symbol Parameter ...
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... Philips Semiconductors 15. Package outline LQFP128: plastic low profile quad flat package; 128 leads; body 1 102 103 pin 1 index 128 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 1.45 mm 1.6 0.25 0.05 1.35 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
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... Philips Semiconductors 16. Soldering 16.1 Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fi ...
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... CWQCCN..L [1] For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your Philips Semiconductors sales office. [2] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26 ...
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... Philips Semiconductors [4] These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. ...
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... Philips Semiconductors 18. References [1] Universal Serial Bus Specification Rev. 2.0 [2] Enhanced Host Controller Interface Specification for Universal Serial Bus Rev. 1.0 On-The-Go Supplement to the USB Specification Rev. 1.0a [3] [4] Embedded Systems Design with the ISP176x (AN10043) [5] ISP176x Linux Programming Guide (AN10042) ...
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... Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. ...
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... Philips Semiconductors 25. Tables Table 1: Ordering information . . . . . . . . . . . . . . . . . . . . .3 Table 2: Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5 Table 3: Memory address . . . . . . . . . . . . . . . . . . . . . . .15 Table 4: Using the IRQ Mask AND or IRQ Mask OR registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Table 5: Register overview . . . . . . . . . . . . . . . . . . . . . .27 Table 6: CAPLENGTH register: bit description . . . . . . .28 Table 7: HCIVERSION register: bit description . . . . . . .28 Table 8: HCSPARAMS register: bit allocation . . . . . . . .28 Table 9: HCSPARAMS register: bit description . . . . . . .29 Table 10: HCCPARAMS register: bit allocation ...
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... Philips Semiconductors DM1 to DM3 and DP1 to DP3 .84 Table 83: Static characteristics: REF5V . . . . . . . . . . . . .85 Table 84: Dynamic characteristics: system clock timing .86 Table 85: Dynamic characteristics: CPU interface block .86 Table 86: Dynamic characteristics: high-speed source electrical characteristics . . . . . . . . . . . . . . . . .86 Table 87: Dynamic characteristics: full-speed source electrical characteristics . . . . . . . . . . . . . . . . .86 Table 88: Dynamic characteristics: low-speed source electrical characteristics ...
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... Philips Semiconductors 26. Figures Fig 1. Block diagram Fig 2. Pin configuration (LQFP128 Fig 3. Internal hub .13 Fig 4. Memory segmentation and access block diagram .16 Fig 5. Adjusting analog overcurrent detection limit (optional .24 Fig 6. ISP1760 power supply connection .24 Fig 7. Most commonly used power supply connection. .25 Fig 8. ...
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... Philips Semiconductors 27. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3.1 Examples of a multitude of possible applications Ordering information . . . . . . . . . . . . . . . . . . . . . 3 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 Functional description . . . . . . . . . . . . . . . . . . 12 7.1 ISP1760 internal architecture: Advanced Philips Slave Host Controller and hub . . . . . . . . . . . . 12 7 ...
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... Philips Semiconductors 12 Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . 86 14.1 PIO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 14.1.1 Register or memory write . . . . . . . . . . . . . . . . 88 14.1.2 Register read . . . . . . . . . . . . . . . . . . . . . . . . . 89 14.1.3 Memory read . . . . . . . . . . . . . . . . . . . . . . . . . 90 14.2 DMA timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 14.2.1 Single cycle: DMA read . . . . . . . . . . . . . . . . . 91 14.2.2 Single cycle: DMA write . . . . . . . . . . . . . . . . . 92 14.2.3 Multicycle: DMA read . . . . . . . . . . . . . . . . . . . 93 14.2.4 Multicycle: DMA write . . . . . . . . . . . . . . . . . . . 94 15 Package outline ...