ISP1561BM Philips Semiconductors, ISP1561BM Datasheet

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ISP1561BM

Manufacturer Part Number
ISP1561BM
Description
ISP1561BM
Manufacturer
Philips Semiconductors
Datasheet

Specifications of ISP1561BM

Case
QFP

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1. General description
The ISP1561 is a PCI-based, single-chip Universal Serial Bus (USB) Host Controller.
It integrates two Original USB Open Host Controller Interface (OHCI) cores, one
Hi-Speed USB Enhanced Host Controller Interface (EHCI) core and four transceivers
that are compliant with Hi-Speed USB and Original USB. The functional parts of the
ISP1561 are fully compliant with Universal Serial Bus Specification Rev. 2.0 , Open
Host Controller Interface Specifications Rev. 1.0a , Enhanced Host Controller
Interface Specification for Universal Serial Bus Rev. 0 . 95 , PCI Local Bus
Specification Rev. 2.2 and PCI Bus Power Management Interface Specification
Rev. 1.1 .
The integrated high performance USB transceivers enable the ISP1561 to handle all
Hi-Speed USB transfer speed modes high-speed (480 Mbit/s), full-speed (12 Mbit/s)
and low-speed (1.5 Mbit/s). The ISP1561 provides four downstream ports that
enables simultaneous connections of USB devices at different speeds.
The ISP1561 provides three downstream port status indicators—GoodLink™ along
with green and amber LEDs—to allow user-rich messages of the Root Hub
downstream ports status, without requiring detailed port information to be reflected in
the internal registers.
The ISP1561 is fully compatible with various operating system drivers, such as
Microsoft
Windows 98 Second Edition (SE), Windows Millennium Edition (Me), Windows XP
and Windows 2000.
The ISP1561 directly interfaces to any 32-bit, 33 MHz PCI bus. It has 5 V-tolerant PCI
pins that can source 3.3 V. The PCI interface fully complies with PCI Local Bus
Specification, Rev. 2.2 .
The ISP1561 is ideally suited for use in Hi-Speed USB host-enabled motherboards,
Hi-Speed USB host PCI add-on card applications, mobile applications, and
embedded solutions.
To facilitate motherboard development, the ISP1561 can use the available 48 MHz
clock signal to reduce the total cost of a solution. However, to reduce the
electromagnetic interference (EMI), it is recommended that the 12 MHz clock is used
in PCI add-on card designs.
ISP1561
Hi-Speed USB PCI host controller
Rev. 01 — 06 February 2003
®
Windows
®
standard OHCI and EHCI drivers that are present in
Product data

Related parts for ISP1561BM

ISP1561BM Summary of contents

Page 1

ISP1561 Hi-Speed USB PCI host controller Rev. 01 — 06 February 2003 1. General description The ISP1561 is a PCI-based, single-chip Universal Serial Bus (USB) Host Controller. It integrates two Original USB Open Host Controller Interface (OHCI) cores, one Hi-Speed ...

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... Philips Semiconductors 1.1 Abbreviations DID — Device ID EHCI — Enhanced Host Controller Interface EMI — electromagnetic interference HC — Host Controller HCCA — Host Controller Communication Area HCD — Host Controller Driver OHCI — Open Host Controller Interface PMC — Power Management Capabilities PME — ...

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... Philips Semiconductors 2. Features Complies with Universal Serial Bus Specification Rev. 2.0 Supports data transfer at high-speed (480 Mbit/s), full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s) Two Original USB OHCI cores comply with Open Host Controller Interface Specification for USB Rev. 1.0a One Hi-Speed USB EHCI core complies with Enhanced Host Controller Interface Specifi ...

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... Philips Semiconductors 4. Ordering information Table 1: Ordering information Type number Package Name Description ISP1561BM LQFP128 plastic low profile quad flat package; 128 leads; body 1.4 mm 9397 750 10015 Product data Rev. 01 — 06 February 2003 ISP1561 USB PCI host controller Version SOT420-1 © ...

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... OC3 OC2 AMB3 AMB2 GRN3 GRN2 GL3 GL2 PWE3 PWE2 DM1 DP1 DM3 DP3 ISP1561BM 7 IRQ1 8 IRQ12 legacy keyboard and mouse support 12 KBIRQ1 13 MUIRQ12 11 A20OUT 9 EHCI (FUNCTION 2) SEL2PORTS 101 RAM ...

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... REQ# 22 AD[31] 23 AD[30 AD[29] 26 AD[28] 27 AD[27] 28 DGND 29 AD[26] 30 AD[25] 31 AD[24] 32 Fig 2. Pin configuration. 9397 750 10015 Product data ISP1561BM Rev. 01 — 06 February 2003 ISP1561 USB PCI host controller 96 OC2 95 GRN1 94 GND_RREF 93 AV AUX 92 AMB1 91 GL1 90 PWE1 89 OC1 88 XTAL2 87 XTAL1 86 DGND ...

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... Philips Semiconductors 6.2 Pin description Table 2: Symbol SEL48M SCL SDA PME# V AUX DGND IRQ1 IRQ12 SEL2PORTS V DD A20OUT KBIRQ1 MUIRQ12 DGND SMI# INTA RST# CLK GNT# DGND 9397 750 10015 Product data Pin description [1] Pin Type Description 1 I selection between 12 MHz crystal and 48 MHz oscillator; ...

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... Philips Semiconductors Table 2: Symbol REQ# AD[31] AD[30 AD[29] AD[28] AD[27] DGND AD[26] AD[25] AD[24 C/BE#[3] IDSEL AD[23] DGND AD[22] AD[21] AD[20 AD[19] AD[18] AD[17] DGND AD[16] C/BE#[2] FRAME IRDY# TRDY# DEVSEL# DGND STOP# CLKRUN# 9397 750 10015 Product data Pin description … ...

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... Philips Semiconductors Table 2: Symbol PERR SERR# PAR C/BE#[1] DGND AD[15] AD[14] AD[13 AD[12] AD[11] AD[10] DGND AD[9] AD[8] C/BE#[ AD[7] AD[6] DGND AD[5] AD[4] AD[ AD[2] AD[1] DGND AD[0] V AUX DGND XTAL1 XTAL2 OC1 9397 750 10015 Product data Pin description …continued ...

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... Philips Semiconductors Table 2: Symbol PWE1 GL1 AMB1 AV AUX GND_RREF GRN1 OC2 PWE2 GL2 AMB2 GRN2 AV AUX_PLL DM1 DP1 AGND OC3 9397 750 10015 Product data Pin description …continued [1] Pin Type Description 90 I/O power enable for the USB downstream port 1 (open-drain). Bi-directional pin; push-pull input; three-state output slew rate control ...

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... Philips Semiconductors Table 2: Symbol PWE3 RREF AV AUX DM2 DP2 AGND GL3 AMB3 GRN3 AV AUX DM3 DP3 AGND OC4 PWE4 AV AUX DM4 DP4 AGND GL4 9397 750 10015 Product data Pin description …continued [1] Pin Type Description 106 I/O power enable for the USB downstream port 3 (open-drain). ...

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... Philips Semiconductors Table 2: Symbol AMB4 GRN4 DGND [1] Symbol names ending with a ‘#’ (for example, NAME#) represent active LOW signals for PCI pins. Symbol names with an overscore (for example, NAME) represent active LOW signals for USB pins. [2] The pull-up resistor should be always present even if I [3] If legacy support is not used, connect this pin to ground ...

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... Philips Semiconductors 7. Functional description 7.1 OHCI Host Controller An OHCI Host Controller transfers data to devices at the Original USB defined bit rate of 12 Mbit/s or 1.5 Mbit/s. 7.2 EHCI Host Controller The EHCI Host Controller transfers data to a Hi-Speed USB compliant device at the Hi-Speed USB defined bit rate of 480 Mbit/s. When the EHCI Host Controller has the ownership of a port, the OHCI Host Controllers are not allowed to modify the port register. All additional port bit defi ...

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... Philips Semiconductors All LED indicators are open-drain output. 7.6 Power management The ISP1561 provides an advanced power management capabilities interface that is compliant with PCI Bus Power Management Interface Specification, Rev. 1.1 . Power is controlled and managed by the interaction between drivers and PCI registers. See Section 10 7 ...

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... Philips Semiconductors 8.1.2 PCI Initiator/Target A PCI initiator initiates PCI transactions to the PCI bus; a PCI target responds to PCI transactions as a slave. In the case of the ISP1561, the two Open Host Controllers and the Enhanced Host Controller function as both initiators or the targets of PCI transactions issued by the host CPU. ...

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... PCI Special Interest Group (PCI-SIG) assigns valid vendor identifiers to ensure the uniqueness of the identifier. The bit description is shown in Table 4: Bit Device ID register (address: 02H): identifies a particular device. This identifier is allocated by Philips Semiconductors. Table 5 Table 5: Bit [ for OHCI1 and OHCI2 and for EHCI. ...

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... Philips Semiconductors Command register (address: 04H): control over the ability of a device to generate and respond to PCI cycles. The bit allocation of the Command register is given in register, the device is logically disconnected from the PCI bus for all accesses except configuration accesses. All devices are required to support this base level of functionality ...

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... Philips Semiconductors Table 7: Bit Status register (address: 06H): used to record status information on PCI bus-related events (bit allocation: see Table Table 8: Status register: bit allocation Bit 15 14 Symbol DPE SSE Reset 0 0 Access R R Bit 7 6 Symbol FBBC reserved Reset 0 0 Access ...

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... Philips Semiconductors Table 9: Bit 9397 750 10015 Product data Status register: bit description Symbol Description DPE Detected Parity Error: This bit must be set by the device whenever it detects a parity error, even if the parity error handling is disabled. SSE Signaled System Error: This bit must be set whenever the device asserts SERR# ...

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... Philips Semiconductors Table 9: Bit Revision ID register (address: 08H): device specific revision identifier. The value is chosen by the vendor. This field is a vendor defined extension of the Device ID. The Revision ID register bit description is given in Table 10: Revision ID register: bit description Bit Symbol Access ...

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... Philips Semiconductors Table 12: Bit CacheLine Size register (address: 0CH): read/write single byte register that specifies the system cacheline size in units of DWords. This register must be implemented by master devices that can generate the Memory Write and Invalidate command. The value in this register is also used by master devices to determine whether to use Read, Read Line, or Read Multiple commands for accessing memory ...

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... Philips Semiconductors Table 16: Bit BIST register (address: 0FH): Self Test (BIST). Devices that do not support BIST must always return a value of logic 0 (that is, treat reserved register). A device whose BIST is invoked must not prevent normal operation of the PCI bus. The BIST register is not used in the ISP1561 ...

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... Philips Semiconductors. Subsystem ID values are vendor specific. Value Description [1] 156XH Subsystem ID: For the ISP1561, Philips Semiconductors has defined OHCI functions as 1561H, and the EHCI function as 1562H. Value Description DCH Capabilities Pointer: EHCI manages power efficiently using this register. This Power Management register is allocated at offset DCH ...

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... Philips Semiconductors Interrupt Pin register (address: 3DH): which interrupt pin the device (or device function) uses. The bit description is given in Table A value of 1H corresponds to INTA#. A value of 2H corresponds to INTB#. A value of 3H corresponds to INTC#. A value of 4H corresponds to INTD#. Devices or functions that do not use an interrupt pin must put a logic 0 in this register. ...

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... Philips Semiconductors Table 26: SBRN register: bit description Bit Symbol Access SBRN[7:0] R FLADJ register (address: 61H): clock source that generates the clock that drives the SOF counter. When a new value is written to these six bits, the length of the frame is adjusted. The bit allocation of the ...

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... Philips Semiconductors EHCI Host Controller. The system-specific policy can be established by BIOS initializing this register to a system-specific value. System software uses the information in this register when enabling devices and ports for remote wake-up. Table 29: PORTWAKECAP register: bit description Bit Symbol ...

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... Philips Semiconductors Table 33: PMC register: bit allocation Bit 15 14 Symbol [1] Reset X 1 Access R R Bit 7 6 Symbol AUX_C[2:0] Reset 0 0 Access for OHCI1, OHCI2 and EHCI S1 for EHCI S3. [ for OHCI1 and OHCI2 for EHCI. Table 34: Bit 9397 750 10015 Product data ...

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... Philips Semiconductors Table 34: Bit The logic level of the AMB4 pin at power-on determines the default value of the PMC registers. If this pin is connected cold the ISP1561 does not support D3 9397 750 10015 Product data PMC register: bit description …continued Symbol Description AUX_C[2:0] Aux_Current: This three-bit field reports the V current requirements for the PCI function ...

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... Philips Semiconductors PMCSR register (address: value read from address 34H + 4H): Management Control/Status (PMCSR) register is a two-byte register used to manage the power management state of the PCI function as well as to enable and monitor Power Management Events (PMEs). The bit allocation of the register is given in ...

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... Philips Semiconductors Table 36: Bit PMCSR_BSE register (address: value read from address 34H + 6H): PMCSR PCI-to-PCI Bridge Support Extensions (PMCSR_BSE) register supports PCI bridge specific functionality and is required for all PCI-to-PCI bridges. The bit allocation of this register is given in Table 37: PMCSR_BSE register: bit allocation ...

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... Philips Semiconductors Table 38: Bit Table 39: PCI bus power and clock control Originating device’s bridge PM state hot D3 cold Data register (address: value read from address 34H + 7H): an optional, 1-byte register that provides a mechanism for the function to report state dependent operating data, such as power consumed or heat dissipation. ...

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... Philips Semiconductors C-bus interface A simple I product ID and some other configuration bits from an external EEPROM. 2 The I serial bus wires, SDA (data) and SCL (clock). Both lines are driven by open-drain circuits and must be connected to the positive supply voltage via pull-up resistors. 9.1 Protocol ...

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... Information loading from EEPROM Figure 4 the default values of Device ID (DID), Vendor ID (VID), subsystem VID and subsystem DID assigned to Philips Semiconductors by PCI-SIG will be loaded. See Table 3 to Designing a USB 2.0 Host PCI Adapter Using the ISP1561 Application Note and ISP1561 Evaluation Board User’s Guide . ...

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... Philips Semiconductors B3 state (PCI clock = Stop, PCI bus power = OFF) — V all devices on the PCI bus segment. 10.2 USB bus states Reset state — When the USB bus is in the reset state, the USB system is stopped. Operational state — When the USB bus is in the active state, the USB system is operating normally. Suspend state — ...

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Table 41: USB Host Controller registers Address OHCI Register (Hex) Func0 OHCI1 (2P) 00 HcRevision 00000110 04 HcControl 00000000 08 HcCommandStatus 00000000 0C HcInterruptStatus 00000000 10 HcInterruptEnable 00000000 14 HcInterruptDisable 00000000 18 ...

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Table 41: USB Host Controller registers …continued Address OHCI Register (Hex) Func0 OHCI1 (2P) 104 HceInput 00000000 108 HceOutput 00000000 10C HceStatus 00000000 [1] Reset hex values that are highlighted (for example, ...

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... Philips Semiconductors For the OHCI Host Controller, these registers are divided into two types: one set of operational registers for the USB operation and one set of legacy support registers for the legacy keyboard and mouse operation. For the Enhanced Host Controller, there are two types of registers: one set of read-only capability registers and one set of read/write operational registers ...

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... Philips Semiconductors Table 43: Bit 11.1.2 HcControl register (address: value read from func0 or func1 of address 10H The HcControl register defines the operating modes for the Host Controller. All the fields in this register, except for HostControllerFunctionalState (HCFS) and RemoteWakeupConnected (RWC), are modified only by the HCD. The bit allocation ...

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... Philips Semiconductors Table 45: Bit 9397 750 10015 Product data HcControl register: bit description Symbol Description - reserved RWE RemoteWakeupEnable: This bit is used by the HCD to enable or disable the remote wake-up feature upon the detection of upstream resume signaling. When this bit is set and the RD bit in HcInterruptStatus is set, a remote wake-up is signaled to the host system ...

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... Philips Semiconductors Table 45: Bit 11.1.3 HcCommandStatus register (address: value read from func0 or func1 of address 10H The HcCommandStatus register is used by the Host Controller to receive commands issued by the HCD, and it also reflects the current status of the Host Controller. To the HCD, it appears “write to set” register. The Host Controller must ensure that bits written as logic 1 become set in the register while bits written as logic 0 remain unchanged in the register ...

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... Philips Semiconductors error is detected, the Host Controller increments the counter and sets the SO (SchedulingOverrun) field in the HcInterruptStatus register. allocation of the HcCommandStatus register. Table 46: HcCommandStatus register: bit allocation Bit 31 30 Symbol Reset 0 0 Access - - Bit 23 22 Symbol Reset 0 0 Access - - Bit 15 14 ...

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... Philips Semiconductors Table 47: Bit 11.1.4 HcInterruptStatus register (address: value read from func0 or func1 of address 10H This register is a four-byte register that provides the status of the events that cause hardware interrupts. The bit allocation of the register is given in event occurs, the Host Controller sets the corresponding bit in this register. When a ...

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... Philips Semiconductors Table 48: HcInterruptStatus register: bit allocation Bit 31 30 Symbol reserved OC Reset 0 0 Access - R/W Bit 23 22 Symbol Reset 0 0 Access - - Bit 15 14 Symbol Reset 0 0 Access - - Bit 7 6 Symbol reserved RHSC Reset 0 0 Access - R/W Table 49: Bit 9397 750 10015 ...

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... Philips Semiconductors Table 49: Bit 11.1.5 HcInterruptEnable register (address: value read from func0 or func1 of address 10H Each enable bit in the HcInterruptEnable register corresponds to an associated interrupt bit in the HcInterruptStatus register. The HcInterruptEnable register is used to control which events generate a hardware interrupt. If the following conditions occur: • ...

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... Philips Semiconductors Bit 7 6 Symbol reserved RHSC Reset 0 0 Access - R/W Table 51: Bit 11.1.6 HcInterruptDisable register (address: value read from func0 or func1 of address 10H Each disable bit in the HcInterruptDisable register corresponds to an associated interrupt bit in the HcInterruptStatus register. The HcInterruptDisable register is coupled with the HcInterruptEnable register ...

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... Philips Semiconductors Bit 23 22 Symbol Reset 0 0 Access - - Bit 15 14 Symbol Reset 0 0 Access - - Bit 7 6 Symbol reserved RHSC Reset 0 0 Access - R/W Table 53: Bit 11.1.7 HcHCCA register (address: value read from func0 or func1 of address 10H The HcHCCA register contains the physical address of the Host Controller Communication Area (HCCA) ...

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... Philips Semiconductors in the lower order bits. The minimum alignment is 256 bytes; therefore, bits 0 through 7 will always return logic 0 when read. This area is used to hold the control structures and the Interrupt table that are accessed by both the Host Controller and the HCD. ...

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... Philips Semiconductors Bit 15 14 Symbol Reset 0 0 Access R R Bit 7 6 Symbol PCED[3:0] Reset 0 0 Access R R Table 57: Bit 11.1.9 HcControlHeadED register (address: value read from func0 or func1 of address 10H The HcControlHeadED register contains the physical address of the first ED of the Control list ...

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... Philips Semiconductors Table 59: Bit 11.1.10 HcControlCurrentED register (address: value read from func0 or func1 of address 10H The HcControlCurrentED register contains the physical address of the current ED of the Control list. The bit allocation is given in Table 60: HcControlCurrentED register: bit allocation Bit 31 30 Symbol Reset ...

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... Philips Semiconductors 11.1.11 HcBulkHeadED register (address: value read from func0 or func1 of address 10H This is a four-byte register, and the bit allocation is given in contains the physical address of the first ED of the Bulk list. Table 62: HcBulkHeadED register: bit allocation Bit 31 30 Symbol Reset ...

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... Philips Semiconductors Bit 15 14 Symbol Reset 0 0 Access R/W R/W Bit 7 6 Symbol BCED[3:0] Reset 0 0 Access R/W R/W Table 65: Bit 11.1.13 HcDoneHead register (address: value read from func0 or func1 of address 10H The HcDoneHead register contains the physical address of the last completed TD that was added to the Done queue ...

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... Philips Semiconductors Bit 7 6 Symbol Reset 0 0 Access R/W R/W Table 67: Bit 11.1.14 HcFmInterval register (address: value read from func0 or func1 of address 10H The HcFmInterval register contains a 14-bit value that indicates the bit time interval in a frame, (that is, between two consecutive SOFs) and a 15-bit value indicating the full-speed maximum packet size that the Host Controller may transmit or receive without causing a scheduling overrun ...

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... Philips Semiconductors Table 69: Bit 11.1.15 HcFmRemaining register (address: value read from func0 or func1 of address 10H The HcFmRemaining register is a 14-bit down counter showing the bit time remaining in the current Frame. Table 70: HcFmRemaining register: bit allocation Bit 31 30 Symbol FRT Reset 0 0 Access ...

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... Philips Semiconductors Table 71: Bit 11.1.16 HcFmNumber register (address: value read from func0 or func1 of address 10H This register is a 16-bit counter, and the bit allocation is given in a timing reference among events happening in the Host Controller and the HCD. The HCD may use the 16-bit value specified in this register and generate a 32-bit frame number without requiring frequent access to the register ...

Page 55

... Philips Semiconductors Table 73: Bit 11.1.17 HcPeriodicStart register (address: value read from func0 or func1 of address 10H The HcPeriodicStart register has a 14-bit programmable value that determines when is the earliest time the Host Controller should start processing the periodic list. The bit allocation is given in ...

Page 56

... Philips Semiconductors 11.1.18 HcLSThreshold register (address: value read from func0 or func1 of address 10H This register contains an 11-bit value used by the Host Controller to determine whether to commit to the transfer of a maximum of 8-byte LS packet before EOF. Neither the Host Controller nor the HCD are allowed to change this value. The bit ...

Page 57

... Philips Semiconductors Table 78: HcRhDescriptorA register: bit allocation Bit 31 30 Symbol Reset 1 1 Access R/W R/W Bit 23 22 Symbol Reset 0 0 Access - - Bit 15 14 Symbol reserved Reset 0 0 Access - - Bit 7 6 Symbol Reset 0 0 Access for OHCI1 (2P) and OHCI2 (2P for OHCI1 (1P) and OHCI2 (1P). ...

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... Philips Semiconductors Table 79: Bit 11.1.20 HcRhDescriptorB register (address: value read from func0 or func1 of address 10H The HcRhDescriptorB register is the second of two registers describing the characteristics of the Root Hub. The bit allocation is given in are written during initialization to correspond with the system implementation. Reset values are implementation-specifi ...

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... Philips Semiconductors Bit 7 6 Symbol Reset 0 0 Access R/W R/W Table 81: Bit 11.1.21 HcRhStatus register (address: value read from func0 or func1 of address 10H The HcRhStatus register is divided into two parts. The lower word of a DWord represents the Hub Status field and the upper word represents the Hub Status Change fi ...

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... Philips Semiconductors Bit 7 6 Symbol Reset 0 0 Access - - Table 83: Bit 9397 750 10015 Product data reserved HcRhStatus register: bit description Symbol Description CRWE On write—ClearRemoteWakeupEnable: Writing logic 1 clears DRWE (DeviceRemoteWakeupEnable). Writing logic 0 has no effect. - reserved CCIC OverCurrentIndicatorChange: This bit is set by hardware when a change has occurred to the OCI (OverCurrentIndicator) fi ...

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... Philips Semiconductors 11.1.22 HcRhPortStatus[1:4] register (address: value read from func0 or func1 of address 10H The HcRhPortStatus[1:4] register is used to control and report port events on a per-port basis. NumberDownstreamPorts represents the number of HcRhPortStatus registers that are implemented in hardware. The lower word is used to reflect the port status, whereas the upper word refl ...

Page 62

... Philips Semiconductors Table 85: Bit 9397 750 10015 Product data HCRhPortStatus[1:4] register: bit description Symbol Description PSSC PortSuspendStatusChange: This bit is set when the full resume sequence has been completed. This sequence includes the 20 ms resume pulse, LS EOP and 3 ms re-synchronization delay. The HCD can write logic 1 to clear this bit ...

Page 63

... Philips Semiconductors Table 85: Bit 9397 750 10015 Product data HCRhPortStatus[1:4] register: bit description Symbol Description PPS On read—PortPowerStatus: This bit reflects the port power status, regardless of the type of power switching implemented. This bit is cleared if an overcurrent condition is detected. The HCD can set this bit by writing SetPortPower or SetGlobalPower. The HCD can clear this bit by writing ClearPortPower or ClearGlobalPower ...

Page 64

... Philips Semiconductors Table 85: Bit 9397 750 10015 Product data HCRhPortStatus[1:4] register: bit description Symbol Description PSS On read—PortSuspendStatus: This bit indicates whether the port is suspended the resume sequence set by a SetSuspendState write and cleared when PSSC (PortSuspendStatusChange) is set at the end of the resume interval ...

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... Philips Semiconductors 11.2 USB legacy support registers The ISP1561 supports legacy keyboards and mice. Four operational registers are used to provide the legacy support. Each of these registers is located on a 32-bit boundary. The offset of these registers is relative to the base address of the Host Controller operational registers with HceControl located at offset 100H. ...

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... Philips Semiconductors Table 89: Bit 11.2.2 HceInput register (address: value read from func0 or func1 of address 10H + 104H) The HceInput register is a four-byte register, and the bit allocation is given in Table when emulation is enabled. This register may be read or written directly by accessing it in the Host Controller’s operational register space. When accessed directly in a memory cycle, reads and writes of this register have no side effects ...

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... Philips Semiconductors Table 90: HceInput register: bit allocation Bit 31 30 Symbol Reset 0 0 Access - - Bit 23 22 Symbol Reset 0 0 Access - - Bit 15 14 Symbol Reset 0 0 Access - - Bit 7 6 Symbol Reset 0 0 Access R/W R/W Table 91: Bit 11.2.3 HceOutput register (address: value read from func0 or func1 of address ...

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... Philips Semiconductors Bit 7 6 Symbol Reset 0 0 Access R/W R/W Table 93: Bit 11.2.4 HceStatus register (address: value read from func0 or func1 of address 10H + 10CH) The contents of the HceStatus register are returned on an I/O read of port 64H when emulation is enabled. Reads and writes of port 60H and writes to port 64H can cause changes in this register. Emulation software can directly access this register through its memory address in the Host Controller’ ...

Page 69

... Philips Semiconductors Table 95: Bit 11.3 EHCI controller capability registers Other than the OHCI Host Controller, there are some registers in EHCI that define the capability of EHCI. The address range of these registers is located before the operational registers. 11.3.1 CAPLENGTH/HCIVERSION register (address: value read from func2 of address ...

Page 70

... Philips Semiconductors Table 97: Bit 11.3.2 HCSPARAMS register (address: value read from func2 of address 10H + 04H) The Host Controller Structural Parameters (HCSPARAMS) register is a set of fields that are structural parameters. The bit allocation is given in Table 98: HCSPARAMS register: bit allocation Bit 31 30 Symbol ...

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... Philips Semiconductors Table 99: Bit 11.3.3 HCCPARAMS register (address: value read from func2 of address 10H + 08H) The Host Controller Capability Parameters (HCCPARAMS) register is a four-byte register, and the bit allocation is given in 9397 750 10015 Product data HCSPARAMS register: bit description Symbol Description N_CC Number of Companion Controller: This fi ...

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... Philips Semiconductors Table 100: HCCPARAMS register: bit allocation Bit 31 30 Symbol Reset 0 0 Access - - Bit 23 22 Symbol Reset 0 0 Access - - Bit 15 14 Symbol Reset 0 0 Access - - Bit 7 6 Symbol Reset 0 0 Access R R Table 101: HCCPARAMS register: bit description Bit 9397 750 10015 ...

Page 73

... Philips Semiconductors 11.4 Operational registers of Enhanced USB Host Controller 11.4.1 USBCMD register (address: value read from func2 of address 10H + 0CH) The USB Command (USBCMD) register indicates the command to be executed by the serial Host Controller. Writing to this register causes a command to be executed. ...

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... Philips Semiconductors Table 103: USBCMD register: bit description Bit 9397 750 10015 Product data Symbol Description - reserved LHCR Light Host Controller Reset: This control bit is not required. It allows the driver software to reset the EHCI controller without affecting the state of the ports or the relationship to the companion Host Controllers. If not implemented, a read of this fi ...

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... Philips Semiconductors Table 103: USBCMD register: bit description Bit 1 0 11.4.2 USBSTS register (address: value read from func2 of address 10H + 10H) The USB Status (USBSTS) register indicates pending interrupts and various states of the Host Controller. The status resulting from a transaction on the serial bus is not indicated in this register ...

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... Philips Semiconductors Bit 7 6 Symbol reserved Reset 0 0 Access - - Table 105: USBSTS register: bit description Bit 9397 750 10015 Product data IAA HSE FLR R/W R/W Symbol Description - reserved ASS Asynchronous Schedule Status Default. The bit reports the current real status of the Asynchronous Schedule. If this bit is zero, the status of the Asynchronous Schedule is disabled ...

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... Philips Semiconductors Table 105: USBSTS register: bit description Bit 11.4.3 USBINTR register (address: value read from func2 of address 10H + 14H) The USB Interrupt Enable (USBINTR) register enables and disables reporting of the corresponding interrupt to the software. When a bit is set and the corresponding interrupt is active, an interrupt is generated to the host ...

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... Philips Semiconductors Bit 15 14 Symbol Reset 0 0 Access - - Bit 7 6 Symbol reserved Reset 0 0 Access - - Table 107: USBINTR register: bit description Bit 11.4.4 FRINDEX register (address: value read from func2 of address 10H + 18H) The Frame Index (FRINDEX) register is used by the Host Controller to index into the periodic frame list ...

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... Philips Semiconductors halted state as indicated by the HCH (HCHalted) bit. A write to this register while the RS (Run/Stop) bit is set produces undefined results. Writes to this register also affect the SOF value. The bit allocation is given in Table 108: FRINDEX register: bit allocation Bit 31 30 ...

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... Philips Semiconductors 11.4.5 CTRLDSSEGMENT register (address: value read from func2 of address 10H + 1CH) The Control Data Structure Segment (CTRLDSSEGMENT) register corresponds to the most significant address bits (bits 63 to 32) for all EHCI data structures. If the 64AC (64-bit Addressing Capability) field in HCCPARAMS is cleared, then this register is not used and software cannot write to it (reading from this register returns zero) ...

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... Philips Semiconductors Table 111: PERIODICLISTBASE register: bit description Bit 11.4.7 ASYNCLISTADDR register (address: value read from func2 of address 10H + 24H) This 32-bit register (bit allocation: asynchronous queue head to be executed. If the Host Controller is in 64-bit mode (as indicated by a one in 64AC (64-bit Addressing Capability) field in the HCCPARAMS register), then the most signifi ...

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... Philips Semiconductors Table 114: CONFIGFLAG register: bit allocation Bit 31 30 Symbol Reset 0 0 Access - - Bit 23 22 Symbol Reset 0 0 Access - - Bit 15 14 Symbol Reset 0 0 Access - - Bit 7 6 Symbol Reset 0 0 Access - - Table 115: CONFIGFLAG register: bit description Bit 11.4.9 PORTSC registers (address: value read from func2 of address 10H + ...

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... Philips Semiconductors Bit 23 22 Symbol reserved WKOC_E Reset 0 0 Access - R/W Bit 15 14 Symbol PIC[1:0] Reset 0 0 Access R R Bit 7 6 Symbol SUSP FPR Reset 0 0 Access R/W R/W Table 117: PORTSC register: bit description Bit PTC[3: PIC[1:0] 9397 750 10015 ...

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... Philips Semiconductors Table 117: PORTSC register: bit description Bit LS[1:0] 9 9397 750 10015 Product data Symbol Description PO Port Owner: Default = 1. This bit unconditionally goes when the Configured bit in the CONFIGFLAG register makes transition. This bit unconditionally goes to 1 whenever the Configured bit is zero. ...

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... Philips Semiconductors Table 117: PORTSC register: bit description Bit 8 7 9397 750 10015 Product data Symbol Description PR Port Reset: logic 1 means the Port is in Reset. A logic 0 means the Port is not in Reset. Default = 0. When software sets this bit (from a logic 0), the bus reset sequence as defined in the Universal Serial Bus Specifi ...

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... Philips Semiconductors Table 117: PORTSC register: bit description Bit 9397 750 10015 Product data Symbol Description FPR Force Port Resume: A logic 1 means Resume detected or driven on the port. A logic 0 means no resume (K-state) detected or driven on the port. Default = 0. Software sets this bit to drive the resume signaling ...

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... Philips Semiconductors Table 117: PORTSC register: bit description Bit [1] These fields read logic 0, if the Port Power (PP) (bit 12 in register PORTSC 1,2,3,4) is logic 0. 9397 750 10015 Product data Symbol Description PED Port Enabled/Disabled: A logic 1 means enable. A logic 0 means disable. Default = 0. Ports can only be enabled by the Host Controller as a part of the reset and enable sequence. Software cannot enable a port by writing a logic 1 to this fi ...

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... Philips Semiconductors 12. Power consumption Table 118 SEL2PORTS pin is connected to V Table 118: Power consumption when SEL2PORTS is HIGH Power pins group total power AUX AUX AUX_PLL DD auxiliary power AUX AUX AUX_PLL V DD [1] When one or two full-speed or low-speed power devices are connected, the power consumption is comparable with the power consumption when no high-speed devices are connected (there is a difference of approximately 1 mA) ...

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... Philips Semiconductors Table 119: Power consumption when SEL2PORTS is LOW Power pins group V DD [1] When one to four full-speed or low-speed power devices are connected, the power consumption is comparable with the power consumption when no high-speed devices are connected (there is a difference of only about 3 mA). ...

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... Philips Semiconductors 13. Limiting values Table 121: Absolute maximum ratings In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage DD V auxiliary voltage AUX AV analog auxiliary voltage (3.3 V); AUX supply voltage AV analog auxiliary voltage (3.3 V); AUX_PLL supply voltage for PLL ...

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... Philips Semiconductors 15. Static characteristics Table 123: Static characteristics: analog I/O pins (SDA and SCL 3 -40 to +85 C; unless otherwise specified. DD amb Symbol Parameter V HIGH-level input voltage IH V LOW-level input voltage IL V hysteresis voltage hys V LOW-level output voltage OL Table 124: Static characteristics: digital pins V = 3.0 to 3.6 V ...

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... Philips Semiconductors Table 126: Static characteristics: USB interface block (pins DM1 to DM4 and DP1 to DP4 3 -40 to +85 C; unless otherwise specified. DD amb Symbol Parameter V disconnect detection threshold HSDSC (differential signal amplitude) V data signaling common mode HSCM voltage range Output levels for high-speed ...

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... Philips Semiconductors 16. Dynamic characteristics Table 127: Dynamic characteristics: system clock timing Symbol Parameter Crystal oscillator [1] f clock frequency clk External clock input clock duty cycle [1] Recommended accuracy of the clock frequency is 500 ppm for the crystal and oscillator. The oscillator should have 3.3 V power supply. ...

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... Philips Semiconductors Table 131: Dynamic characteristics: full-speed source electrical characteristics V = 3 -40 to +85 C; unless otherwise specified. DD amb Symbol Parameter Driver characteristics t rise time FR t fall time FF t differential rise and fall time FRFM matching Z driver output resistance for the ...

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... Philips Semiconductors 17. Timing Table 133: PCI clock and IO timing Symbol Parameter PCI clock timing; see Figure 5 T CLK cycle time cyc t CLK HIGH time high t CLK LOW time low SR CLK slew rate CLK SR RST# slew rate RST# PCI input timing; see ...

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... Philips Semiconductors CLK INPUT DELAY Fig 6. PCI input timing. CLK OUTPUT DELAY OUTPUT Fig 7. PCI output timing. T PERIOD 3.3 V crossover point differential data lines the bit duration corresponding with the USB data rate. PERIOD Full-speed timing symbols have a subscript prefix ‘F’, low-speed timings a prefix ‘L’. ...

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... Philips Semiconductors 18. Package outline LQFP128: plastic low profile quad flat package; 128 leads; body 1 pin 1 index 128 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 1.45 0.23 mm 1.6 0.25 0.05 1.35 0.13 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...

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... Philips Semiconductors 19. Soldering 19.1 Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fi ...

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... SSOP, TSSOP, VSO, VSSOP [1] For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your Philips Semiconductors sales office. [2] All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26 ...

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... Philips Semiconductors 20. Revision history Table 135: Revision history Rev Date CPCN Description 01 20030206 Product data (9397 75010015) 9397 750 10015 Product data Rev. 01 — 06 February 2003 ISP1561 USB PCI host controller © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 100 of 102 ...

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... Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. ...

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... Philips Semiconductors Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 1.1 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 4 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 6 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7 7 Functional description . . . . . . . . . . . . . . . . . . 13 7.1 OHCI Host Controller . . . . . . . . . . . . . . . . . . . 13 7.2 EHCI Host Controller . . . . . . . . . . . . . . . . . . . 13 7.3 Dynamic port-routing logic . . . . . . . . . . . . . . . 13 7.4 Hi-Speed USB analog transceivers ...

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