ISP1161BD Philips Semiconductors, ISP1161BD Datasheet

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ISP1161BD

Manufacturer Part Number
ISP1161BD
Description
5 to 3.3 V, full-speed universal serial bus single-chip host and device controller
Manufacturer
Philips Semiconductors
Datasheet

Specifications of ISP1161BD

Case
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1. General description
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The ISP1161 is a single-chip Universal Serial Bus (USB) Host Controller (HC) and
Device Controller (DC) which complies with Universal Serial Bus Specification
Rev 1.1 . These two USB controllers, the HC and the DC, share the same
microprocessor bus interface. They have the same data bus, but different I/O
locations. They also have separate interrupt request output pins, separate DMA
channels that include separate DMA request output pins and DMA acknowledge
input pins. This makes it possible for a microprocessor to control both the USB HC
and the USB DC at the same time.
ISP1161 provides two downstream ports for the USB HC and one upstream port for
the USB DC. Each downstream port has its own overcurrent (OC) detection input pin
and power supply switching control output pin. The upstream port has its own V
detection input pin. ISP1161 also provides separate wakeup input pins and
suspended status output pins for the USB HC and the USB DC, respectively. This
makes power management flexible. The downstream ports for the HC can be
connected with any USB compliant USB devices and USB hubs that have USB
upstream ports. The upstream port for the DC can be connected to any USB
compliant USB host and USB hubs that have USB downstream ports.
The DC is compliant with most device class specifications such as Imaging Class,
Mass Storage Devices, Communication Devices, Printing Devices and Human
Interface Devices.
ISP1161 is well suited for embedded systems and portable devices that require a
USB host only, a USB device only, or a combined and configurable USB host and
USB device capabilities. ISP1161 brings high flexibility to the systems that have it
built-in. For example, a system that has ISP1161 built-in allows it not only to be
connected to a PC or USB hub that has a USB downstream port, but also to be
connected to a device that has a USB upstream port such as a USB printer, USB
camera, USB keyboard, USB mouse, among others. ISP1161 enables peer-to-peer
connectivity between embedded systems. An interesting application example is to
connect a ISP1161 HC with a ISP1161 DC.
Let us see an example of ISP1161 being used in a Digital Still Camera (DSC) design.
Figure 1
used as a USB HC.
DC at the same time.
ISP1161
Full-speed Universal Serial Bus single-chip host and device
controller
Rev. 01 — 3 July 2001
shows ISP1161 being used as a USB DC.
Figure 3
shows ISP1161 being used as a USB HC and a USB
Figure 2
shows ISP1161 being
Product data
BUS

Related parts for ISP1161BD

ISP1161BD Summary of contents

Page 1

ISP1161 Full-speed Universal Serial Bus single-chip host and device controller Rev. 01 — 3 July 2001 1. General description The ISP1161 is a single-chip Universal Serial Bus (USB) Host Controller (HC) and Device Controller (DC) which complies with Universal Serial ...

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... Philips Semiconductors Fig 1. ISP1161 operating as a USB device. Fig 2. ISP1161 operating as a stand-alone USB host. 9397 750 08313 Product data Full-speed USB single-chip host and device controller PC (host) USB cable USB I/F USB I/F EMBEDDED SYSTEM P SYSTEM P MEMORY P bus I/F ISP1161 ...

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... Philips Semiconductors PC (host) USB cable USB I/F Fig 3. ISP1161 operating as both USB host and device simultaneously. 2. Features Complies with Universal Serial Bus Specification Rev 1.1 Combines HC and single chip On-chip DC complies with most Device Class specifications Both HC and DC can be accessed by an external microprocessor via separate I/O ...

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... Game console. 4. Ordering information Table 1: Ordering information Type number Package Name Description ISP1161BD LQFP64 Plastic low profile quad flat package; 64 leads; body 1.4 mm ISP1161BM LQFP64 Plastic low profile quad flat package; 64 leads; body 1.4 mm 9397 750 08313 Product data Full-speed USB single-chip host and device controller Rev. 01 — ...

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H_WAKEUP 42 H_SUSPEND 33 NDP_SEL 14, 16, 17, 63 D15 ISP1161 HOST/ 28 DEVICE DACK2 27 AUTOMUX ...

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... Philips Semiconductors POWER-ON RESET P interface DMA HANDLER Host bus I/F P HANDLER Fig 5. Host controller sub block diagram. POWER-ON RESET Device BUS I/F bus I/F Fig 6. Device controller sub block diagram. 9397 750 08313 Product data Full-speed USB single-chip host and device controller ...

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... Fig 7. Pin configuration LQFP64. 6.2 Pin description Table 2: Symbol DGND 9397 750 08313 Product data Full-speed USB single-chip host and device controller ISP1161BD ISP1161BM Pin description for LQFP64 [1] Pin Type Description 1 - digital ground 2 I/O bit 2 of bidirectional data; slew-rate controlled; TTL input; ...

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... Philips Semiconductors Table 2: Symbol D6 D7 DGND D8 D9 D10 D11 D12 D13 DGND D14 D15 DGND V hold1 n. hold2 DREQ1 9397 750 08313 Product data Full-speed USB single-chip host and device controller Pin description for LQFP64 …continued [1] Pin Type Description 6 I/O bit 6 of bidirectional data; slew-rate controlled; TTL input; ...

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... Philips Semiconductors Table 2: Symbol DREQ2 DACK1 DACK2 INT1 INT2 TEST RESET NDP_SEL EOT DGND D_SUSPEND D_WAKEUP GL D_VBUS H_WAKEUP CLKOUT H_SUSPEND XTAL1 9397 750 08313 Product data Full-speed USB single-chip host and device controller Pin description for LQFP64 …continued [1] Pin Type Description ...

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... Philips Semiconductors Table 2: Symbol XTAL2 DGND H_PSW1 H_PSW2 D_DM D_DP H_DM1 H_DP1 H_DM2 H_DP2 H_OC1 H_OC2 V CC AGND V reg(3. n.c. DGND D0 D1 [1] Symbol names with an overscore (e.g. NAME) represent active LOW signals. 9397 750 08313 Product data Full-speed USB single-chip host and device controller Pin description for LQFP64 … ...

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... Philips Semiconductors 7. Functional description 7.1 PLL clock multiplier MHz clock multiplier Phase-Locked Loop (PLL) is integrated on-chip. This allows for the use of a low-cost 6 MHz crystal, which also minimizes EMI. No external components are required for the operation of the PLL. 7.2 Bit clock recovery The bit clock recovery circuit recovers the clock from the incoming USB data stream using a 4 over-sampling principle ...

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... Philips Semiconductors 7.6 GoodLink (in DC) Indication of a good USB connection is provided at pin GL through GoodLink technology. During enumeration the LED indicator will blink on momentarily. When the ISP1161 has been successfully enumerated (the device address is set), the LED indicator will remain permanently on. Upon each successful packet transfer (with ACK) to and from the ISP1161 the LED will blink off for 100 ms. During ‘ ...

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... Philips Semiconductors microprocessors can read or write ISP1161’s internal control registers and FIFO buffer RAM through the parallel I/O (PIO) operating mode. I/O interface between a microprocessor and ISP1161. Fig 9. Parallel I/O interface between microprocessor and ISP1161. 8.2 DMA mode ISP1161 also provides DMA mode for external microprocessors to access its internal FIFO buffer RAM. Data can be transferred by DMA operation between a microprocessor’ ...

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... Philips Semiconductors Fig 10. DMA interface between microprocessor and ISP1161. 8.3 Microprocessor read/write ISP1161’s internal control registers by PIO mode 8.3.1 I/O port addressing Table 3 address should include the chip select signal CS and the address lines A1 and A0. However, the direction of the access of the I/O ports is controlled by the RD and WR signals. When RD is LOW, the microprocessor reads data from ISP1161’ ...

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... Philips Semiconductors When microprocessor accesses the HC. When microprocessor accesses the DC. Fig 11. A microprocessor accessing via an automux switch. When microprocessor accesses the data port. When microprocessor accesses the command port. Fig 12. Access to internal control registers. 8.3.2 Register access phases ISP1161’s register structure is a command-data register pair structure. A complete register access cycle comprises a command phase followed by a data phase ...

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... Philips Semiconductors For ISP1161’s ES1 (engineering sample: version one), the chip’ 6110H, where the upper byte of 61H stands for ISP1161, and the lower byte of 10H stands for the first version of the IC chip. Fig 13. 16-bit register access cycle. Most of ISP1161’s internal control registers are 16 bits wide. Some of the internal control registers, however, have 32-bit width ...

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... Philips Semiconductors Signals CS A1, A0 RD, WR data bus Fig 16. Accessing ISP1161 DC control registers. 8.4 Microprocessor read/write ISP1161’s internal FIFO buffer RAM by PIO mode Since ISP1161’s internal memory is structured as a FIFO buffer RAM, the FIFO buffer RAM is mapped to dedicated register fields. Therefore, accessing ISP1161’s internal FIFO buffer RAM is just like accessing the internal control registers in multiple data phases ...

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... Philips Semiconductors microprocessor must still issue signal to ISP1161’ pin. (DACK Only mode does not need the signal.) ISP1161 will repeat the DMA cycles until it receives an EOT signal to terminate the DMA transfer. ISP1161 supports both external EOT and internal EOT signals. The external EOT signal is received as input from ISP1161’ ...

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... Philips Semiconductors 8.6 Interrupts ISP1161 has separate interrupt request pins for the USB HC (INT1) and the USB DC (INT2). 8.6.1 Pin configuration The interrupt output signals have four configuration modes: • Level trigger, active LOW • Level trigger, active HIGH • ...

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... Philips Semiconductors HcInterruptStatus register FNO RHSC FNO IE RHSC IE HcInterruptEnable register Fig 21. HC interrupt logic. The interrupt events of the Hc PInterrupt register (24H - Read, A4H - Write) changes the status of pin INT1 when the corresponding bits of the Hc PInterruptEnable register (25H - Read, A5H - Write) and pin INT1’s global enable bit (bit 0 of the HcHardwareConfi ...

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... Philips Semiconductors Bits RESET, RESUME, EOT and SOF are cleared upon reading the Interrupt Register. The endpoint bits (EP0OUT to EP14) are cleared by reading the associated Endpoint Status Register. Bit BUSTATUS follows the USB bus status exactly, allowing the firmware to get the current bus status when reading the Interrupt Register. SETUP and OUT token interrupts are generated after ISP1161’ ...

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... Philips Semiconductors 9. The USB host controller (HC) 9.1 The HC’s four USB states ISP1161’s USB HC has four USB states USB Operational, USB Reset, USB Suspend, and USB Resume that define the HC’s USB signaling and bus states responsibilities. The signals are visible to the HC (software) Driver via ISP1161 USB HC’ ...

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... Philips Semiconductors A simplistic flow diagram showing when and how to generate USB traffic is shown in Figure Revision 1.1 about the protocol and ISP1161 USB HC’s register usage. Reset HC state = USB_Operational Initialize HC Entry Fig 24. ISP1161 HC operating flow. • Reset This includes hardware reset by pin RESET and software reset by the HcSoftwareReset command (A9H). The reset function will clear all the HC’ ...

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... Philips Semiconductors • Prepare PTD Data in P System RAM The communication channel between the HC Driver and ISP1161’s USB the form of Philips Transfer Descriptor (PTD) data. The PTD data provides USB traffic information about the commands, status, and USB data packets. ...

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... Philips Semiconductors The PTD data structure is used by the HC to define a buffer of data that will be moved to or from an endpoint in the USB device. This data buffer is set up for the current frame (1 ms frame) by the firmware, the HC Driver. The payload data for every transfer in the frame must have a PTD as a header to describe the characteristic of the transfer. PTD data is DWORD aligned. 9.3.1 PTD data header defi ...

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... Philips Semiconductors Table 5: Philips Transfer Descriptor (PTD): bit description Symbol Access ActualBytes[9:0] R/W Contains the number of bytes that were transferred for this PTD CompletionCode[3:0] R/W 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 Active R/W Set to logic 1 by fi ...

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... Philips Semiconductors Table 5: Philips Transfer Descriptor (PTD): bit description Symbol Access TotalBytes[9:0] R Specifies the total number of bytes to be transferred with this data structure. For Bulk and Control only, this can be greater than MaximumPacketSize. DirectionPID[1: Format R The format of this data structure. If this is a Control, Bulk or Interrupt endpoint, then Format = 0 ...

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... Philips Semiconductors • ATL buffer length = 400H, ITL buffer length = 200H. This is insufficient use of the internal FIFO buffer RAM. • ATL buffer length = 1000H, ITL buffer length = 0H. This will use the internal FIFO buffer RAM for only ATL transfers. • ...

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... Philips Semiconductors The data transfer can be done via PIO mode or DMA mode. The data transfer rate can Mbyte/s. In DMA operation, single-cycle or multi-cycle burst modes are supported. For the multi-cycle burst mode cycles per burst is supported for ISP1161. 9.4.2 Data organization PTD data is used for every data transfer between a microprocessor and the USB bus, and the PTD data resides in the buffer RAM ...

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... Philips Semiconductors Fig 28. PTD data with DWORD alignment in buffer RAM. 9.4.3 Operation & C Program Example Figure 29 mode. ISP1161 provides one register as the access port for each buffer RAM. For the ITL buffer RAM, the access port is the ITLBufferPort register (40H - Read, C0H - Write) ...

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... Philips Semiconductors Following is an example program that shows how to write data into the ATL buffer RAM. The total number of data bytes to be transferred is 80 (decimal) which will be set into the HcTransferCounter register as 50H. The data consists of four types of PTD data: 1. The first PTD header (IN bytes, followed by 16 bytes of space reserved for its payload data ...

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... Philips Semiconductors unsigned int i; unsigned int wCount,wData; // Prepare PTD data to be written into HC ATL buffer RAM: unsigned int PTDData[0x28]= { 0x0800,0x1010,0x0810,0x0005, //PTD header for IN token #1 //Reserved space for payload data of IN token #1 0x0000,0x0000,0x0000,0x0000, 0x0000,0x0000,0x0000,0x0000, 0x0800,0x1008,0x0808,0x0005, //PTD header for IN token #2 //Reserved space for payload data of IN token #2 ...

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... Philips Semiconductors return(wValue Write HC 16-bit registers // void HcRegWrite(unsigned int wIndex,unsigned int wValue) { outport(HcCmdPort,wIndex | 0x80); outport(HcDataPort,wValue Host bus I 000H 001H 3FFH ITL0 buffer RAM (8-bit width) Fig 29. PIO access to Internal FIFO buffer RAM. 9.5 HC’s operational model Upon power up, the HC Driver sets up all operational registers (32-bit). The FSLargestDataPacket fi ...

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... Philips Semiconductors One interrupt is issued concurrently with the SOF. This interrupt (the ITLint is set in the Hc PInterrupt register) triggers reading and writing of the ITL by the microprocessor, after which the interrupt is cleared by the microprocessor. Next the programmable AT Interrupt (the ATLint is set in the Hc PInterrupt Register) is issued, which triggers reading and writing of the ITL by the microprocessor, after which the interrupt is cleared by the microprocessor ...

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... Philips Semiconductors • The ISO packet for frame will be written; • The AT packet for frame will be written. traffic SOF on USB (frame N) ISO interrupt read ISO_A(N 1) write ISO_A(N 1) Fig 30. HC time domain behavior: example 1. In the next example, the microprocessor is still busy transferring the AT data when the ISO interrupt of the next frame ( raised result, there will traffi ...

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... Philips Semiconductors (frame N) Fig 32. HC time domain behavior: example 3. Control Transaction Limitations The different phases of a Control transfer (SETUP, Data and Status) should never be put in the same ATL. 9.6 Microprocessor loading The maximum amount of data that can be transferred for an endpoint during one frame is 1023 bytes. The number of USB packets that are needed for this batch of data depends on the Maximum Packet Size that is specifi ...

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... Philips Semiconductors Using either internal or external 15 k resistors. Fig 33. Use pull-down resistors on downstream ports. 9.8 Overcurrent detection and power switching control A downstream port provides +5 V power supply to the V hardware functions to monitor the downstream ports loading conditions and control their power switching. These hardware functions are implemented by the internal power switching control circuit and overcurrent detection circuit ...

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... Philips Semiconductors 9.8.1 Using internal OC detection circuit The internal OC detection circuit can be used only when power supply. The HC Driver must set AnalogOCEnable, bit 10 of the HcHardwareConfiguration register, to logic 1. An application using the internal OC detection circuit and internal 15 k pull-down resistors is shown in while H_DPn denotes either pin H_DP1 or H_DP2 ...

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... Philips Semiconductors BUS V BUS USB downstream port connector 22 22 Fig 35. Using internal OC detection circuit. 9.8.2 Using external OC detection circuit When V power supply, then the internal OC detection circuit cannot be used. An external OC detection circuit must be used instead. Nevertheless, regardless of V connections, an external OC detection circuit can be used from time to time. To use an external OC detection circuit, AnalogOCEnable, bit 10 of the HcHardwareConfi ...

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... Philips Semiconductors V BUS external OC detect USB downstream port connector 22 22 Fig 36. Using external OC detection circuit. 10. Suspend and wakeup (in HC) 10.1 HC suspended state The HC can be put into suspended state by setting the HcControl register (01H - Read, 81H - Write). See XOSC_6MHz XOSC (to DC PLL) ...

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... Philips Semiconductors With the device in a suspended state it will consume considerably less power by turning off the internal 48 MHz clock, PLL and crystal, and setting the internal regulator to power-down mode. The ISP1161 suspend and resume clock scheme is shown in Remark: ISP1161 can be put into a fully suspended mode only after both the HC and the DC go into the suspended mode, when the crystal can be turned off and the internal regulator can be put into power-down mode ...

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... Philips Semiconductors No matter which method is used to wake up the HC from SUSPEND state, you must enable the corresponding interrupt bits before the HC goes into SUSPEND state so that the microprocessor can receive the correct interrupt request to wake up the HC. 11. The USB device controller (DC) The Device Controller (DC) in ISP1161 originates from Philips ISP1181 USB Full-Speed Interface Device IC ...

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... Philips Semiconductors 11.1.2 OUT data transfer • The arrival of the OUT token is detected by the SIE by decoding the PID. • The SIE also checks for the device number and endpoint number and verifies whether they are ok. • If the endpoint is enabled, the SIE checks the contents of the Endpoint Status register ...

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... Philips Semiconductors When the DMA controller terminates the DMA transfer by asserting EOT and Auto-reload mode is off, the buffer is also cleared (even if not all data are read) and the DMA handler is disabled automatically. For the next DMA transfer, the DMA controller as well as the DMA handler must be re-enabled. However in Auto-reload mode, the DMA handler will automatically restart by reasserting the DREQ2 line, without any loss of data ...

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... Philips Semiconductors [1] IN: input for the USB host (ISP1161 transmits); OUT: output from the USB host (ISP1161 receives). [2] The data flow direction is determined by bit EPDIR in the Endpoint Configuration Register. [3] The total amount of FIFO storage allocated to enabled endpoints must not exceed 2462 bytes. ...

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... Philips Semiconductors Table 8: FFOSZ[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Each programmable FIFO can be configured independently via its ECR, but the total physical size of all enabled endpoints (IN plus OUT) must not exceed 2462 bytes (512 bytes for non-isochronous FIFOs) ...

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... Philips Semiconductors 11.3.4 Endpoint initialization In response to the standard USB request Set Interface, the firmware must program all 16 ECRs of the ISP1161 in sequence (see enabled or not. The hardware will then automatically allocate FIFO storage space. If all endpoints have been configured successfully, the firmware must return an empty packet to the control IN endpoint to acknowledge success to the host. If there are errors in the endpoint confi ...

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... Philips Semiconductors 12. DMA transfer for the Device Controller Direct Memory Access (DMA method to transfer data from one location to another in a computer system, without intervention of the Central Processor Unit (CPU). Many different implementations of DMA exist. The ISP1161 DC supports two methods: • 8237 compatible mode: based on the DMA subsystem of the IBM personal computers (PC, AT and all its successors and clones) ...

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... Philips Semiconductors Table 10: Endpoint selection for DMA transfer Endpoint identifier 12.2 8237 compatible mode The 8237 compatible DMA mode is selected by clearing bit DAKOLY in the Hardware Configuration Register (see Table Table 11: 8237 compatible mode: pin functions Symbol DREQ2 DACK2 EOT ...

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... Philips Semiconductors The following example shows the steps which occur in a typical DMA transfer: 1. ISP1161 DC receives a data packet in one of its endpoint FIFOs; the packet must be transferred to memory address 1234H. 2. ISP1161 DC asserts the DREQ2 signal requesting the 8237 for a DMA transfer. 3. The 8237 asks the CPU to release the bus by asserting the HRQ signal. ...

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... Philips Semiconductors Table 12: DACK-only mode: pin functions Symbol EOT DACK-only mode the ISP1161 DC uses the DACK2 signal as a data strobe. Input signals RD and WR are ignored. This mode is used in CPU systems that have a single address space for memory and I/O access. Such systems have no separate MEMW and MEMR signals: the RD and WR signals are also used as memory data strobes ...

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... Philips Semiconductors DMA is enabled (DMAEN = 1), the internal DMA counter is loaded with the value from the DMA Counter Register. When the internal counter reaches zero an EOT condition is generated and the DMA operation stops. Short/empty packet: endpoint before any DMA transfer takes place. When a short/empty packet has been enabled as EOT indicator (SHORTP = 1), the transfer size is determined by the presence of a short/empty packet in the data ...

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... Philips Semiconductors 13. HC registers The HC contains a set of on-chip control registers. These registers can be read or written by the Host Controller Driver (HCD). The Control and Status register sets, Frame Counter register sets, and Root Hub register sets are grouped under the category of HC Operational Registers (32 bits). These operational registers are made compatible to OpenHCI (Host Controller Interface) Operational Registers ...

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... Philips Semiconductors Table 15: HC Control Register summary Command (Hex) Read 13.1 HC control and status registers 13.1.1 HcRevision Register Table 16: HcRevision Register: bit allocation Bit 31 30 Symbol Reset Access R R Bit 23 22 Symbol Reset Access R R Bit 15 14 Symbol Reset Access ...

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... Philips Semiconductors Code (Hex): 00 — read only 13.1.2 HcControl Register The HcControl register defines the operating modes for the HC. Most fields are modified only by the HCD, except for HostControllerFunctionalState (HCFS) and RemoteWakeupConnected (RWC). Table 18: HcControl Register: bit allocation Bit 31 30 ...

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... Philips Semiconductors Table 19: HcControl Register: bit description Bit Code (Hex): 01 — read Code (Hex): 81 — write 13.1.3 HcCommandStatus Register The HcCommandStatus register is used by the HC to receive commands issued by the HCD, and it also reflects the HC’s current status. To the HCD, it appears ‘write to set’ register. The HC must ensure that bits written as logic 1 become set in the register while bits written as logic 0 remain unchanged in the register ...

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... Philips Semiconductors The SchedulingOverrunCount field indicates the number of frames with which the HC has detected the scheduling overrun error. This occurs when the Periodic list does not complete before EOF. When a scheduling overrun error is detected, the HC increments the counter and sets the SchedulingOverrun field in the HcInterruptStatus register ...

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... Philips Semiconductors 13.1.4 HcInterruptStatus Register This register provides the status of the events that cause hardware interrupts. When an event occurs, the HC sets the corresponding bit in this register. When a bit becomes set, a hardware interrupt is generated if the interrupt is enabled in the HcInterruptEnable register (see set. The HCD may clear specific bits in this register by writing logic1 to the bit positions to be cleared ...

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... Philips Semiconductors Table 23: HcInterruptStatus Register: bit description Bit Code (Hex): 03 — read Code (Hex): 83 — write 13.1.5 HcInterruptEnable Register Each enable bit in the HcInterruptEnable register corresponds to an associated interrupt bit in the HcInterruptStatus register. The HcInterruptEnable register is used to control which events generate a hardware interrupt. When these three conditions occur: • ...

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... Philips Semiconductors Table 24: HcInterruptEnable Register: bit allocation Bit 31 30 Symbol MIE Reset 0 0 Access Bit 23 22 Symbol Reset Access Bit 15 14 Symbol Reset Access Bit 7 6 Symbol reserved RHSC Reset 0 0 Access Table 25: HcInterruptEnable Register: bit description Bit Code (Hex): 04 — read Code (Hex): 84 — ...

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... Philips Semiconductors 13.1.6 HcInterruptDisable Register Each disable bit in the HcInterruptDisable register corresponds to an associated interrupt bit in the HcInterruptStatus register. The HcInterruptDisable register is coupled with the HcInterruptEnable register. Thus, writing a logic bit in this register clears the corresponding bit in the HcInterruptEnable register, whereas writing a logic bit in this register leaves the corresponding bit in the HcInterruptEnable register unchanged ...

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... Philips Semiconductors Table 27: HcInterruptDisable Register: bit description Bit Code (Hex): 05 — read Code (Hex): 85 — write 13.2 HC frame counter registers 13.2.1 HcFmInterval Register The HcFmInterval register contains a 14-bit value which indicates the bit time interval in a frame (that is, between two consecutive SOFs), and a 15-bit value indicating the full-speed maximum packet size that the HC may transmit or receive without causing a scheduling overrun ...

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... Philips Semiconductors Table 29: HcFmInterval Register: bit description Bit Code (Hex): 0D — read Code (Hex): 8D — write 13.2.2 HcFmRemaining Register The HcFmRemaining register is a 14-bit down counter showing the bit time remaining in the current frame. Table 30: HcFmRemaining Register: bit allocation Bit 31 30 ...

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... Philips Semiconductors Table 31: HcFmRemaining Register: bit description Bit Code (Hex): 0E — read 13.2.3 HcFmNumber Register The HcFmNumber register is a 16-bit counter. It provides a timing reference for events happening in the HC and the HCD. The HCD may use the 16-bit value specified in this register and generate a 32-bit frame number without requiring frequent access to the register ...

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... Philips Semiconductors Table 33: HcFmNumber Register: bit description Bit Code (Hex): 0F — read 13.2.4 HcLSThreshold Register The HcLSThreshold register contains an 11-bit value used by the HC to determine whether to commit to the transfer of a maximum of 8-byte LS packet before EOF. Neither the HC nor the HCD is allowed to change this value. ...

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... Philips Semiconductors Code (Hex): 11 — read Code (Hex): 91 — write 13.3 HC Root Hub registers All registers included in this partition are dedicated to the USB Root Hub, which is an integral part of the HC although functionally separate entity. The Host Controller Driver (HCD) emulates USBD accesses to the Root Hub via a register interface. The HCD maintains many USB-defi ...

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... Philips Semiconductors Table 36: HcRhDescriptorA Register: bit description Bit 31 30 Symbol Reset Access Bit 23 22 Symbol Reset Access Bit 15 14 Symbol reserved Reset 0 0 Access R/W Bit 7 6 Symbol Reset Access 9397 750 08313 Product data Full-speed USB single-chip host and device controller ...

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... Philips Semiconductors Table 37: HcRhDescriptorA Register: bit description Bit Code (Hex): 12 — read Code (Hex): 92 — write 9397 750 08313 Product data Full-speed USB single-chip host and device controller Symbol Description POTPGT PowerOnToPowerGoodTime: This byte specifies the duration [7:0] HCD has to wait before accessing a powered-on port of the Root Hub implementation-specifi ...

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... Philips Semiconductors 13.3.2 HcRhDescriptorB Register The HcRhDescriptorB register is the second register of two describing the characteristics of the Root Hub. These fields are written during initialization to correspond with the system implementation. Reset values are implementation-specific (IS). Table 38: HcRhDescriptorB Register: bit allocation Bit 31 30 ...

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... Philips Semiconductors Code (Hex): 13 — read Code (Hex): 93 — write 13.3.3 HcRhStatus Register The HcRhStatus register is divided into two parts. The lower word of a Dword represents the Hub Status field and the upper word represents the Hub Status Change field. Reserved bits should always be written as logic 0. ...

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... Philips Semiconductors Table 41: HcRhStatus Register: bit description Bit Code (Hex): 14 — read Code (Hex): 94 — write 9397 750 08313 Product data Full-speed USB single-chip host and device controller Symbol Description CRWE On write—ClearRemoteWakeupEnable: Writing a logic 1 clears DeviceRemoveWakeupEnable. Writing a logic 0 has no effect. ...

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... Philips Semiconductors 13.3.4 HcRhPortStatus[1:2] The HcRhPortStatus[1:2] register is used to control and report port events on a per-port basis. NumberDownstreamPorts represents the number of HcRhPortStatus registers that are implemented in hardware. The lower word is used to reflect the port status, whereas the upper word reflects the status change bits. Some status bits are implemented with special write behavior ...

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... Philips Semiconductors Table 43: HcRhPortStatus[1:2] Register: bit description Bit 9397 750 08313 Product data Full-speed USB single-chip host and device controller Symbol Description - reserved PRSC PortResetStatusChange: This bit is set at the end of the 10 ms port reset signal. The HCD writes a logic 1 to clear this bit. Writing a logic 0 has no effect. 0 — ...

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... Philips Semiconductors Table 43: HcRhPortStatus[1:2] Register: bit description Bit 9397 750 08313 Product data Full-speed USB single-chip host and device controller Symbol Description PPS (read) PortPowerStatus: This bit reflects the port power status, regardless of the type of power switching implemented. This bit is cleared if an overcurrent condition is detected. ...

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... Philips Semiconductors Table 43: HcRhPortStatus[1:2] Register: bit description Bit Code (Hex): [1] = 15, [ — read Code (Hex): [1] = 95, [ — write 9397 750 08313 Product data Full-speed USB single-chip host and device controller Symbol Description PSS (read) PortSuspendStatus: This bit indicates whether the port is suspended or in the resume sequence ...

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... Philips Semiconductors 13.4 HC DMA and interrupt control registers 13.4.1 HcHardwareConfiguration Register Table 44: HcHardwareConfiguration Register: bit allocation Bit 15 14 Symbol reserved Reset 0 0 Access R/W Bit 7 6 Symbol EOTInput DACKInput Polarity Polarity Reset 0 0 Access R/W R/W Table 45: HcHardwareConfiguration Register: bit description ...

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... Philips Semiconductors Code (Hex): 20 — read Code (Hex): A0 — write Remark: 1. Bit 0, InterruptPinEnable, is used as pin INT1’s master interrupt enable. This bit should be used together with the register Hc PInterruptEnable to enable pin INT1. 2. Bits 4:3 are fixed at the value 01B for ISP1161. ...

Page 78

... Philips Semiconductors 13.4.3 HcTransferCounter Register This register holds the number of bytes of a PIO or DMA transfer. For a PIO transfer, the number of bytes being read or written to the (Isochronous Transfer List) ITL or (Acknowledged Transfer List) ATL buffer RAM must be written into this register. For a DMA transfer, the number of bytes must be written into this register as well ...

Page 79

... Philips Semiconductors Table 50: Hc PInterrupt Register: bit allocation Bit 15 14 Symbol Reset Access Bit 7 6 Symbol reserved ClkReady Reset 0 0 Access Table 51: Hc PInterrupt Register: bit description Bit Code (Hex): 24 — read Code (Hex): A4 — write 9397 750 08313 Product data ...

Page 80

... Philips Semiconductors 13.4.5 HcuPInterruptEnable Register The bits 6:0 in this register are the same as those in the Hc PInterrupt register. They are used together with bit 0 of the HcHardwareConfiguration register to enable or disable the bits in the Hc PInterrupt register. On power-on, all bits in this register are masked with 0. This means no interrupt request output on the interrupt pin INT1 can be generated ...

Page 81

... Philips Semiconductors Code (Hex): 25 — read Code (Hex): A5 — write 13.5 HC miscellaneous registers 13.5.1 HcChipID Register Read this register to get the ID of the ISP1161 silicon chip. The high byte stands for the product name (here 61H stands for ISP1161). The low byte indicates the revision number of the product including engineering samples (here 10H means revision 1, that is ES1 of ISP1161) ...

Page 82

... Philips Semiconductors Code (Hex): A8 — write 13.5.3 HcSoftwareReset Register This is a soft reset command. The microprocessor writes A9H to ISP1161’s command port, resetting all the HC’s internal registers except for the internal FIFO buffer RAM. Table 58: HcSoftwareReset Register: bit allocation Bit ...

Page 83

... Philips Semiconductors Table 61: HcITLBufferLength Register: bit description Bit Code (Hex): 2A — read Code (Hex): AA — write 13.6.2 HcATLBufferLength Register Write to this register to assign ATL buffer size. Table 62: HcATLBufferLength Register: bit allocation Bit 15 14 Symbol Reset 0 0 Access Bit 7 6 Symbol Reset ...

Page 84

... Philips Semiconductors Table 65: HcBufferStatus Register: bit description Bit Code (Hex): 2C — read 13.6.4 HcReadBackITL0Length Register This register’s value stands for the current number of data bytes inside an ITL0 buffer to be read back by the microprocessor. The HCD must set the HcTransferCounter equivalent to this value before reading back the ITL0 buffer RAM. ...

Page 85

... Philips Semiconductors Table 68: HcReadBackITL1Length Register: bit allocation Bit 15 14 Symbol Reset 0 0 Access Bit 7 6 Symbol Reset 0 0 Access Table 69: HcReadBackITL1Length Register: bit description Bit Code (Hex): 2E — read 13.6.6 HcITLBufferPort Register This is the ITL buffer RAM read/write port. The bits 15:8 contain the data byte that comes from the ITL buffer RAM’ ...

Page 86

... Philips Semiconductors The HCD must take care of the difference that the internal buffer RAM is organized in bytes. The HCD must write the byte count into the HcTransferCounter register, but the HCD reads or writes the buffer RAM by 16 bits (by 1 word). 13.6.7 HcATLBufferPort Register This is the ATL buffer RAM read/write port. The bits 15:8 contain the data byte that comes from the Acknowledged Transfer List (ATL) buffer RAM’ ...

Page 87

... Philips Semiconductors 1. Command phase: when address bit the DC interprets the data on the lower byte of the bus (bits command code. Commands without a data phase are executed immediately. 2. Data phase (optional): when address bit the DC transfers the data on the bus to or from a register or endpoint FIFO. Multi-byte registers are accessed least signifi ...

Page 88

... Philips Semiconductors Table 74: Command and register summary Name Read Endpoint n Buffer ( 14) Stall Control OUT Endpoint Stall Control IN Endpoint Stall Endpoint 14) Read Control OUT Status Read Control IN Status Read Endpoint n Status ( 14) Validate Control OUT Buffer Validate Control IN Buffer Validate Endpoint n Buffer ( 14) ...

Page 89

... Philips Semiconductors Table 74: Command and register summary Name Read Chip ID Read Interrupt Register [1] With N representing the number of bytes, the number of words for 16-bit bus width is DIV 2. [2] Validating an OUT endpoint buffer causes unpredictable behavior of ISP1161’s DC. [3] Clearing an IN endpoint buffer causes unpredictable behavior of ISP1161’s DC. ...

Page 90

... Philips Semiconductors Table 76: Endpoint Configuration Register: bit description Bit 14.1.2 Write/Read Device Address This command is used to set the USB assigned address in the Address Register and enable the USB device. The Address Register bit allocation is shown in A USB bus reset sets the device address to 00H (internally) and enables the device. ...

Page 91

... Philips Semiconductors Table 79: Mode Register: bit allocation Bit 7 6 Symbol DMAWD reserved [1] Reset 0 0 Access R/W R/W [1] Unchanged by a bus reset. Table 80: Mode Register: bit description Bit 14.1.4 Write/Read Hardware Configuration This command is used to access the Hardware Configuration Register, which consists of 2 bytes. The fi ...

Page 92

... Philips Semiconductors Bit 7 6 Symbol DAKOLY DRQPOL Reset 0 1 Access R/W R/W Table 82: Hardware Configuration Register: bit description Bit 9397 750 08313 Product data Full-speed USB single-chip host and device controller DAKPOL EOTPOL WKUPCS R/W R/W R/W Symbol Description - reserved EXTPUL A logic 1 indicates that an external 1 ...

Page 93

... Philips Semiconductors 14.1.5 Write/Read Interrupt Enable Register This command is used to individually enable/disable interrupts from all endpoints, as well as interrupts caused by events on the USB bus (SOF, SOF lost, EOT, suspend, resume, reset). A bus reset will not change any of the programmed bit values. The command accesses the Interrupt Enable Register, which consists of 4 bytes. The bit allocation is given in Code (Hex): C2/C3 — ...

Page 94

... Philips Semiconductors 14.1.6 Write/Read DMA Configuration This command defines the DMA configuration of ISP1161’s DC and enables/disables DMA transfers. The command accesses the DMA Configuration Register, which consists of 2 bytes. The bit allocation is given in DMAEN (DMA disabled), all other bits remain unchanged. ...

Page 95

... Philips Semiconductors 14.1.7 Write/Read DMA Counter This command accesses the DMA Counter Register. The bit allocation is given in Table the register returns the number of remaining bytes in the current transfer. A bus reset will not change the programmed bit values. The internal DMA counter is automatically reloaded from the DMA Counter Register when DMA is re-enabled (DMAEN = 1). See Code (Hex): F2/F3 — ...

Page 96

... Philips Semiconductors 14.2.1 Write/Read Endpoint Buffer This command is used to access endpoint FIFO buffers for reading or writing. First, the buffer pointer is reset to the beginning of the buffer. Following the command, a maximum words can be written or read, with M given by (N representing the size of the endpoint buffer. After each read/write action the buffer pointer is automatically incremented DMA access the fi ...

Page 97

... Philips Semiconductors meaningful after a successful transaction. Exception: during DMA access of a double-buffered endpoint, the buffer pointer automatically points to the secondary buffer after reaching the end of the primary buffer. 14.2.2 Read Endpoint Status This command is used to read the status of an endpoint FIFO. The command ...

Page 98

... Philips Semiconductors 14.2.3 Stall Endpoint/Unstall Endpoint These commands are used to stall or unstall an endpoint. The commands modify the content of the Endpoint Status Register (see A stalled control endpoint is automatically unstalled when it receives a SETUP token, regardless of the packet content. If the endpoint should stay in its stalled state, the microprocessor can re-stall it with the Stall Endpoint command ...

Page 99

... Philips Semiconductors Table 93: Endpoint Status Image Register: bit allocation Bit 7 6 Symbol EPSTAL EPFULL1 Reset 0 0 Access R R Table 94: Endpoint Status Image Register: bit description Bit 14.2.7 Acknowledge Setup This command acknowledges to the host that a SETUP packet was received. The arrival of a SETUP packet disables the Validate Buffer and Clear Buffer commands for the control IN and OUT endpoints ...

Page 100

... Philips Semiconductors Transaction — read 1 word Table 95: Error Code Register: bit allocation Bit 7 6 Symbol UNREAD DATA01 Reset 0 0 Access R R Table 96: Error Code Register: bit description Bit Table 97: Transaction error codes Error code (Binary) 0000 0001 0010 0011 0100 0101 ...

Page 101

... Philips Semiconductors After waking up from ‘suspend’ state, the firmware must unlock the registers and FIFOs via this command, by writing the unlock code (AA37H) into the Lock Register. The bit allocation of the Lock Register is given in Code (Hex): B0 — unlock the device Transaction — ...

Page 102

... Philips Semiconductors 14.3.4 Read Frame Number This command returns the frame number of the last successfully received SOF followed by reading one word from the Frame Number Register, containing the frame number. The Frame Number Register is shown in Remark: After a bus reset, the value of the frame Number Register is undefined. ...

Page 103

... Philips Semiconductors Table 105:Chip ID Register: bit description Bit 14.3.6 Read Interrupt Register This command indicates the sources of interrupts as stored in the 4-byte Interrupt Register. Each individual endpoint has its own interrupt bit. The bit allocation of the Interrupt Register is shown in bus status in the interrupt service routine. Interrupts are enabled via the Interrupt Enable Register, see While reading the interrupt register, please read both 2 bytes completely ...

Page 104

... Philips Semiconductors Table 107: Interrupt Register: bit description Bit 15. Reset Pin RESET is the hardware reset input of ISP1161 active LOW. To reset all internal logic, the minimum timing requirement is 200 ns. Fig 40. RESET pin usage. 16. Power supply ISP1161 can operate at either + +3.3 V. When using + ISP1161’s power supply input: Only V connected to the +5 V power supply ...

Page 105

... Philips Semiconductors ISP1161 1 USB upstream V reg(3.3) D_DP port connector V hold1 V hold2 Fig 41. Using supply. 17. External clock input The ISP1161 has a crystal oscillator designed for a 6 MHz parallel-resonant crystal (fundamental). A typical circuit is shown in signal of 6 MHz can be applied to in put XTAL1, while leaving output XTAL2 open. ...

Page 106

... Philips Semiconductors 18. Limiting values Table 108:Absolute maximum ratings In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage to V CC(5V supply voltage to V CC(3.3V) reg(3.3) V input voltage I I latchup current latchup V electrostatic discharge voltage esd T storage temperature stg [1] Equivalent to discharging a 100 pF capacitor via a 1 ...

Page 107

... Philips Semiconductors 19. Static characteristics Table 110:Static characteristics; supply pins V = 3 4 GND Symbol Parameter internal regulator output reg(3.3) I operating supply current suspend supply current CC(susp I ) operating supply current for suspended CC( operating supply current for suspended CC( +3 operating supply current ...

Page 108

... Philips Semiconductors Table 112:Static characteristics: analog I/O pins ( 3 4 GND Symbol Parameter Input levels V differential input sensitivity DI V differential common mode CM voltage V LOW-level input voltage IL V HIGH-level input voltage IH Output levels V LOW-level output voltage OL V HIGH-level output voltage ...

Page 109

... Philips Semiconductors 20. Dynamic characteristics Table 113:Dynamic characteristics V = 3 4 GND Symbol Parameter Reset t pulse width on input RESET W(RESET) Crystal oscillator f crystal frequency XTAL [1] Dependent on the crystal oscillator start-up time. Table 114:Dynamic characteristics: analog I/O pins ( 3 4 GND otherwise specifi ...

Page 110

... Philips Semiconductors 20.1 Timing symbols Table 115:Legend for timing characteristics Symbol Time symbols t T Signal names Logic levels 9397 750 08313 Product data Full-speed USB single-chip host and device controller Description time cycle time (periodic signal) address; DMA acknowledge (DACK) clock; ...

Page 111

... Philips Semiconductors 20.2 Parallel I/O timing Table 116:Dynamic characteristics: parallel interface timing Symbol Parameter Read timing t first RD/WR after CMD SHSL t CS LOW to RD LOW SLRL t RD HIGH to CS HIGH RHSH t RD LOW pulse width HIGH to next RD LOW RHRL t RD cycle ...

Page 112

... Philips Semiconductors 20.3 DMA interface timing 20.3.1 HC single-cycle burst mode DMA timing Table 117:Dynamic characteristics: HC single-cycle burst mode DMA timing Symbol Parameter Read/write timing t RD pulse width RL t read process data setup time RLDV t read process data hold time RHDZ t write process data setup time ...

Page 113

... Philips Semiconductors 20.3.2 HC multi-cycle burst mode DMA timing Table 118:Dynamic characteristics: HC multi-cycle burst mode DMA timing Symbol Parameter Read/write timing (for 4-cycle and 8-cycle burst mode) t WR/RD LOW pulse width RL t WR/RD HIGH to next WR/RD RHRL LOW t WR/RD cycle RC t RD/WR LOW to DREQ1 LOW ...

Page 114

... Philips Semiconductors 20.3.3 External EOT timing for HC single-cycle burst mode DMA Fig 48. External EOT timing for HC single-cycle burst mode DMA. 20.3.4 External EOT timing for HC multi-cycle burst mode DMA Fig 49. External EOT timing for HC multi-cycle burst mode DMA. 20.3.5 DC single-cycle DMA timing (8237 mode) ...

Page 115

... Philips Semiconductors 20.3.6 DC single-cycle DMA timing (DACK-only mode) Table 120:Dynamic characteristics: DC single-cycle DMA timing (DACK-only mode) Symbol Parameter t DACK2 ON to DREQ2 OFF ALRL t DACK2 OFF to DREQ2 ON AHRH t DACK2 ON to data valid ALDV t DACK2 OFF to data invalid AHDZ DREQ2 DACK2 D [ 15:0 ] Fig 51. DC single-cycle DMA timing (DACK-only mode). ...

Page 116

... Philips Semiconductors 20.3.8 DC multi-cycle burst mode DMA timing Table 122:Dynamic characteristics: DC multi-cycle burst mode DMA timing Symbol Parameter t DREQ2 ON to first RD/WR OFF RHSH t last RD/ DREQ2 OFF SLRL t last RD/WR OFF to DACK2 OFF SHAH t DMA burst repeat interval RHRL DREQ2 DACK2 Fig 53 ...

Page 117

... Philips Semiconductors 21. Application information 21.1 Typical interface circuit 5 V 3.3 V SH7709 D [ 15 CS5 RD RD/WR DREQ0 DACK0 DREQ1 DACK1 5 V CLKOUT EXTAL IRQ2 IRQ3 PTC0 XTAL PTC1 PTC2 PTC3 EXTAL2 RSTOUT 32 kHz XTAL2 GND 7 For MOSFET 150 m . DSon Fig 55. Typical interface circuit to Hitachi SH-3 (SH7709) RISC processor. ...

Page 118

... Philips Semiconductors 21.2 Interfacing a ISP1161 with a SH7709 RISC processor This section shows a typical interface circuit between ISP1161 and a RISC processor. The Hitachi SH-3 series RISC processor SH7709 is used as the example. The main ISP1161 signals to be taken into consideration for connecting to a SH7709 RISC processor are: • ...

Page 119

... Philips Semiconductors the device stack. The device stack provides API directly to the application task for device function; the host stack provides API for Class driver and device driver, both of which provide API for application tasks for host function. MECHANISM CONTROL TASK ...

Page 120

... Philips Semiconductors Load capacitance: Speed: Fig 57. Load impedance for D_DP and D_DM pins. 9397 750 08313 Product data Full-speed USB single-chip host and device controller 22 D.U. (full-speed mode). L full-speed mode only: internal 1.5 k pull-up resistor on D_DP. Rev. 01 — 3 July 2001 ISP1161 ...

Page 121

... Philips Semiconductors 23. Package outline LQFP64: plastic low profile quad flat package; 64 leads; body 1 pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT max. 0.20 1.45 0.27 1.60 mm 0.25 0.05 1.35 0.17 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...

Page 122

... Philips Semiconductors LQFP64: plastic low profile quad flat package; 64 leads; body 1 pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 1.45 0.23 1.6 mm 0.25 0.05 1.35 0.13 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION ...

Page 123

... Philips Semiconductors 24. Soldering 24.1 Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fi ...

Page 124

... Philips Semiconductors During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications ...

Page 125

... This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. ...

Page 126

... Korea: Tel. + 1412, Fax. + 1415 Malaysia: Tel. + 5214, Fax. + 4880 Mexico: Tel. +9-5 800 234 7381 Middle East: see Italy For all other countries apply to: Philips Semiconductors, Marketing Communications, Building BE, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 272 4825 ...

Page 127

... Philips Semiconductors Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 4 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 7 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 7 7 Functional description . . . . . . . . . . . . . . . . . . 11 7.1 PLL clock multiplier 7.2 Bit clock recovery . . . . . . . . . . . . . . . . . . . . . . 11 7.3 Analog transceivers . . . . . . . . . . . . . . . . . . . . 11 7.4 Philips Serial Interface Engine (SIE ...

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