SAA7356HL Philips Semiconductors, SAA7356HL Datasheet

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SAA7356HL

Manufacturer Part Number
SAA7356HL
Description
1394 SBP-2 link layer controller
Manufacturer
Philips Semiconductors
Datasheet

Specifications of SAA7356HL

Case
QFP
Preliminary specification
File under Integrated Circuits, IC01
DATA SHEET
SAA7356HL
1394 SBP-2 link layer controller
INTEGRATED CIRCUITS
2000 Nov 17

Related parts for SAA7356HL

SAA7356HL Summary of contents

Page 1

... DATA SHEET SAA7356HL 1394 SBP-2 link layer controller Preliminary specification File under Integrated Circuits, IC01 INTEGRATED CIRCUITS 2000 Nov 17 ...

Page 2

... Microcontroller interface 7.4.1 Intel 8031 interface support 7.4.2 Hitachi H8 interface 7.4.3 NEC V851 interface support 7.5 Interrupt handling 7.6 Address map for the SAA7356HL 8 MICROCONTROLLER COMMUNICATION WITH THE SAA7356HL 8.1 Communications initiated by the microcontroller 8.2 Communications initiated by the SAA7356HL 8.3 Interrupt registers 2000 Nov 17 8 ...

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... GENERAL DESCRIPTION The SAA7356HL is an IEEE1394-1995 and P1394a compliant link layer controller featuring an embedded SBP-2 transaction layer for data storage applications. The SAA7356HL provides full automation of the SBP-2 transaction layer to an extent that the user need not have knowledge of SBP-2 or 1394. CONDITIONS ...

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... CONTROLLER MICROCONTROLLER INTERFACE microcontroller interface 2000 Nov 17 32-bit data bus SRAM ARBITER SRAM Req/Ack flow control ARBITER SBP-2 AUTOMATION ENGINE Fig.1 Block diagram. 4 Preliminary specification SAA7356HL LINK 1394 PHY interface CORE DMA DMA interface CONTROL SAA7356HL GSA038 ...

Page 5

... DMA acknowledge signal input in slave mode (request in master/ATA mode) (may be configured for active HIGH or active LOW) ground 2 for core supply voltage 2 for core DMA read strobe input/output (may be configured for active HIGH or active LOW) 5 Preliminary specification SAA7356HL DESCRIPTION ...

Page 6

... PHY are directly connected or when bus-holder isolation is used; note 4 microcontroller select (1) input; selects microcontroller interface; note 10 note 7 asynchronous master reset input to the SAA7356HL (active LOW) reserved for factory testing; for normal operation should be connected to ground reserved for factory testing; for normal operation should be connected to ...

Page 7

... MICRO_SEL [1:0] = ‘10’ selects 16-bit 8031 mode; MICRO_SEL [1:0] = ‘11’ V851 mode. 2000 Nov 17 (1) microcontroller data input/output (bit 4); note 9 microcontroller data input/output (bit 5); note 9 ground 4 for core supply voltage 4 for core microcontroller data input/output (bit 6); note 9 microcontroller data input/output (bit 7); note 9 7 Preliminary specification SAA7356HL DESCRIPTION ...

Page 8

... MICRO_ADDR [ MICRO_ADDR [ MICRO_ADDR [ MICRO_ADDR [ DD2( SS2(P) 12 DMA_DATA [ DMA_DATA [ DMA_DATA [ DMA_DATA [ DMA_DATA [ DMA_DATA [ DD1( SS1(C) 20 2000 Nov 17 SAA7356HL Fig.2 Pin configuration. 8 Preliminary specification SAA7356HL RESET 58 1394_MODE MICRO_SEL [ PHY_ISO 55 PHY_LREQ MICRO_SEL [ PHY_SCLK 52 V SS5( DD5(P) PHY_DATA [ PHY_DATA [ PHY_DATA [ PHY_DATA [ DD4( SS4(P) PHY_DATA [ 3 ] ...

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... DMA_REQ DMA_ACK Fig.3 Functional diagram. The microcontroller will return the requested information. The SAA7356HL will then add the required header for the 1394 transaction to service these requests. 7.3 The SAA7356HL supports many formats of DMA interface. The DMA bus width may bits wide. The polarity of the request, acknowledge, read and write strobes can be configured for active HIGH or active LOW ...

Page 10

... DMA interface flow control by the time duration between successive acknowledge assertions or read/write assertions. 2000 Nov 17 In master mode the SAA7356HL appears Advanced Technology Attachment (ATA) host and can be connected to an ATA or Advanced Technology Attachment Packet Interface (ATAPI) peripheral. The ...

Page 11

... BUFFER SAA7356HL MANAGER master mode 1 Fig.5 Master Mode 0, 1 and 2. 11 Preliminary specification SAA7356HL DMA_REQ DMA_ACK buffer data 16 or 8-bit BUFFER SAA7356HL MANAGER GSA040 slave mode 2 DMA_ACK DMA_REQ DMA_REQ DMA_ACK buffer data 16 or 8-bit BUFFER SAA7356HL MANAGER GSA041 master mode 2 ...

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... The microcontroller will read from the CmdToMicro register to find the interrupt reason. If parameters are required with the command then this is implied in the command byte.These parameters may then be read from the SAA7356HL RAM using the RAM.Offset and the RAM.Next registers. 7.6 Address map for the SAA7356HL The address mapping for the 4-bit, 8-bit and 16-bit addressing modes is given in Table 1 ...

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... CLK MICRO_ADDR AS MICRO_READ MICRO_DATA(read) MICRO_WRITE MICRO_DATA(write) MICRO_WAIT handbook, full pagewidth CLK MICRO_ADDR MICRO_ALE(ASTB) MICRO_READ(DSTB) MICRO_DATA(read) MICRO_READ(R/W) MICRO_DATA(write) MICRO_WAIT 2000 Nov Fig.6 H8 microcontroller interface timing ADDRESS ADDRESS Fig.7 V851 microcontroller interface timing. 13 Preliminary specification SAA7356HL Tw T3 GSA042 Tw T3 DATA DATA GSA043 ...

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... CmdMicro bit and negating the interrupt (if no other interrupts are pending): writing a logic 0 to the CmdMicro bit has no effect. On signalling the acknowledgment, the value in the CmdToMicro register is unchanged, but now the SAA7356HL is free to modify the CmdToMicro register contents. 14 Preliminary specification ...

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... The definition of the InterruptReason, InterruptEnable and the InterruptSet register fields are shown in Table 8. BIT 5 BIT 4 BIT 3 BIT 5 BIT 4 BIT 3 BIT 5 BIT 4 BIT 3 15 Preliminary specification SAA7356HL BIT 2 BIT 1 BIT 0 BIT 2 BIT 1 BIT 0 BIT 2 BIT 1 BIT 0 BIT 2 BIT 1 BIT 0 CmdMicro ...

Page 16

... Reserved X 8.4 RAM access for parameter passing Within the SAA7356HL there kbyte RAM. This is shared between: the IEEE1394 transaction FIFOs, the code for the automation engine and its local storage requirements, and the shared memory area for communications with the microcontroller. ...

Page 17

... NUMBER 0 RAM.Next(7:0) Table 11 Definition of the RAM.Current register (read/write) BYTE BIT 7 BIT 6 NUMBER 0 RAM.Current(7:0) 2000 Nov 17 BIT 5 BIT 4 BIT 3 RAM.Offset (13:8) BIT 5 BIT 4 BIT 3 BIT 5 BIT 4 BIT 3 17 Preliminary specification SAA7356HL BIT 2 BIT 1 BIT 0 BIT 2 BIT 1 BIT 0 BIT 2 BIT 1 BIT 0 ...

Page 18

... Nov 17 CONDITIONS microcontroller and DMA pins PHY pins package comma mode o C. CONDITIONS microcontroller and DMA pins PHY pins 18 Preliminary specification SAA7356HL MIN. MAX. UNIT 0.5 +4 0 150 ...

Page 19

... Under idle conditions the average value is 108 mA. 2000 Nov 17 CONDITIONS MIN. note 1 2.4 note 1 note 2 0.5V + 0.12 DD note 2 0.5V 0.66 DD note 1 2.4 note 1 - note 3 2.9 note 3 note 1 note 4 note 5 note 3 note 6 19 Preliminary specification SAA7356HL TYP. MAX. UNIT V 0.8 V 0. 0. 100 200 A mA ...

Page 20

... DMA_ACK active pulse duration during data write 5 t read data stable after DMA_ACK assert 6 t read data 3-state after DMA_ACK de-assert 7 2000 Nov 17 PARAMETER 0; see Fig.8 1; see Fig.9 2; see Fig.10 20 Preliminary specification SAA7356HL CONDITIONS MIN. TYP ...

Page 21

... DMA_ACK active pulse duration during data write 5 t read data stable after DMA_ACK assert 6 t read data 3-state after DMA_ACK de-assert 7 2000 Nov 17 PARAMETER 0; note 1; see Fig.11 1; note 1; see Fig.12 2; note 1; see Fig.13 21 Preliminary specification SAA7356HL CONDITIONS MIN. TYP ...

Page 22

... FIFO reads or a FIFO read or write followed by a read of the FIFO flag 3 CP registers. 9. This time relates to accesses to addresses other than RAM.Next and RAM.Current. 10. This time relates to accesses to the addresses RAM.Next and RAM.Current. 2000 Nov 17 PARAMETER 22 Preliminary specification SAA7356HL CONDITIONS MIN. TYP note 2 ...

Page 23

... DMA_DATA [ 15:0 ] DMA_WRITE DMA_DATA [ 15:0 ] DMA_REQ is configured active HIGH. DMA_ACK, DMA_WRITE and DMA_READ are configured active LOW. Fig.9 DMA interface write/read timing diagram for slave mode 1. 2000 Nov write data read data read data write data 23 Preliminary specification SAA7356HL GSA044 GSA045 ...

Page 24

... DMA_READ DMA_DATA [ 15:0 ] DMA_REQ is configured active HIGH. DMA_ACK, DMA_WRITE and DMA_READ are configured active LOW. Fig.11 DMA interface write/read timing diagram for master mode 0. 2000 Nov write data t 6 read data write data read data 24 Preliminary specification SAA7356HL GSA046 GSA047 ...

Page 25

... DMA_REQ DMA_ACK DMA_DATA [ 15:0 ] DMA_DATA [ 15:0 ] DMA_REQ is configured active HIGH. DMA_ACK is configured active LOW. Fig.13 DMA interface write/read timing diagram for master mode 2. 2000 Nov read data write data write data t 6 read data 25 Preliminary specification SAA7356HL GSA048 GSA049 ...

Page 26

... PHY_CTRL [ 1:0 ] Fig.14 Data and control input set-up and hold timing waveforms. handbook, full pagewidth PHY_DATA [ 7:0 ] PHY_CTRL [ 1:0 ] Fig.15 Data, control and PHY_LREQ output delay timing waveforms. 2000 Nov 17 PHY_SCLK t 1 PHY_SCLK t 3 PHY_LREQ 26 Preliminary specification SAA7356HL t 2 GSA050 GSA051 ...

Page 27

... MICRO_ADDR [ 7:0 ] handbook, full pagewidth (16-bit mode only) MICRO_ALE MICRO_CS MICRO_WRITE MICRO_DATA [ 7:0 ] ADDRESS Fig. 16-bit addressed 8031 register write timing diagram. 2000 Nov 17 UPPER ADDRESS ADDRESS ADDRESS Preliminary specification SAA7356HL UPPER ADDRESS DATA ADDRESS DATA ADDRESS GSA052 DATA GSA053 ...

Page 28

... MICRO_ADDR MICRO_CS MICRO_READ MICRO_DATA Fig.18 8-bit addressed H8 register read timing diagram. handbook, full pagewidth MICRO_ADDR MICRO_CS MICRO_READ MICRO_DATA MICRO_WAIT Fig.19 8-bit addressed H8 register read timing diagram with MICRO_WAIT asserted. 2000 Nov 17 ADDRESS DATA ADDRESS DATA Preliminary specification SAA7356HL GSA054 GSA055 ...

Page 29

... Fig.20 8-bit addressed H8 register write timing diagram. handbook, full pagewidth MICRO_ADDR [ 7:0 ] MICRO_ALE MICRO_CS MICRO_READ MICRO_DATA [ 7:0 ] Fig.21 16-bit addressed V851 register read timing diagram. 2000 Nov 17 ADDRESS DATA ADDRESS ADDRESS 29 Preliminary specification SAA7356HL ADDRESS t 18 DATA GSA056 DATA GSA057 ...

Page 30

... APPLICATION INFORMATION handbook, full pagewidth CD-RW ENGINE CD-RW LOADER 2000 Nov DRAM 2 I S-bus BUFFER MANAGER DMA SPI SAA7391 MICROCONTROLLER Fig.23 Application diagram. 30 Preliminary specification SAA7356HL ADDRESS DATA ADDRESS 1394 bus SBP-2 LINK PHY 1394 PHY SAA7356HL GSA059 DATA GSA058 ...

Page 31

... Nov scale (1) ( 0.27 0.18 12.1 12.1 14.15 14.15 0.5 0.13 0.12 11.9 11.9 13.85 13.85 REFERENCES JEDEC EIAJ MS-026 31 Preliminary specification detail 0.75 1.0 0.2 0.15 0.1 0.30 EUROPEAN PROJECTION SAA7356HL SOT315 (1) ( 1.45 1. 1.05 1.05 0 ISSUE DATE 99-12-27 00-01-19 ...

Page 32

... Use a low voltage ( less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds 300 C. When using a dedicated tool, all other leads can be soldered in one operation within seconds between 270 and 320 C. 32 Preliminary specification SAA7356HL ...

Page 33

... Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 2000 Nov 17 SOLDERING METHOD WAVE not suitable (2) not suitable suitable (3)(4) not recommended (5) not recommended 33 Preliminary specification SAA7356HL (1) REFLOW suitable suitable suitable suitable suitable ...

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... Preliminary specification SAA7356HL (1) These products are not Philips Semiconductors ...

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... Philips Semiconductors 1394 SBP-2 link layer controller 2000 Nov 17 NOTES 35 Preliminary specification SAA7356HL ...

Page 36

... Tel. +46 8 5985 2000, Fax. +46 8 5985 2745 Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH, Tel. +41 1 488 2741 Fax. +41 1 488 3263 Taiwan: Philips Semiconductors, 5F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2451, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 60/14 MOO 11, Bangna Trad Road KM ...

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