SAA7392HL Philips Semiconductors, SAA7392HL Datasheet

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SAA7392HL

Manufacturer Part Number
SAA7392HL
Description
Channel encoder/decoder CDR60
Manufacturer
Philips Semiconductors
Datasheet

Specifications of SAA7392HL

Case
QFP
Preliminary specification
File under Integrated Circuits, IC01
DATA SHEET
SAA7392
Channel encoder/decoder CDR60
INTEGRATED CIRCUITS
2000 Mar 21

Related parts for SAA7392HL

SAA7392HL Summary of contents

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DATA SHEET SAA7392 Channel encoder/decoder CDR60 Preliminary specification File under Integrated Circuits, IC01 INTEGRATED CIRCUITS 2000 Mar 21 ...

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... Philips Semiconductors Channel encoder/decoder CDR60 CONTENTS 1 FEATURES 2 GENERAL DESCRIPTION 3 QUICK REFERENCE DATA 4 ORDERING INFORMATION 5 BLOCK DIAGRAM 6 PINNING INFORMATION 6.1 Pinning 6.2 Pin description 7 FUNCTIONAL DESCRIPTION 7.1 Microprocessor interfaces 7.2 Register map 7.3 System clocks 7.4 HF analog front-end 7.5 Bit recovery 7.6 Decoder function 7 ...

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... ORDERING INFORMATION TYPE NUMBER NAME SAA7392HL LQFP80 plastic low profile quad flat package; 80 leads; body 12 2000 Mar 21 The bit detector recovers the individual bits from the incoming signal, correcting asymmetry, performing noise filtering and equalisation, and recovering the channel bit clock using a digital PLL ...

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Acrobat reader. white to force landscape pages to be ... WREFMID WIN WREFLO WREFHI ATIPSYC WOBBLE IREF IREF PROCESSOR ...

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... Philips Semiconductors Channel encoder/decoder CDR60 6 PINNING INFORMATION 6.1 Pinning handbook, full pagewidth WREFLO 1 WREFHI 2 WREFMID 3 V SSA1 4 V DDA1 5 WIN 6 VREF 7 IREF 8 n.c. 9 HREFHI 10 HREFLO 11 AGCREF 12 HIN 13 HREFMID 14 V DDA2 15 V SSA2 16 TEST1 17 TEST2 18 V SSD 19 V DDE 20 2000 Mar 21 SAA7392 Fig ...

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... Philips Semiconductors Channel encoder/decoder CDR60 6.2 Pin description Table 1 LQFP80 package; note 1 SYMBOL PIN WREFLO 1 WREFHI 2 WREFMID SSA1 V 5 DDA1 WIN 6 VREF 7 IREF 8 n.c. 9 HREFHI 10 HREFLO 11 AGCREF 12 HIN 13 HREFMID DDA2 V 16 SSA2 TEST1 17 TEST2 18 V 19, 43, 62, 71 SSD V 20 DDE XTLI ...

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... Philips Semiconductors Channel encoder/decoder CDR60 SYMBOL PIN DA3 39 DA2 40 DA1 41 DA0 DDE WRi 45 RDi 46 ALE 47 CSi 50 PCAin 51 STOPCK EBUOUT 56 SYNC 57 FLAG 58 DATAO 59 WCLK 60 BCLK DDE DATAI 64 SUB 65 RCK 66 SFSY 67 CFLG DDE MOTO2/T3 73 MOTO1 74 LASERON 77 XEFM 78 EFMDATA 79 MEAS1 80 Notes 1. No signal may be applied to this device when it is not powered. ...

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... Philips Semiconductors Channel encoder/decoder CDR60 7 FUNCTIONAL DESCRIPTION 7.1 Microprocessor interfaces The SAA7392 is programmed via two independent microprocessor interfaces: 2 Serial I C-bus 2 – SDA = I C-bus data 2 – SCL = I C-bus clock 2 – I C-bus write address = 3EH 2 – I C-bus read address = 3FH. Parallel 80C51 compatible – ...

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... Philips Semiconductors Channel encoder/decoder CDR60 handbook, full pagewidth ALE RDi CSi DA0 to DA7 Table 2 Parallel interface timing SYMBOL t Delay ALE falling to RDi/WRi falling Delay CSi rising to RDi/WRi falling CSi hold time after RDi/WRi falling Address setup time before ALE falling. su1 t Address hold time after ALE falling ...

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Acrobat reader. white to force landscape pages to be ... 7.2 Register map Table 3 Register map ADDRESS REGISTER NAME (HEX) 00 PLL Lock ...

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Acrobat reader. white to force landscape pages to be ... ADDRESS REGISTER NAME (HEX) 12 Clock Preset Register (ClockPre) 13 Decoder Mode Select Register ...

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Acrobat reader. white to force landscape pages to be ... ADDRESS REGISTER NAME (HEX) 2D ATIP Data End Register (ATIPDataEnd) 2E Wobble Peak Status ...

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... Philips Semiconductors Channel encoder/decoder CDR60 7.2.1 I NTERRUPT PIN The interrupt pin (INT) is the AND-OR-INVERT of the Status and Interrupt Enable Registers, i.e. INT will become active when corresponding bits are set at the same time in the Status and Interrupt Enable Registers. 7.2 EMAPHORE EGISTERS The Semaphore Registers are intended for inter-microprocessor communications ...

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... Philips Semiconductors Channel encoder/decoder CDR60 7.2 NTERRUPT NABLE EGISTER Table 9 Interrupt Enable Register (address 0BH) - WRITE 7 6 Sema1En Sema2En Sema3En Table 10 Description of IntEn bits BIT SYMBOL 7 Sema1En If Sema1En = 1, then Semaphore Register 1 interrupt is enabled. 6 Sema2En If Sema2En = 1, then Semaphore Register 2 interrupt is enabled. 5 Sema3En If Sema3En = 1, then Semaphore Register 3 interrupt is enabled ...

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... Philips Semiconductors Channel encoder/decoder CDR60 7.2 NTERRUPT NABLE EGISTER Table 13 Interrupt Enable Register 2 (address 21H) - WRITE 7 6 BankSwitch SyncErrorEn DataNotValid En Table 14 Description of IntEn2 bits BIT SYMBOL 7 BankSwitch If BankSwitchEn = 1, then BankSwitch interrupt is enabled SyncErrorEn If SyncErrorEn = 1, then SyncError interrupt is enabled. 5 DataNotVali If DataNotValidEn = 1, then DataNotValid interrupt is enabled. ...

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... Philips Semiconductors Channel encoder/decoder CDR60 7.3 System clocks The principle clocks used in the SAA7392 are derived from the crystal oscillator input pin XTLI (alternatively, an external clock can be connected to this pin). These clocks are the system clock (also used as the ADC clock) and the I bit clock (BCLK) ...

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... Philips Semiconductors Channel encoder/decoder CDR60 7.3 LOCK RESET EGISTER Table 17 Clock Preset Register (address 12H) - WRITE 7 6 CL1Div GateBClk Table 18 Description of ClockPre bits BIT SYMBOL 7 CL1Div If CL1Div = 0, then CL1 output frequency is frequency is 6 GateBClk If GateBClk = 0, then I output bit clock gating enabled, BCLK is output, clock is automatically stopped if FIFO underfl ...

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... Philips Semiconductors Channel encoder/decoder CDR60 7.4 HF analog front-end The HF ADC in the SAA7392 encodes the EFM high frequency signal from the disc light pen assembly. These signals are pre-processed, externally to the SAA7392, by either AEGER DALAS equivalent. The dynamic range of the ADC is optimized by the inclusion coupled AGC function under digital control ...

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... Philips Semiconductors Channel encoder/decoder CDR60 7.5 Bit recovery The bit recovery block (shown in Fig.6) contains the slice level circuitry, a noise filter to limit the HF-EFM signal noise contribution, an adaptive slicer circuit and a digital PLL. These blocks can be controlled via the microprocessor. The channel rate should always obey the following ...

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... Philips Semiconductors Channel encoder/decoder CDR60 7.5.1 D PLL IGITAL The digital PLL will recover the channel bit clock. As the capture range of the PLL itself is limited, lock detectors and 2 capture aids are present. In total three different PLL operation modes exist: In-lock, Inner-lock aid and Outer-lock aid ...

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... Philips Semiconductors Channel encoder/decoder CDR60 7.5.2 MEAS1 PIN The MEAS1 pin carries the 3 measurement signals: jitter (sampled twice), PLL frequency, and asymmetry. Each frame consists of 64 bits (each 4 system clock periods long), beginning with a start bit, then data bits then pause bits (see Fig.8). The start bit is always preceded by 17 pause bits ...

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... Philips Semiconductors Channel encoder/decoder CDR60 7.5.3 PLL OCK ELECT EGISTER The behaviour of this register is dependent upon whether its being read or written. The behaviour for the write operation is described in Tables 24 to 27. When read the 8 MSBs of the PLL frequency counter are returned; this is described in Tables 24 and 28 ...

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... Philips Semiconductors Channel encoder/decoder CDR60 Table 28 Description of PLLock bits for read operation BIT SYMBOL PLLFreq<7:0> This register holds the 8 MSBs of the PLL frequency counter. The PLL frequency is calculated as shown below: f PLL 7.5.4 PLL B S ANDWIDTH ELECT The function of this register is dependent upon whether its being read or written. The function for the write operation is described in Tables ...

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... Philips Semiconductors Channel encoder/decoder CDR60 Table 33 Selection of PLL bandwidth PLLBWF1.1 PLLBWF1 21000 10528 5264 2632 Hz Table 34 Selection of low-pass bandwidth LPBWF2.1 LPBWF2 42100 21000 10528 This value is reserved. 7.5.5 PLL F P REQUENCY RESET The function of this register is dependent upon whether its being read or written. Tables 35 and 36 define the register function for the write operation ...

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... Philips Semiconductors Channel encoder/decoder CDR60 7.5.6 PLL E P QUALIZER RESET The function of this register is dependent upon whether its being read or written. Tables 38, 39 and 40 define the register function for the write operation. Tables 38 and 41 define the register function for the read operation. ...

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... Philips Semiconductors Channel encoder/decoder CDR60 7.5.7 PLL OCK ID RESET The PLL setting point for the EFM counting locking strategy is controlled by setting the PLL frequency such that, there are, on average, a fixed number of EFM transitions per PLL clock period: PLL Locking Frequency/EFM Transition Frequency = (EFM_Count + 32)/ typical application. ...

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... Philips Semiconductors Channel encoder/decoder CDR60 7.5 ITERBI ETECTOR ETTING This register controls an advanced data slicer for improved bit detector performance. An adaptive slicer performs a second slice operation. This has a higher bandwidth than the first slicer. If switched on, the run length 2 push-back circuit pushes all run length two symbols to run length 3 ...

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... Philips Semiconductors Channel encoder/decoder CDR60 Table 48 Motor Control Register 1 (address 0CH) - READ 7 6 ASCV.7 ASCV.6 7.6 Decoder function 7.6.1 D EMODULATOR The demodulator block includes sync extraction, interpolation and protection circuits, and converts the 14-bit EFM data and subcode words into 8-bit symbols. ...

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... Philips Semiconductors Channel encoder/decoder CDR60 7.6 ECODER ODE ELECT Table 50 Decoder Mode Select Register (address 13H) - WRITE 7 6 Mode.6 Mode.5 Table 51 Description of DecoMode bits BIT SYMBOL Mode<6:0> These 7 bits select the Decoder mode; see Table 52. 0 LWCon When a logic 0, LaserOn and WriteOn2 signals operate normally. When a logic 1, LaserOn and WriteOn2 signals are reset ...

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... Philips Semiconductors Channel encoder/decoder CDR60 7.6.5 D FIFO ATA The decoder block can be viewed as a FIFO, demodulated data is written in while the output interface reads from it. The way in which the FIFO is filled depends on the decoder mode set via register DecoMode. The decoder modes that effect the filling of the FIFO are described in Sections 7 ...

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... Philips Semiconductors Channel encoder/decoder CDR60 7.7 LOCK RESET EGISTER This is a dual-function register. When read the status of the Q-channel is returned. Table 55 Clock Preset Register (address 12H) - READ 7 6 Ready Busy Table 56 Description of ClockPre bits BIT SYMBOL 7 Ready If Ready = 0, then buffer filling. If Ready = 1, then valid Q subcode frame available. ...

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... Philips Semiconductors Channel encoder/decoder CDR60 7.8 Digital output The AES/EBU signal is available on pin EBUOUT, according to the format defined by the “IEC958 specification” . This signal is only available in the CLV modes of the decoder (not in QCLV). Three different modes can be selected: EBU off EBU data all zero EBU data valid ...

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... Philips Semiconductors Channel encoder/decoder CDR60 7.8.2 F ORMAT The digital audio output consists of 32-bit words (subframes) transmitted in biphasemark code (two transitions for a logic 1 and one transition for a logic 0). Words are transmitted in blocks of 384. Table 61 Digital audio output subframe format BIT FIELD NAME ...

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... Philips Semiconductors Channel encoder/decoder CDR60 7.9 Serial output interface The serial data output interface consists of three signals: WCLK (word select), BCLK (serial clock), DATAO (serial data). The polarity of WCLK and the data can be inverted. The FLAG signal is used to identify if there are errors in either the LSB or MSB of the 16-bit data word ...

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... Philips Semiconductors Channel encoder/decoder CDR60 handbook, full pagewidth BCLK DATA D15 D14 D13 D12 D11 D10 D9 FLAG FLAG - MSB (1 is unreliable) left WCLK SYNC handbook, full pagewidth BCLK DATA D1 D0 FLAG FLAG - MSB (1 is unreliable) right WCLK SYNC Fig.14 Format 4: 24 clocks/word ‘S’ format (WCLK inverted). ...

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Acrobat reader. white to force landscape pages to be ... BCLK DATA D15 D14 D13 D12 D11 D10 FLAG FLAG - ...

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... Philips Semiconductors Channel encoder/decoder CDR60 2 7.9 UTPUT EGISTER 2 Table Output Register 1 (address 05H) - WRITE 7 6 Format.2 Format.1 Table 64 Description of Output1 bits BIT SYMBOL 7 Format.2 These 3 bits select the format; see Table 65. 6 Format.1 5 Format.0 4 WClkIO When WClkIO = 0, then WCLK is in Input mode. When WClkIO = 1, then WCLK is in Output mode ...

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... Philips Semiconductors Channel encoder/decoder CDR60 2 7.9 UTPUT EGISTER 2 Table Output Register 3 (address 07H) - WRITE 7 6 WClkHLeft DescrmOn Table 69 Description of Output3 bits BIT SYMBOL 7 WClkHLeft When WClkHLeft = 0, then WCLK is HIGH on right byte format modes). When WCLKHLeft = 1, then WCLK is HIGH on left byte of I format output; (use for S format modes). ...

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... Philips Semiconductors Channel encoder/decoder CDR60 7.10 Motor control The spindle motor is controlled by a fully integrated digital servo sub-system within the SAA7392. Information from the data FIFO, data recovery PLL and tacho inputs may be used to calculate the motor control output signals. The frequency set-point, the FIFO settings and coefficients G, K control registers ...

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... Philips Semiconductors Channel encoder/decoder CDR60 7.10 OTOR ONTROL EGISTER The frequency/tacho set-point (i.e. the target PLL or tacho frequency) is calculated as follows: MFS<7:0> Frequency set-point 1 = – --------------------------- - PLLFreqR<7:0> PLL frequency = ----------------------------------------- - 128 Note that: (PLL frequency frequency set-point) must be less than 1.33 Table 70 Motor Control Register 1 (address 0CH) - WRITE ...

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... Philips Semiconductors Channel encoder/decoder CDR60 Table 74 Selection of coefficient K Ki 2.4 Table 75 Selection of the coefficient K Kf.2 Kf 7.10 OTOR ONTROL EGISTER Table 76 Motor Control Register 7 (address 1DH) - WRITE 7 6 PhErSrc Table 77 Description of Motor7 bits BIT SYMBOL 7 PhErSrc If PhErSrc = 0, then the phase error source is FIFOFil. If PhErSrc = 1, then the phase error source is XError ...

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... Philips Semiconductors Channel encoder/decoder CDR60 Table 78 Selection of coefficient K Kf’.2 Kf’.1 Ki’.2 Ki’. 7.10 OTOR ONTROL EGISTER The function of this register is dependent upon whether its being read or written. When written, the value determines the FIFO set-point value in C1 frames (one C1 frame is 24 bytes). The FIFO set-point value should be set to a value greater than 110 frames for CD Fast mode and greater than 219 frames for CD Normal mode ...

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... Philips Semiconductors Channel encoder/decoder CDR60 7.10 OTOR ONTROL EGISTER Table 81 Motor Control Register (address 0FH) - WRITE 7 6 PWM_PDM OVF_SW Table 82 Description of Motor4 bits BIT SYMBOL 7 PWM_PDM If PWM_PDM = 0, then motor control in PWM mode. If PWM_PDM = 1, then motor control in PDM mode. 6 OVF_SW If OVF_SW = 0, then SW1 and SW2 in normal operation. If OVF_SW = 1, then SW1 and SW2 will both open on overfl ...

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... Philips Semiconductors Channel encoder/decoder CDR60 7.10 OTOR ONTROL EGISTERS These two registers hold the 16-bit motor integrator value. The motor integrator value can be read or updated using registers Motor5 and Motor6. Register Motor5 should be read or written first to prevent spurious results. 7.10.6.1 Motor Control Register 5 (Motor5) ...

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... Philips Semiconductors Channel encoder/decoder CDR60 7.10 ACHO ONTROL EGISTER Table 88 Tacho Control Register 3 (address 19H) - WRITE 7 6 SConS.1 SConS.0 TachoFRes Table 89 Description of Tacho3 bits BIT SYMBOL 7 SConS.1 These 2 bits select the motor servo frequency source; see Table 90. 6 SConS.0 5 TachoFRes If TachoFRes = 0, then the tacho filter is enabled (normal mode). If TachoFRes = 1, then the tacho fi ...

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... Philips Semiconductors Channel encoder/decoder CDR60 7.11 The serial in function The serial in function takes serial data from the block decoder and passes the data on to the encoder. It supports the I and Sony 3-wire serial interfaces (DATAI, BCLK and WCLK). The block is slave to the interface and therefore the BCLK and WCLK signals are generated externally and are the same signals as the serial data output interface ...

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... Philips Semiconductors Channel encoder/decoder CDR60 7.12 The subcode insert function The SAA7392 allows two modes of subcode insertion: Bypass mode and Auto-format mode. Bypass mode. In this mode the subcode is generated by a block decoder (such as PLUM) and transmitted to the SAA7392 via the proprietary Subcode Record Interface (SRI) ...

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... Philips Semiconductors Channel encoder/decoder CDR60 7.12 UBCODE ONFIGURATION Table 96 Subcode Configuration Register 1 (address 23H) - WRITE 7 6 sri_on p_toggle Table 97 Description of SubConfig1 bits BIT SYMBOL 7 sri_on If sri_on = 0, then subcode generated by CDR60 for P and Q-channels channels are all logic 0’s. If sri_on = 1, then subcode data from SRI except Q-channel CRC and S0 and S1 bytes. SRI frame sync checking is enabled. SubConfi ...

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... Philips Semiconductors Channel encoder/decoder CDR60 7.12 UBCODE ONFIGURATION Table 99 Subcode Configuration Register 2 (address 24H) - READ/WRITE 7 6 BSwOn InOBO Table 100 Description of SubConfig2 bits BIT SYMBOL 7 BSwOn If BSwOn = 0, then no bank switching. If BSwOn = 1, then bank switch will occur when first subcode sync output by EFM modulator and curcnt<2:0> = 000 ...

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... Philips Semiconductors Channel encoder/decoder CDR60 7.12.6 G CD-T ENERATING EXT CD-Text is stored in the channels of the disc. The CD-Text standard states that a CD-Text disc must at least contain CD-Text information in the lead-in, and it may contain CD-Text information in the program area. CDR60 supports writing of the subcode channels only in bypass mode which means that the whole subcode information has to be generated from an external device ...

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... Philips Semiconductors Channel encoder/decoder CDR60 7.14 NCODE TART FFSET Table 106 Encode Start Offset Register (address 31H) - WRITE 7 6 StartOffset.7 StartOffset.6 StartOffset.5 StartOffset.4 StartOffset.3 StartOffset.2 StartOffset.1 StartOffset.0 Table 107 Description of EncodeStartOffset bits BIT SYMBOL StartOffset<7:0> 7.14 NCODE TOP FFSET Table 108 Encode Stop Offset Register (address 32H) - WRITE ...

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... Philips Semiconductors Channel encoder/decoder CDR60 7.15 The EFM modulator This block takes data from the data encoder block and adds the subcode and synchronisation information. This data stream is modulated using EFM according to the Red Book standard. This data is output serially from the SAA7392, with the associated EFM clock signal ...

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... Philips Semiconductors Channel encoder/decoder CDR60 7.15.3 EFM M C ODULATOR ONFIGURATION Table 116 EFM Modulator Configuration Register 2 (address 3EH) - WRITE 7 6 Table 117 Description of EFMModConfig2 bits BIT SYMBOL These 5 bits are reserved. 2 TIM2Mode These 2 bits control the XEFM output; see Table 118. ...

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... Philips Semiconductors Channel encoder/decoder CDR60 7.16 The EFM clock generator The EFM clock generator will produce the recording clock based on one of three reference sources. There are five stages to the function. The first selects the reference source using a multiplexer. The next stage is a digital PLL to up-multiply the reference source ...

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... Philips Semiconductors Channel encoder/decoder CDR60 7.16.1 EFM C C LOCK ONFIGURATION Table 120 EFM Clock Configuration Register 1 (address 34H) - WRITE 7 6 DPLLBW.2 DPLLBW.1 DPLLBW.0 Table 121 Description of EFMClockConf1 bits BIT SYMBOL 7 DPLLBW.2 These 3 bits select the digital PLL bandwidth; see Table 122. ...

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... Philips Semiconductors Channel encoder/decoder CDR60 7.16.2 EFM C C LOCK ONFIGURATION Table 124 EFM Clock Configuration Register 2 (address 35H) - WRITE 7 6 FreqSrc.1 FreqSrc.0 Table 125 Description of EFMClockConf2 bits BIT SYMBOL 7 FreqSrc.1 These 2 bits select the frequency source for the PLL; see Table 126. ...

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... Philips Semiconductors Channel encoder/decoder CDR60 7.16.3 EFM C C LOCK ONFIGURATION This is a dual-function register, the specific function is controlled by the state of bit 7. The integrator of the PI controller can be preset by writing to this register with the MSB set to logic 0. The value written is interpreted as a signed value. The current integrator value can be read back via this register. ...

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... Philips Semiconductors Channel encoder/decoder CDR60 7.16.4 EFM C C LOCK ONFIGURATION (EFMC C F4) LOCK ON This is a dual-function register, the specific function is controlled by the state of bit 7. The sample rate of the integrator may be programmed by writing to this register when the MSB is set to a logic 1. Higher sample rates let the integrator work faster. This is effectively the same as increasing the K Table 132 EFM Clock Confi ...

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... Philips Semiconductors Channel encoder/decoder CDR60 7.17 The Wobble processor The Wobble processor is a critical part of the recording process, and performs two main functions: To extract the ATIP data from the wobble signal To control the linear disc speed during recording. The Wobble processor comprises four functions, a front-end ADC, a digital PLL, the ATIP bit detector and the ATIP data read interface ...

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... Philips Semiconductors Channel encoder/decoder CDR60 Table 137 Selection of integrator bandwidth PLLIntBW.2 PLLIntBW.1 PLLIntBW Table 138 Selection of loop bandwidth LOOPBW.2 LOOPBW.1 LOOPBW Table 139 Description of WobbleConfig1 bits, bit BIT SYMBOL 6 ATIPhold When ATIPhold = 1, then Wobble PLL in Hold mode. 5 This bit is reserved. ...

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... Philips Semiconductors Channel encoder/decoder CDR60 7.17 OBBLE ONFIGURATION Table 140 Wobble Configuration Register 2 (address 28H) - WRITE 7 6 PLLLBW.2 Table 141 Description of WobbleConfig2 bits BIT SYMBOL 7 These 2 bits are reserved PLLLBW.2 These 3 bits select the PLL low-pass bandwidth; see Table 142. ...

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... Philips Semiconductors Channel encoder/decoder CDR60 7.17.7 ATIP S R TATUS EGISTER Table 143 ATIP Status Register (address 29H) - READ 7 6 ATIPReady Busy Table 144 Description of ATIPStatus bits BIT SYMBOL 7 ATIPReady If ATIPReady = 0, then ATIP data is not ready. If ATIPReady = 1, then ATIP data is ready for read. Can also be an interrupt source. ...

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... Philips Semiconductors Channel encoder/decoder CDR60 7.17.10 ATIP D R (ATIPD ATA EGISTER The upper 16 bits of the ATIP data can be obtained from this register by carrying out consecutive read operations. Table 149 ATIP Data Register (address 2CH) - READ 7 6 ATIPData.23 ATIPData.22 ATIPData.21 ATIPData.20 ATIPData.19 ATIPData.18 ATIPData.17 ATIPData.16 ATIPData ...

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... Philips Semiconductors Channel encoder/decoder CDR60 8 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL PARAMETER V supply voltage - pad output drivers DDE V supply voltage - core/pad ring DDD V supply voltage - analog DDA V maximum input voltage (any input) i(max) V output voltage (any output) ...

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... Philips Semiconductors Channel encoder/decoder CDR60 9 OPERATING CHARACTERISTICS SYMBOL PARAMETER Supply V supply voltage (core/pad ring) DDD V supply voltage (analog) DDA V supply voltage (pad output drivers) DDE I supply current DD Digital inputs SCL (CMOS) V LOW-level input voltage IL V HIGH-level input voltage IH I input leakage current ...

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... Philips Semiconductors Channel encoder/decoder CDR60 SYMBOL PARAMETER I 3-state leakage current LI C input capacitance i V LOW-level output voltage OL V HIGH-level output voltage OH C load capacitance L t output rise time r t output fall time f 2 SDA ( BUS V LOW-level input voltage IL V HIGH-level input voltage ...

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... Philips Semiconductors Channel encoder/decoder CDR60 9.1 ADC and AGC parameters Table 156 ADC parameters PARAMETER VALUE Resolution 8-bit Data format Simple Binary Maximum sample 70 MS/s frequency SINAD >26 dB DNL 1.0/+1.0 LSB INL 2.0/+2.0 LSB Power dissipation <100 mW Input range 1 ...

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... Philips Semiconductors Channel encoder/decoder CDR60 10 APPLICATION INFORMATION 10.1 Write start control of encoder in CD-ROM mode In CD-ROM mode, the CDR60 is intended to operate in lock-to-disc mode during write. When writing is stopped by the Encode Control Block, the data flow through the device will also stop. All pointers will stop incrementing and the ...

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... Philips Semiconductors Channel encoder/decoder CDR60 7. When the correct start address is found on the disc, the LaserOn and WriteOn2 signals are switched on at the same time result data flow in the encoder starts while data is written to the disc. 10.4 Start-up of encoder in synchronous stream mode In synchronous stream mode operation is different because the serial input stream cannot be gated off ...

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... Philips Semiconductors Channel encoder/decoder CDR60 11 PACKAGE OUTLINE LQFP80: plastic low profile quad flat package; 80 leads; body 1 pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT max. 0.16 1.5 mm 1.6 0.25 0.04 1.3 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...

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... Philips Semiconductors Channel encoder/decoder CDR60 12 SOLDERING 12.1 Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). ...

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... Philips Semiconductors Channel encoder/decoder CDR60 12.5 Suitability of surface mount IC packages for wave and reflow soldering methods PACKAGE BGA, LFBGA, SQFP, TFBGA HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS (3) PLCC , SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect) ...

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... Philips Semiconductors Channel encoder/decoder CDR60 13 DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. ...

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... Philips Semiconductors Channel encoder/decoder CDR60 2000 Mar 21 NOTES 74 Preliminary specification SAA7392 ...

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... Philips Semiconductors Channel encoder/decoder CDR60 2000 Mar 21 NOTES 75 Preliminary specification SAA7392 ...

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... Tel. +46 8 5985 2000, Fax. +46 8 5985 2745 Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH, Tel. +41 1 488 2741 Fax. +41 1 488 3263 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel ...

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