IDT70V5388S133BGI Integrated Device Technology, Inc., IDT70V5388S133BGI Datasheet

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IDT70V5388S133BGI

Manufacturer Part Number
IDT70V5388S133BGI
Description
IDT70V5388S133BGI3.3V 64/32K X 18 SYNCHRONOUS FOURPORT STATIC RAM
Manufacturer
Integrated Device Technology, Inc.
Datasheet

Specifications of IDT70V5388S133BGI

Case
BGA
Dc
05+

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IDT70V5388S133BGI
Manufacturer:
IDT
Quantity:
12 388
NOTE:
1. A
2. Port 2, Port 3, and Port 4 Logic Blocks are similar to Port 1 Logic Blocks.
©2002 Integrated Device Technology, Inc.
True four-ported memory cells which allow simultaneous
access of the same memory location
Synchronous Pipelined device
– 64/32K x 18 organization
Pipelined output mode allows fast 200MHz operation
High Bandwidth up to 14 Gbps (200MHz x 18 bits wide x
4 ports)
LVTTL I/O interface
High-speed clock to data access 3.0ns (max.)
3.3V Low operating power
Interrupt flags for message passing
Width and depth expansion capabilities
15
x is a NC for IDT70V5378.
A
0P1
CNTRST
CNTINC
CNTRD
CNTLD
MKRD
MKLD
- A
CNTINT
CLK
MRST
15P1
MRST
P1
P1
P1
P1
P1
P1
P 1
(1)
P1
I/O
I/O
Decision
Priority
Logic
9P1
0P1
R/W
CE
CE
- I/O
OE
UB
LB
- I/O
0P1
1P1
P1
P1
P1
P1
17P1
8P1
3.3V 64/32K X 18
SYNCHRONOUS
FOURPORT™ STATIC RAM
Addr.
Read
Back
Readback
Counter/
Register
Register
Address
Register
Port 1
Port 1
Port 1
Mask
1/0
0
1
R/W
CLK
CE
CE
MRST
0P1
1P1
P1
P1
1
Interrupt
Address
Decode
Port 1
Port 1
Logic
Counter wrap-around control
– Internal mask register controls counter wrap-around
– Counter-Interrupt flags to indicate wrap-around
Counter readback on address lines
Mask register readback on address lines
Global Master reset for all ports
Dual Chip Enables on all ports for easy depth expansion
Separate upper-word and lower-word controls on all ports
272-BGA package (27mm x 27mm 1.27mm ball pitch) and
256-BGA package (17mm x 17mm 1.0mm ball pitch)
Commercial and Industrial temperature ranges
JTAG boundary scan
MBIST (Memory Built-In Self Test) controller
Control
Port 1
I/O
INT
P1
Memory
64KX18
Array
5 64 9 d rw 0 1
CLKMBIST
,
TRST
TMS
TCK
TDI
IDT70V5388/78
PRELIMINARY
Controller
MBIST
JTAG
TDO
DSC-5649/2

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IDT70V5388S133BGI Summary of contents

Page 1

... P1 NOTE for IDT70V5378 Port 2, Port 3, and Port 4 Logic Blocks are similar to Port 1 Logic Blocks. ©2002 Integrated Device Technology, Inc. 3.3V 64/32K X 18 SYNCHRONOUS FOURPORT™ STATIC RAM Counter wrap-around control – Internal mask register controls counter wrap-around – Counter-Interrupt flags to indicate wrap-around ...

Page 2

IDT70V5388/78 3.3V 64/32K x 18 Synchronous FourPort™ Static RAM The IDT70V5388/ high-speed 64/32Kx18 bit synchronous FourPort RAM. The memory array utilizes FourPort memory cells to allow simultaneous access of any address from all four ports. Registers on control, ...

Page 3

IDT70V5388/78 3.3V 64/32K x 18 Synchronous FourPort™ Static RAM (4) 09/25/ I/O I/O I/O I/O I I/O I/O I/O I/O 16 ...

Page 4

IDT70V5388/78 3.3V 64/32K x 18 Synchronous FourPort™ Static RAM (2) 09/25/ I I ...

Page 5

IDT70V5388/78 3.3V 64/32K x 18 Synchronous FourPort™ Static RAM Port 1 Port 2 Port 3 (1) ( I/O - I/O I/O ...

Page 6

IDT70V5388/78 3.3V 64/32K x 18 Synchronous FourPort™ Static RAM P ort 1 P ort 2 MKLD MKLD MKLD MKRD MKRD MKRD INT INT INT ...

Page 7

IDT70V5388/78 3.3V 64/32K x 18 Synchronous FourPort™ Static RAM ...

Page 8

IDT70V5388/78 3.3V 64/32K x 18 Synchronous FourPort™ Static RAM MRST CNTRST MKLD CLK ( NOTES: ...

Page 9

IDT70V5388/78 3.3V 64/32K x 18 Synchronous FourPort™ Static RAM Symbol Rating (2) Terminal Voltage V TERM with Respect to GND (3) Temperature Under Bias T BIAS T Storage Temperature STG T Junction Temperature Output Current OUT NOTES: ...

Page 10

IDT70V5388/78 3.3V 64/32K x 18 Synchronous FourPort™ Static RAM Symbol Parameter Dynamic Operating Current (All Outputs Disabled, Ports Active) ( ...

Page 11

IDT70V5388/78 3.3V 64/32K x 18 Synchronous FourPort™ Static RAM Input Pulse Levels (Address & Controls) Input Pulse Levels (I/Os) Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load DATA OUT tCD (Typical, ns) 4 ...

Page 12

IDT70V5388/78 3.3V 64/32K x 18 Synchronous FourPort™ Static RAM Sym bol Param eter Fre Tim ...

Page 13

IDT70V5388/78 3.3V 64/32K x 18 Synchronous FourPort™ Static RAM Symbol Interrupt Timing Clock to INT Set Time t S INT Clock to INT Reset Time t R INT Clock to CNTINT Set Time t S CIN T Clock to CNTINT ...

Page 14

IDT70V5388/78 3.3V 64/32K x 18 Synchronous FourPort™ Static RAM t CH2 CLK LB (4) ADDRESS An (1 ...

Page 15

IDT70V5388/78 3.3V 64/32K x 18 Synchronous FourPort™ Static RAM CLK "A" R/W "A" ADDRESS "A" MATCH DATA VALID IN"A" t CCS CLK "B" R/W "B" ...

Page 16

IDT70V5388/78 3.3V 64/32K x 18 Synchronous FourPort™ Static RAM t CYC2 t t CH2 CL2 CLK LB (3) An ADDRESS t ...

Page 17

IDT70V5388/78 3.3V 64/32K x 18 Synchronous FourPort™ Static RAM t CYC2 t CH2 CLK ADDRESS (3) INTERNAL ADDRESS t t SCLD HCLD CNTLD CNTINC DATA IN WRITE EXTERNAL ADDRESS t ...

Page 18

IDT70V5388/78 3.3V 64/32K x 18 Synchronous FourPort™ Static RAM CLK t RS MRST t ROF ALL ADDRESS/ DATA LINES ALL OTHER INPUTS CNTINT INT NOTES: 1. Master Reset will reset the device. For JTAG and MBIST reset please refer to ...

Page 19

IDT70V5388/78 3.3V 64/32K x 18 Synchronous FourPort™ Static RAM t CYC2 t t CH2 CL2 CLK SCLD HCLD CNTLD CNTINC t SCINC CNTRD INTERNAL ADDRESS DATA OUT ...

Page 20

IDT70V5388/78 3.3V 64/32K x 18 Synchronous FourPort™ Static RAM t CYC2 t CH2 CLK EXTERNAL 007Fh xx7Dh ADDRESS t t HMLD SMLD MKLD t SCLD CNTLD CNTINC COUNTER A INTERNAL ADDRESS (2 ) CNTINT t CYC2 t CH2 CLK P1 ...

Page 21

IDT70V5388/78 3.3V 64/32K x 18 Synchronous FourPort™ Static RAM The IDT70V5388/78 provides a true synchronous FourPort Static RAM interface. Registered inputs provide minimal set-up and hold times on address, data, and all critical control inputs. All internal registers are clocked ...

Page 22

IDT70V5388/78 3.3V 64/32K x 18 Synchronous FourPort™ Static RAM The IDT70V5388/78 supports mailbox interrupts, facilitating communication among the devices attached to each port. If the user chooses the interrupt function, then each of the upper four address locations in the ...

Page 23

IDT70V5388/78 3.3V 64/32K x 18 Synchronous FourPort™ Static RAM Each port on the IDT70V5388/78 is equipped with an internal address counter, to ease the process of bursting data into or out of the device. Truth Table II depicts the specific ...

Page 24

IDT70V5388/78 3.3V 64/32K x 18 Synchronous FourPort™ Static RAM Load Counter-Mask STEP 1 Register = FF Load Address STEP 2 Counter = FD Max Address STEP 3 Register Max + 1 STEP 4 Address Register NOTE: 1. The "X's" in ...

Page 25

IDT70V5388/78 3.3V 64/32K x 18 Synchronous FourPort™ Static RAM in increments of four: masking bits 2, 1, and 0 configures that port to count in increments of eight, and so on. The ability to set the increments by which the ...

Page 26

IDT70V5388/78 3.3V 64/32K x 18 Synchronous FourPort™ Static RAM MBIST Mode Select Register (MSR) TDI CONTROLLER CLKMBIST Bypass Register (BYR Instruction Register (IR MBIST Result Register (MRR ...

Page 27

IDT70V5388/78 3.3V 64/32K x 18 Synchronous FourPort™ Static RAM TCK (1) Device Inputs / TDI/TMS (2) Device Outputs / TDO TRST t JRST NOTES: 1. Device inputs = All device inputs except TDI, TMS, and TRST. 2. Device outputs = ...

Page 28

IDT70V5388/78 3.3V 64/32K x 18 Synchronous FourPort™ Static RAM Instruction Field Revision Number (31:28) IDT Device ID (27:12) IDT JEDEC ID (11:1) ID Register Indicator Bit (Bit 0) NOTE: 1. Device ID for IDT70V5378 is 0x31E. Register Nam e Instructio ...

Page 29

... Preliminary datasheets contain descriptions for products that are in early release. 08/20/02: Initial Public Datashee 09/25/02: Added 0.5M Density to Datasheet CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 The IDT logo is a registered trademark of Integrated Device Technology, Inc Package Process/ Temperature Range Blank ...

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