TTSI4K32T3BAL Agere Systems, TTSI4K32T3BAL Datasheet
TTSI4K32T3BAL
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Data Sheet June 2000 4096-Channel, 32-Highway Time-Slot Interchanger Features Thirty-two full-duplex, serial time-division multi- plexed (TDM) highways. Full availability, nonblocking 4096-channel time/ space switch. 2.048 Mbits/s (32 time slots), 4.096 Mbits/s (64 time slots), or 8.192 Mbits/s (128 time slots) ...
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TTSI4K32T 4096-Channel, 32-Highway Time-Slot Interchanger Contents Features .................................................................................................................................................................. 1 Applications ............................................................................................................................................................. 1 Description............................................................................................................................................................... 1 Functional Description ............................................................................................................................................. 5 Pin Information ........................................................................................................................................................ 7 Typical TSI Application .......................................................................................................................................... 15 Interchange Fabric................................................................................................................................................. 16 Small and Large TSIs ............................................................................................................................................ 17 Microprocessor Interface ....................................................................................................................................... 18 ...
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Data Sheet June 2000 Figures Figure 1. Block Diagram of the TTSI4K32T .............................................................................................................6 Figure 2. 217-Pin PBGA (Bottom View) ...................................................................................................................7 Figure 3. A Typical TSI Application ........................................................................................................................15 Figure Time-Slot Switch Made from 4K TSIs ..........................................................................................17 Figure 5. ...
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TTSI4K32T 4096-Channel, 32-Highway Time-Slot Interchanger Tables Table 1. Data Rate and Switch Size Examples ....................................................................................................... 5 Table 2. Pin Assignments for a 217-Pin PBGA—Pin Number Order ...................................................................... 8 Table 3. Pin Assignments for a 217-Pin PBGA—Signal Name Order................................................................... 10 Table ...
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Data Sheet June 2000 Functional Description The TTSI4K32T is a 4096 time-slot switch that can be used in a variety of ways, with some or all of the highways active and running at different data rates. The table below lists ...
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TTSI4K32T 4096-Channel, 32-Highway Time-Slot Interchanger Functional Description (continued) The device capabilities include several test features for board and device diagnostics. Test-pattern checking on input time slots (PRBS, QRSS fixed byte). Test-pattern generation on output time slots (PRBS, QRSS, ...
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Data Sheet June 2000 Pin Information The TTSI4K32T is available in a 217-pin PBGA with 1.27 mm (50 mil) pin pitch ...
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TTSI4K32T 4096-Channel, 32-Highway Time-Slot Interchanger Pin Information (continued) Table 2. Pin Assignments for a 217-Pin PBGA—Pin Number Order Pin Signal Name Pin TXOE1 C8 A5 TXD18 C9 A6 TXD2 C10 ...
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Data Sheet June 2000 Pin Information (continued) Table 2. Pin Assignments for a 217-Pin PBGA—Pin Number Order (continued) Pin Signal Name Pin T10 P7 TXD30 T11 P8 V T12 DD ...
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TTSI4K32T 4096-Channel, 32-Highway Time-Slot Interchanger Pin Information (continued) Table 3. Pin Assignments for a 217-Pin PBGA—Signal Name Order Signal Name Pin Signal Name ...
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Data Sheet June 2000 Pin Information (continued) Table 3. Pin Assignments for a 217-Pin PBGA—Signal Name Order (continued) Signal Name Pin Signal Name TXOE23 D13 V SS TXOE24 G16 V SS TXOE25 M14 V SS TXOE26 G15 V SS TXOE27 ...
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TTSI4K32T 4096-Channel, 32-Highway Time-Slot Interchanger Pin Information (continued) Table 4. TTSI4K32T Pin Descriptions Symbol Type* RESET I Reset (Active-Low). A low on this pin resets the TTSI4K32T asynchronous to any other clock or input signal. All flip-flops will ...
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Data Sheet June 2000 Pin Information (continued) Table 4. TTSI4K32T Pin Descriptions (continued) Symbol Type* D[7—0] I/O Host Processor Data Bus. These pins provide an 8-bit, bidirectional data bus. Read data is valid for one PCLK cycle coincident with the ...
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TTSI4K32T 4096-Channel, 32-Highway Time-Slot Interchanger Pin Information (continued) Table 4. TTSI4K32T Pin Descriptions (continued) Symbol Type* TXOE[0—31] O Transmit Output Enables 0—31. These output pins reflect the active/high-imped- ance status for the corresponding transmit highways. They are continuously driven to ...
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Data Sheet June 2000 Typical TSI Application T1/E1 LIU AND FRAMER ICs T7630/T7633 T1/E1 T1/E1 LIUs FRAMERS T1/E1 LINES T7698 T7230A T7693 TFRA08C13 MICROPROCESSOR A typical application that requires a TSI is where TDM highways that are carrying different types ...
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TTSI4K32T 4096-Channel, 32-Highway Time-Slot Interchanger Interchange Fabric The time-slot interchanger core has a memory-based architecture. The received time slots are converted from serial to parallel by the receive highways block and stored in an internal dual-ported memory called the data ...
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Data Sheet June 2000 Small and Large TSIs The TTSI4K32T is one in a family of time-slot interchanger (TSI) devices offered by Lucent Technologies Micro- electronics Group. This family of devices are all software compatible since they all have similar ...
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TTSI4K32T 4096-Channel, 32-Highway Time-Slot Interchanger Microprocessor Interface The host interface is designed to connect directly to a typical synchronous or asynchronous host bus. The interface to the TTSI4K32T includes a separate clock, PCLK, which is used only in the synchronous ...
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Data Sheet June 2000 Microprocessor Interface Synchronous Mode ( The following two timing diagrams show read and write in the synchronous mode. PCLK D[7—0] A[14— R/W HIGH IMPEDANCE DT PCLK D[7—0] A[14— R/W HIGH ...
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TTSI4K32T 4096-Channel, 32-Highway Time-Slot Interchanger Mixed-Highway Data Rates Each receive (Rx) highway can be selected to sample at a rate of either 2.048 Mbits/s, 4.096 Mbits/s, or 8.192 Mbits/s. This rate selection is made via the HDR[1—0] field in the ...
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Data Sheet June 2000 TDM Highway Interface Timing Virtual and Physical Frames Figure 10 below shows a virtual frame offset from the physical frame. The FSYNC pulse marks the beginning of the physical frame, but the TSI can be programmed ...
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TTSI4K32T 4096-Channel, 32-Highway Time-Slot Interchanger TDM Highway Interface Timing TDM Highway Alignment at Zero Offset The TDM highway interface logic is designed to make interconnection to the TTSI4K32T as simple as possible. Consider the timing diagram shown in Figure 11 ...
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Data Sheet June 2000 TDM Highway Offsets (continued) One can also see that bit 0 of the transmit time slot 0 is driven four CK cycles after FSYNC is sampled active. Since CK is set for 8.192 MHz and TXD0 ...
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TTSI4K32T 4096-Channel, 32-Highway Time-Slot Interchanger Low-Latency and Frame-Integrity Modes Transmit time slots can be selected for low-latency (minimum delay) or for frame-integrity modes using the connec- tion store memory. Low Latency Low latency causes a received time slot to be ...
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Data Sheet June 2000 Low-Latency and Frame-Integrity Modes Low Latency (continued) For example, consider any Rx highway running at 4.096 Mbits/s using time slot 5 to receive data, with an Rx high- way offset of 3 time slots ...
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TTSI4K32T 4096-Channel, 32-Highway Time-Slot Interchanger Low-Latency and Frame-Integrity Modes Frame Integrity (continued) The range of Rx and Tx offsets can be independently selected from (125 – configuration registers, bytes 0 and 1, where set) can therefore take ...
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Data Sheet June 2000 Low-Latency and Frame-Integrity Modes Frame Integrity (continued) In the example shown below in Figure 13, a receive and transmit highway are both running at 2.048 Mbits/s. There are 32 time slots for each 125 s frame. ...
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TTSI4K32T 4096-Channel, 32-Highway Time-Slot Interchanger Test-Pattern Generation Test-pattern generation involves selecting outgoing time slots on a particular transmit highway for use in transmit- ting one of 15 patterns of data. The patterns available are selected using TPS[3—0] (bits 7—4) of ...
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Data Sheet June 2000 Test-Pattern Checking (continued) 2. Set the Test-Pattern Checker Upper Time-Slot Register (0x0C), Table 25 on page 44 and the Test-Pattern Checker Lower Time-Slot Register (0x0D), Table 26 on page 44 to indicate the range of input ...
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TTSI4K32T 4096-Channel, 32-Highway Time-Slot Interchanger JTAG Boundary-Scan Specification Principle of the Boundary Scan The boundary scan (BS test aid for chip, module, and system testing. The key aspects of BS are as follows: 1. Testing the connections between ...
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Data Sheet June 2000 JTAG Boundary-Scan Specification Test Access Port Controller The test access port controller is a synchronous sequence controller with 16 states. The state changes are preset by the TMS, TCK, and TRST signals and by the previous ...
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TTSI4K32T 4096-Channel, 32-Highway Time-Slot Interchanger JTAG Boundary-Scan Specification Test Access Port Controller Table 9. TAP Controller States in the Data Register Branch Name TEST LOGIC RESET The BS logic is switched in such a way that normal operation of the ...
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Data Sheet June 2000 JTAG Boundary-Scan Specification Instruction Register The instruction register (IR bits in length. Table 11 shows the BS instructions implemented by the TTSI4K32T. Table 11. TTSI4K32T’s Boundary-Scan Instructions Instruction Code EXTEST 0000 IDCODE 0001 HIGHZ ...
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TTSI4K32T 4096-Channel, 32-Highway Time-Slot Interchanger JTAG Boundary-Scan Specification Instruction Register (continued) BYPASS: This instruction selects the BYPASS register. A minimal shift path exists between TDI and TDO. The BYPASS reg- ister is selected after the UPDATE IR. The BS register ...
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Data Sheet June 2000 Register Architecture Table overview of the register architecture. The table is a summary of the register function and address. Complete detail of each register is given in the following sections. Table 12. TTSI4K32T ...
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TTSI4K32T 4096-Channel, 32-Highway Time-Slot Interchanger Register Architecture (continued) Table 12. TTSI4K32T Register Summary (continued) Register Name/Function Test-Pattern Error Injection Register Test-Pattern Checker Data Register Test-Pattern Checker Lower Time-Slot Register Test-Pattern Checker Upper Time-Slot Register Test-Pattern Checker Highway Register Test-Pattern Style ...
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Data Sheet June 2000 Configuration Register Architecture Note: All registers’ bits default to 0 upon reset, unless noted otherwise. All TDM highway data, which is stored in the TSI, will have the following convention. Bit 7 is first transmitted and ...
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TTSI4K32T 4096-Channel, 32-Highway Time-Slot Interchanger Configuration Register Architecture Table 14. Software Reset Register (0x01) Bit Symbol 7—1 — Table 15. BIST Command Register (0x02) Bit Symbol BPF 4—0 — The BIST test sequence ...
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Data Sheet June 2000 Configuration Register Architecture Table 16. Idle Code 1 Register (0x03) Bit Symbol 7—0 IC1 Table 17. Idle Code 2 Register (0x04) Bit Symbol 7—0 IC2 Table 18. Idle Code 3 Register (0x05) Bit Symbol 7—0 IC3 ...
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TTSI4K32T 4096-Channel, 32-Highway Time-Slot Interchanger Configuration Register Architecture Table 20. Interrupt Status Register* (0x07) Bit Symbol 7 — Reserved. Read FSERR Frame Sync Error. When set to 1, this bit indicates that an error related to frame ...
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Data Sheet June 2000 Configuration Register Architecture Table 21. Interrupt Mask Register (0x08) Bit Symbol 7 — Reserved. Read MASKFS Mask Frame Sync Error Interrupt. Set this bit mask the generation of an ...
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TTSI4K32T 4096-Channel, 32-Highway Time-Slot Interchanger Configuration Register Architecture Table 22. Test Command Register (0x09) Bit Symbol 7 STTPG 6 STTPC 5—4 GENHDR [1—0] 3—2 CHKHDR [1—0] 1—0 — 42 (continued) Name/Description Start Test-Pattern Generator. Writing this register ...
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Data Sheet June 2000 Configuration Register Architecture Table 23. Test-Pattern Style Register (0x0A) Bit Symbol 7—4 TPS[3—0] Generator Test-Pattern Style[3—0]. These 4 bits determine the type of test pattern that will be generated by the on-line maintenance test-pattern generator. TPS3 ...
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TTSI4K32T 4096-Channel, 32-Highway Time-Slot Interchanger Configuration Register Architecture Table 24. Test-Pattern Checker Highway Register (0x0B) Bit Symbol 7—5 — 4—0 CHS[4—0] Table 25. Test-Pattern Checker Upper Time-Slot Register (0x0C) Bit Symbol 7 — 6—0 CKRUP[6—0] Checker Upper Time-Slot Select[6—0]. These ...
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Data Sheet June 2000 Configuration Register Architecture Table 29. Test-Pattern Error Counter (Byte 0) (0x10)* Bit Symbol 7—0 EC[7—0] * Read-only register. Table 30. Test-Pattern Error Counter (Byte 1) (0x11)* Bit Symbol 7—0 EC[15—8] * Read-only register. Note: The error ...
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TTSI4K32T 4096-Channel, 32-Highway Time-Slot Interchanger Configuration Register Architecture Table 33. Transmit Highway Configuration Register (Byte 0) (0x1000 + 4i)* Bit Symbol 7 — 6—4 XBITOFF [2—0] 3—2 XFBOFF [1—0] 1—0 — the transmit highway number. 46 (continued) ...
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Data Sheet June 2000 Configuration Register Architecture Table 34. Transmit Highway Configuration Register (Byte 1) (0x1001 + 4i)* Bit Symbol 7 — 6—0 XTSOFF [6— the transmit highway number. Table 35. Transmit Highway Configuration Register (Byte 2) ...
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TTSI4K32T 4096-Channel, 32-Highway Time-Slot Interchanger Configuration Register Architecture Table 36. Receive Highway Configuration Register (Byte 0) (0x1800 + 4i)* Bit Symbol 7 — 6—4 RBITOFF [2—0] 3—2 RFBOFF [1—0] 1—0 — the receive highway number. 48 (continued) ...
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Data Sheet June 2000 Configuration Register Architecture Table 37. Receive Highway Configuration Register (Byte 1) (0x1801 + 4i)* Bit Symbol 7 — 6—0 RTSOFF [6— the receive highway number. Table 38. Receive Highway Configuration Register (Byte 2) ...
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TTSI4K32T 4096-Channel, 32-Highway Time-Slot Interchanger Configuration Register Architecture Transmit Highway 3-State Options There are several ways of 3-stating the transmit highways: TEST (active-low) is the input pin that 3-states all outputs and bidirectional pins of the device. GXE (bit 0) ...
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Data Sheet June 2000 Data Store Memory Microprocessor access to the incoming highway data is provided by directly reading the data store memory. Each one of the time slots is addressable by constructing the address in the following way address ...
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TTSI4K32T 4096-Channel, 32-Highway Time-Slot Interchanger Connection Store Memory Table 42. Connection Store Memory (Byte 0) Bit Symbol 7—0 RTSA[6—0]/ HSD[7—0] Table 43. Connection Store Memory (Byte 1) Bit Symbol 7—5 TSDSM[2—0] Time-Slot Data Select Mode[2—0] 4—0 RXHWY [4—0] To illustrate ...
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Data Sheet June 2000 Connection Store Memory TSDSM[5—0] (bits 7—5) of byte 1 of the connection store select the source of data for each of the time slots being transmitted by the TTSI4K32T. The configuration can be divided into three ...
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TTSI4K32T 4096-Channel, 32-Highway Time-Slot Interchanger Absolute Maximum Ratings Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso- lute stress ratings only. Functional operation of the device is not implied at these ...
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Data Sheet June 2000 Electrical Characteristics T = – Parameter Input Leakage Current: Non-pull-up Pins Pull-up Pins Non-pull-up I/O Pins Pull-down Pins Output Voltage: Low: DT, D[7—0] TXD[31—0], TXOE[31—0] TDO, ...
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TTSI4K32T 4096-Channel, 32-Highway Time-Slot Interchanger Timing Characteristics (continued) A[14—0] R HIGH IMPEDANCE DT D[7—0] Figure 16. Asynchronous Read Cycle Timing Using DT Handshake A[14—0] R HIGH IMPEDANCE DT D[7—0] Figure 17. ...
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Data Sheet June 2000 Timing Characteristics (continued) MM A[14— R/W D[7—0] Figure 18. Asynchronous Read Cycle Timing Using Only CS MM A[14— R/W D[7—0] Figure 19. Asynchronous Write Cycle Timing Using Only CS Table ...
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TTSI4K32T 4096-Channel, 32-Highway Time-Slot Interchanger Timing Characteristics (continued) PCLK CS t15 AS t17 R/W t22 DT t19 D[7—0] A[14—0] PCLK CS t15 AS t17 R/W DT t19 D[7—0] A[14—0] 58 t15 t18 READ ADDRESS Figure 20. Synchronous Read Cycle Timing ...
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Data Sheet June 2000 Timing Characteristics (continued) Table 47. Synchronous Microprocessor Interface Timing Symbol t15 CS Setup to Rising PCLK Edge t16 CS Hold from Rising PCLK Edge t17 AS Setup to Rising PCLK Edge t18 AS Hold from Rising ...
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TTSI4K32T 4096-Channel, 32-Highway Time-Slot Interchanger Timing Characteristics (continued) TDM highway timing is shown below for the following scenario ( 31 31): The input CK speed ...
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Data Sheet June 2000 Timing Characteristics (continued) TCK TMS TDI TDO Table 49. JTAG Interface Timing Symbol t31 TDI, TMS Setup to Rising TCK Edge t32 TDI, TMS Hold from Rising TCK Edge t33 TDO Delay from Falling TCK Edge ...
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TTSI4K32T 4096-Channel, 32-Highway Time-Slot Interchanger Outline Diagram 217-Pin PBGA Dimensions are in millimeters. A1 BALL IDENTIFIER ZONE MOLD COMPOUND PWB 0.36 ± 0.04 0.60 ± 0. ...
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... Data Sheet June 2000 Ordering Information Device Code TTSI4K32T3BAL DS99-178PDH Replaces DS98-291TIC to Incorporate the Following Updates 1. Page 8, Pin D17, added overline to show active-low (TRST). 2. Page 8, removed duplicate E1, E2, E3, E4, E14, E15, E16, and E17 pins. 3. Page 21, updated Figure 10, Virtual and Physical Frames on page 21. ...
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Time-Slot Interchanger For additional information, contact your Microelectronics Group Account Manager or the following: INTERNET: http://www.lucent.com/micro E-MAIL: docmaster@micro.lucent.com N. AMERICA: Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-2386 1-800-372-2447, FAX 610-712-4106 (In CANADA: ...