CXA3086Q Sony, CXA3086Q Datasheet
CXA3086Q
Specifications of CXA3086Q
Related parts for CXA3086Q
CXA3086Q Summary of contents
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... Flash A/D Converter For the availability of this product, please contact the sales office. Description The CXA3086Q is an 6-bit high-speed flash A/D converter capable of digitizing analog signals at the maximum rate of 140MSPS. ECL, PECL or TTL can be selected as the digital input level in accordance with the application ...
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... DGND3 – 1.05 DGND3 – 0.5 V DGND3 – 3.2 DGND3 – 1.4 V DGND3 – 0.5 DGND3 – 1.4 2.0 0 DGND1 0.4 0.8 100 140 +75 –20 DGND3 V (max (DGND3 – 1.2V (min.) IL CXA3086Q Max. +5.25 V +0.05 V +0.05 V –4. +4.1 V +2 MSPS MSPS +75 °C ...
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... RBS 27 CLK/T CLK/E 25 CLKN RESETN/T 12 RESETN/E 11 RESET AGND INV 6bit 6bit 6bit Delay D Q Select SELECT DGND1 – 3 – DGND3 (MSB) 35 P1D5 34 P1D4 33 P1D3 32 P1D2 31 P1D1 30 P1D0 (LSB) (MSB) 7 P2D5 6 P2D4 6bit 5 P2D3 4 P2D2 3 P2D1 2 P2D0 (LSB CLKOUT DGND2 CXA3086Q ...
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... DGND3 – 4 – CXA3086Q Description Analog ground. Separated from the digital ground. Analog power supply. Separated from the digital power supply. Digital ground. Digital power supply. Digital power supply. Ground for ECL input. +5V for PECL and TTL input. Digital power supply. ...
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... Comparator – 5 – CXA3086Q Description Clock input. Reset input. When left open, this input goes to high level. When the input is set to low level, the built-in CLK frequency divider circuit can be reset. Data output polarity inversion input. When left open, this input goes to high level ...
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... Symbol I/O voltage level No P1D0 P1D5 2 P2D0 TTL 7 P2D5 43 CLKOUT O Equivalent circuit Comparator Vref 19 AGND CC2 DGND2 D 3 DGND1 VEE – 6 – CXA3086Q Description Analog input. Port 1 side data output. 7 Port 2 side data output. Clock output. (See Table 2. Operating Mode Table.) ...
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... DGND3 – 1.4 DGND3 – 1.2 –50 +50 –75 2.0 0.8 1.5 –50 –500 2.4 0.5 –15 70 140 10 3 4.5 2.9 2.9 3 5pF) 4 5pF 5pF) 6 5pF 5pF) 2 CXA3086Q Unit bits LSB LSB pF kΩ µA Ω mA Ω Ω µA 0 µ µA 0 µ µA MSPS ...
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... RB 2 – · · · : · · · · Iref – 8 – Min. Typ. Max. 200 37.0 34.5 – 54.0 67.5 90 0.4 0.6 0.8 290 360 470 2.0 8 1LSB RTS V IN CXA3086Q Unit MHz TPS –9 TPS –9 TSP Iref RBS RB ...
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... Taj is: ∆ 64 Taj = / = / ( ∆ Comparator B A > B Counter CXA3086Q 6 Logic Analizer 1024 samples (LSB) Pulse ...
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... Description of Operating Modes The CXA3086Q has two types of operating modes which are selected with Pin 41 (SELECT). Operating Maximum SELECT mode conversion rate DMUX mode V 140MSPS CC Straight mode GND 100MSPS 1. DMUX mode (See Application Circuits (1), (2) and (3).) Set the SELECT pin to Vcc for this mode. In this mode, the clock frequency is divided the IC, and the data is output after being demultiplexed by this 1/2 frequency divided clock ...
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... The A/D converter can operate at Fc (min.) = 100MSPS in this mode. Digital input level and supply voltage settings The logic input level for the CXA3086Q supports ECL, PECL and TTL levels. The power supplies (DV 3, DGND3) for the logic input block must be set to match the logic input (CLK and EE RESET signals) level ...
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... P2D0 to P2D5 Latch 6 bit Digital Data +5V (D) DG +5V (D) DG +5V (D) 6 bit Digital Data P1D0 to P1D5 Latch 6 bit Digital Data 6 bit Digital Data P2D0 to P2D5 Latch 6 bit Digital Data +5V (D) DG +5V (D) DG +5V (D) 6 bit Digital Data P1D0 to P1D5 Latch 6 bit Digital Data CXA3086Q ...
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... Data ECL TTL +5V ( P1D0 to P1D5 bit Digital +5V (D) Data PECL TTL +5V ( P1D0 to P1D5 bit Digital +5V (D) – 13 – +5V (D) DG +5V ( +5V (D) 6 bit Digital Data Latch +5V (D) DG +5V ( +5V (D) 6 bit Digital Data Latch +5V (D) DG +5V ( +5V (D) 6 bit Digital Data Latch Data CXA3086Q ...
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... Analog +5V input ( short – 14 – 1µF 10µ RBS short RESETN/E 12 RESET RESETN DGND2 7 P2D5 6 P2D4 5 P2D3 P2D2 4 3 P2D1 2 P2D0 DGND2 CXA3086Q (MSB) P2D5 P2D4 P2D3 P2D2 P2D1 (LSB) P2D0 ...
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... CLK OUT T_rh T_rs T_rh RESET signal ) Td_clk; 7ns (typ.) 8ns (max.) 4.5ns (min.) 2.0V 2.0V (Reset period) 0.8V 0.8V 4.5ns (min.) 8ns (max.) T_rs Td_clk – 15 – CXA3086Q Tdo2; 8ns (typ.) 6.5ns (min.) 10ns (max.) 2. 0. Tdo1 T + 1ns (typ.) 2.0V 0. ...
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... Td_clk; 7ns (typ.) CLK OUT (CLK is inverted and output.) RESET signal N – 1 Tds N T Tpw1 Tpw0 6.5ns (min.) 10ns (max.) 2.0V N – – 3 0.8V 2.0V N – – 4 0.8V 4.5ns (min.) 8ns (max.) 2.0V 0.8V – 16 – – – – – 2 CXA3086Q – 1 ...
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... P2D/out CLK OUT 6bit P1D/out 6bit P2D/out CLK OUT 6bit P1D/out 6bit P2D/out CLK OUT 7ns ( = 1/140MSPS) Td_clk (min.) 5.0ns <4.5ns> Td_clk (max.) 7.5ns <8.0ns> Tdo2 (min.) 7.0ns <6.5ns> Tdo2 (min.) 9.5ns <10ns> – 17 – CXA3086Q th (min.) ts (min.) 2.5ns 6.5ns 14ns ...
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... Notes on Operation • The CXA3086Q is a high-speed A/D converter which is capable of TTL, ECL and PECL level clock input. Characteristic impedance should be properly matched to ensure optimum performance during high-speed operation. • The power supply and grounding have a profound influence on converter performance. The power supply and grounding method are particularly important during high-speed operation ...
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... Analog input current vs. Analog input voltage characteristics 100 Analog input voltage [ –25 – 19 – Current consumption vs. Conversion rate characteristics f CLK fin = – 1kHz 4 DMUX mode C = 5pF 140 Fc – Conversion rate [MSPS] Reference current vs. Ambient temperature characteristics 25 Ta – Ambient temperature [°C] CXA3086Q 75 ...
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... Error rate: 10 170 160 150 140 – – Ambient temperature [°C] Error rate vs. Conversion rate characteristics –6 10 fin = –7 10 Error > 4LSB –8 10 –9 10 – 100 140 TPS 75 – 20 – CXA3086Q f CLK – 1kHz 4 160 180 200 Fc – Conversion rate [MSPS] ...
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... The CXA3086Q Evaluation Board is a special board designed to maximize and facilitate the evaluation performance of the CXA3086Q. After latching the CXA3086Q output data with a frequency divided clock, the analog signal can be regenerated by a 10-bit high-speed D/A converter. The latched data can also be extracted externally via a 24-pin cable connector ...
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... CXA3086Q ...
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... DIR.IN 7. S2: Setting junction for the clock frequency division ratio. The operating speed after latching is determined by the frequency division ratio set here. When set to CLK OUT, it operates according to the CXA3086Q clock output. 8. SW1 SELECT: CXA3086Q output mode selector switch. 9. SW2 A/D INV: CXA3086Q output polarity inversion switch ...
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... CON2 (DIR.IN) pin with AC coupling. In these cases, the input dynamic range is not limited, but the V level may be limited by IC3: NJM3403A the evaluation board of the CXA3086Q, CLC404 (Comlinear) is employed for IC2 to drive the analog input signal. Though, CLC505 (Comlinear) can also be used instead of CLC404, there should be a little change in the peripheral circuit in this case. ...
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... CXA3086Q Evaluation Board Timing Chart N CON2 DIR IN CON3 1Vp-p CLK IN CXA3086Q CLK (PECL) CXA3086Q N – side DATA (TTL) Approximately 6.0ns CON8 P1 side DATA CLK (TTL) CON8 P1 side DATA N – 6 DATA (TTL) N – 6 CON5 P1 side OUT (Analog regeneration waveform) Operating Conditions CXA3086Q operating mode ...
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... IC4C DGND C23 0.1µF 13 CLK R25 130 R28 82 R26 130 R29 82 10H136 (PECL R27 130 R30 DGND CXA3086Q DAINV PS ADINV SELECT P2D5 P2D4 P2D3 P2D2 P2D1 P2D0 DGND DGND C28 0.1µ DGND1 46 DGND C25 0.1µF N. CLKOUT CLKOUT 43 ...
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... C46 NC 620 0.1µ DGND 17 13 INV 16 CLKN DGND 14 CLK R46 620 CON8 P1 side DATA 25 26 CXA3086Q AGND C51 R42 R43 0.1µF 1k 270 TL431CP C52 C11 AV 0.1µF 1µF EE CON4 AGND P2 side OUT AGND DGND C53 0.1µ AGND C54 ...
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... R13, 23 33, 37, 38 R14 27 36, 39, 40 FRD-25SR (0.25W) 130Ω R15, 16, 43, 45 R17 R20, 22, 42, 44 R21 R41, 46 Component side silk diagram – 28 – CXA3086Q Product name Function RJ-5W-1K 1kΩ volume resistor RJ-5W-2K 2kΩ volume resistor RJ-5W-10K 10kΩ volume resistor RGLD4X621J 620Ω ...
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... Component side pattern diagram Solder side pattern diagram – 29 – CXA3086Q ...
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... M PACKAGE STRUCTURE PACKAGE MATERIAL LEAD TREATMENT QFP-48P-L04 LEAD MATERIAL QFP048-P-1212-B PACKAGE WEIGHT – 30 – CXA3086Q + 0.1 0.15 – 0.05 0.15 + 0.2 0.1 – 0.1 + 0.35 2.2 – 0.15 EPOXY RESIN SOLDER / PALLADIUM PLATING COPPER / 42 ALLOY ...