MC100EP196

Manufacturer Part NumberMC100EP196
Description3.3V ECL Programmable Delay Chip with FTUNE
ManufacturerON Semiconductor
MC100EP196 datasheet
 


1
Page 1
2
Page 2
3
Page 3
4
Page 4
5
Page 5
6
Page 6
7
Page 7
8
Page 8
9
Page 9
10
Page 10
11
12
13
14
15
16
17
18
19
20
Page 1/20

Download datasheet (205Kb)Embed
Next
( DataSheet : www.DataSheet4U.com )
MC100EP196
3.3V ECL Programmable
Delay Chip with FTUNE
The MC100EP196 is a programmable delay chip (PDC) designed
primarily for clock deskewing and timing adjustment. It provides variable
delay of a differential NECL/PECL input transition. It has similar
architecture to the EP195 with the added feature of further tuneability in
delay using the FTUNE pin. The FTUNE input takes an analog voltage
from V
to V
to fine tune the output delay from 0 to 60 ps.
CC
EE
The delay section consists of a programmable matrix of gates and
multiplexers as shown in the logic diagram, Figure 2. The delay increment
of the EP196 has a digitally selectable resolution of about 10 ps and a net
range of up to 10.2 ns. The required delay is selected by the 10 data select
inputs D[9:0] values and controlled by the LEN (pin 10). A LOW level on
LEN allows a transparent LOAD mode of real time delay values by
D[9:0]. A LOW to HIGH transition on LEN will LOCK and HOLD
current values present against any subsequent changes in D[10:0]. The
approximate delay values for varying tap numbers correlating to D0 (LSB)
through D9 (MSB) are shown in Table 5.
Because the EP196 is designed using a chain of multiplexers, it has a
fixed minimum delay of 2.4 ns. An additional pin, D10, is provided for
controlling Pins 14 and 15, CASCADE and CASCADE, also latched
by LEN, in cascading multiple PDCs for increased programmable
range. The cascade logic allows full control of multiple PDCs.
Switching devices from all “1” states on D[0:9] with SETMAX LOW
to all “0” states on D[0:9] with SETMAX HIGH will increase the
delay equivalent to “D0”, the minimum increment.
Select input pins, D[10:0], may be threshold controlled by
combinations of interconnects between V
for LVCMOS, ECL, or LVTTL level signals. LVTTL and LVCMOS
operation is available in PECL mode only. For LVCMOS input levels,
leave V
and V
open. For ECL operation, short V
CF
EF
(pins 7 and 8). For LVTTL level operation, connect a 1.5 V supply
reference to V
and leave open V
CF
to V
pin can be accomplished by placing a 2.2 kW resistor between
CF
V
and V
for 3.3 V power supply.
CF
EE
The V
pin, an internally generated voltage supply, is available to
BB
this device only. For single−ended input conditions, the unused
differential input is connected to V
V
may also rebias AC coupled inputs. When used, decouple V
BB
via a 0.01 mF capacitor and limit current sourcing or sinking
and V
CC
to 0.5 mA. When not used, V
The 100 Series contains temperature compensation.
Maximum Frequency > 1.2 GHz Typical
Programmable Range: 0 ns to 10 ns
Delay Range: 2.4 ns to 12.4 ns
10 ps Increments
PECL Mode Operating Range:
V
= 3.0 V to 3.6 V with V
CC
NECL Mode Operating Range:
V
= 0 V with V
= −3.0 V to −3.6 V
CC
EE
Semiconductor Components Industries, LLC,2004
October, 2004 − Rev. 10
www.DataSheet4U.com
(pin 7) and V
(pin 8)
EF
CF
and V
CF
EF
pin. The 1.5 V reference voltage
EF
as a switching reference voltage.
BB
BB
should be left open.
BB
Open Input Default State
Safety Clamp on Inputs
A Logic High on the EN Pin Will Force Q to Logic
Low
D[10:0] Can Accept Either ECL, LVCMOS, or LVTTL
Inputs
= 0 V
EE
V
BB
1
http://onsemi.com
MARKING
DIAGRAM*
MC100
EP196
AWLYYWW
LQFP−32
FA SUFFIX
32
CASE 873A
1
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
*For additional marking information, refer to
Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 17 of this data sheet.
Output Reference Voltage
Publication Order Number:
MC100EP196/D
www.DataSheet4U.com

MC100EP196 Summary of contents