MC68HC11KW1 Motorola, MC68HC11KW1 Datasheet
MC68HC11KW1
Specifications of MC68HC11KW1
Related parts for MC68HC11KW1
MC68HC11KW1 Summary of contents
Page 1
... HC11 MC68HC11KW1 TECHNICAL DATA MC68HC11KW1/D !MOTOROLA ...
Page 2
...
Page 3
... The Customer should ensure that it has the most up to date version of the document by contacting its local Motorola office. This document supersedes any earlier documentation relating to the products referred to herein. The information contained in this document is current at the date of publication. It may subsequently be updated, revised or withdrawn. MOTOROLA LTD., 1999 MC68HC11KW1 TPG ...
Page 4
Where abbreviations are used in the text, an explanation can be found in the glossary, at the back of this manual. Register and bit mnemonics are defined in the paragraphs describing them. An overbar is used to designate an active-low ...
Page 5
... Port A ...............................................................................................................2-6 2.11.2 Port B ...............................................................................................................2-8 2.11.3 Port C ...............................................................................................................2-8 2.11.4 Port D ...............................................................................................................2-8 2.11.5 Port E ...............................................................................................................2-9 2.11.6 Port F ...............................................................................................................2-9 2.11.7 Port G...............................................................................................................2-9 2.11.8 Port H ...............................................................................................................2-10 2.11.9 Port J................................................................................................................2-10 2.11.10 Port K ...............................................................................................................2-10 MC68HC11KW1 TITLE 1 INTRODUCTION 2 PIN DESCRIPTIONS TABLE OF CONTENTS Page Number TPG MOTOROLA i ...
Page 6
... Mapping allocations .........................................................................................4-3 4.2.1.1 RAM ...........................................................................................................4-4 4.2.1.2 Bootloader ROM ........................................................................................4-4 4.2.2 Registers..........................................................................................................4-4 4.3 System initialization ...............................................................................................4-10 4.3.1 Mode selection.................................................................................................4-10 4.3.1.1 HPRIO — Highest priority I-bit interrupt & misc. register ...........................4-11 MOTOROLA ii TITLE 3 CENTRAL PROCESSING UNIT 4 TABLE OF CONTENTS Page Number TPG MC68HC11KW1 ...
Page 7
... EEPROM row erase ...................................................................................4-43 4.6.1.4 EEPROM byte erase ..................................................................................4-44 4.6.2 CONFIG register programming ........................................................................4-44 4.6.3 RAM and EEPROM security ............................................................................4-45 5.1 Resets ...................................................................................................................5-1 5.1.1 Power-on reset .................................................................................................5-1 5.1.2 External reset (RESET) ...................................................................................5-2 MC68HC11KW1 TITLE 5 RESETS AND INTERRUPTS TABLE OF CONTENTS Page Number TPG MOTOROLA iii ...
Page 8
... DDRB — Data direction register for port B ......................................................6-3 6.3 Port C ....................................................................................................................6-4 6.3.1 PORTC — Port C data register........................................................................6-4 6.3.2 DDRC — Data direction register for port C......................................................6-4 6.4 Port D ....................................................................................................................6-5 6.4.1 PORTD — Port D data register........................................................................6-5 MOTOROLA iv TITLE 6 PARALLEL INPUT/OUTPUT TABLE OF CONTENTS Page Number TPG MC68HC11KW1 ...
Page 9
... SCSR1 — SCI status register 1.......................................................................7-10 7.6.5 SCSR2 — SCI status register 2.......................................................................7-11 7.6.6 SCDRH, SCDRL — SCI data high/low registers .............................................7-12 7.7 Status flags and interrupts.....................................................................................7-12 7.7.1 Receiver flags ..................................................................................................7-13 MC68HC11KW1 TITLE 7 TABLE OF CONTENTS Page Number TPG MOTOROLA v ...
Page 10
... F23FRC — Compare force register for Timers 2 and 3. ..................................9-18 9.2.4 T2C4 — Timer 2 channel 4 register.................................................................9-19 9.2.5 T2OC1–T2OC3 — Timer 2 output compare registers .....................................9-19 9.2.6 TCNT2 — Timer 2 counter register..................................................................9-20 MOTOROLA vi TITLE 8 9 TIMING SYSTEM TABLE OF CONTENTS Page Number TPG MC68HC11KW1 ...
Page 11
... Boundary cases ...............................................................................................9-44 ANALOG-TO-DIGITAL CONVERTER 10.1 Conversion process .............................................................................................10-2 10.2 Channel assignments ..........................................................................................10-2 10.3 Single channel operation .....................................................................................10-3 10.3.1 4-conversion, single scan...............................................................................10-4 10.3.2 4-conversion, continuous scan.......................................................................10-4 10.3.3 8-conversion, single scan...............................................................................10-4 MC68HC11KW1 TITLE 10 TABLE OF CONTENTS Page Number TPG MOTOROLA vii ...
Page 12
... EEPROM characteristics ...................................................................................... A-15 B.1 Packaging ............................................................................................................. B-1 C.1 EVS — Evaluation system.................................................................................... C-1 C.2 MMDS11 — Motorola modular development system ........................................... C-2 C.3 SPGMR11 — Serial peripheral system ................................................................ C-2 MOTOROLA viii TITLE A B MECHANICAL DATA C DEVELOPMENT SYSTEMS TABLE OF CONTENTS Page Number TPG MC68HC11KW1 ...
Page 13
... Oscillator connections ............................................................................................2-3 2-4 RAM stand-by connections.....................................................................................2-5 3-1 Programming model ...............................................................................................3-1 3-2 Stacking operations ................................................................................................3-3 4-1 MC68HC11KW1 memory map ...............................................................................4-3 4-2 RAM and register overlap.......................................................................................4-14 4-3 Memory map example of memory expansion.........................................................4-25 4-4 Schematic example of memory expansion .............................................................4-26 4-5 Memory map example of memory expansion ...
Page 14
... SPI master timing (CPHA = 1) ...............................................................................A-12 A-12 SPI slave timing (CPHA = 0) ..................................................................................A-13 A-13 SPI slave timing (CPHA = 1) ..................................................................................A-13 A-14 Expansion bus timing .............................................................................................A-15 B-1 100-pin TQFP .........................................................................................................B-1 B-2 100-pin TQFP mechanical dimensions...................................................................B-2 MOTOROLA xii TITLE LIST OF FIGURES Page Number TPG MC68HC11KW1 ...
Page 15
... Port configuration ...................................................................................................6-1 7-1 Example SCI baud rate control values ...................................................................7-7 8-1 SPI clock rates........................................................................................................8-7 9-1 Timer 1 resolution and capacity..............................................................................9-3 9-2 RTI periodic rates ...................................................................................................9-31 9-3 Pulse accumulator timing .......................................................................................9-34 MC68HC11KW1 LIST OF TABLES TITLE LIST OF TABLES Page Number TPG MOTOROLA xiii ...
Page 16
... Table Number 9-4 Clock A and clock B prescalers .............................................................................. 9-40 10-1 Channel assignments........................................................................................... 10-3 C-1 M68HC11 development tools ................................................................................ C-1 MOTOROLA xiv TITLE LIST OF TABLES Page Number TPG MC68HC11KW1 ...
Page 17
... INTRODUCTION The MC68HC11KW1 8-bit microcontroller is a member of the M68HC11 family of HCMOS microcontrollers. It has 640 bytes of EEPROM and 768 bytes of RAM. Making use of a 100-pin TQFP package, a non-multiplexed expanded bus is a feature of this device. The main timer system includes three input captures, four output compares and a software selectable input capture or output compare ...
Page 18
... Four 8-bit PWM timer channels • Available in 100-pin TQFP package 1.2 Mask option There is a single mask option on the MC68HC11KW1, which is programmed during manufacture and must be specified on the order form: • Security option (available/unavailable). See Section 4.6.3 MOTOROLA 1-2 ...
Page 19
... IRQ & RESET mode LIR/MODA select VSTBY/MODB XTAL EXTAL Oscillator R/W E XOUT 3 VDD VSS 3 Port B Figure 1-1 MC68HC11KW1 block diagram MC68HC11KW1 OC1/PAI Pulse accumulator OC1/OC2 OC1/OC3 Timer 2 Timer 1 OC1/OC4 IC4/OC1/OC5 Periodic interrupt COP watchdog Timer 3 SPI+ MOSI MISO SCI+ 10-channel, 10-bit ...
Page 20
... THIS PAGE LEFT BLANK INTENTIONALLY MOTOROLA 1-4 INTRODUCTION TPG MC68HC11KW1 ...
Page 21
... PIN DESCRIPTIONS The MC68HC11KW1 is available packaged in a 100-pin thin quad flat pack (TQFP), as shown in Figure 2-1. Most pins on this MCU serve two or more functions, as described in the following paragraphs. PK4/OC1 1 PK3/ECIN 2 PK2 3 PK1 4 PK0 5 PH0/PWM1 6 PH1/PWM2 7 PH2/PWM3 8 PH3/PWM4 9 PH4/CSIO 10 PH5/CSGP1 11 PH6/CSGP2 12 PH7/CSPROG ...
Page 22
... Figure 2-2 illustrates a typical reset circuit that includes an external switch together with a low voltage inhibit circuit, to prevent power transitions, or RAM or EEPROM corruption. Manual reset MOTOROLA 2 RESET MC34064 GND 4 4.7 k 1µF IN RESET MC34164 GND 3 Figure 2-2 External reset circuitry PIN DESCRIPTIONS M68HC11 RESET 1 MC68HC11KW1 TPG ...
Page 23
... In all cases, use caution when designing circuitry associated with the oscillator pins. (a) Common crystal connections (b) External oscillator M68HC11 connections EXTAL M68HC11 10 M XTAL (c) One crystal driving two MCUs Figure 2-3 Oscillator connections MC68HC11KW1 EXTAL 4•E M68HC11 10 M crystal XTAL EXTAL External oscillator XTAL 4• ...
Page 24
... Bypass capacitors should have good high-frequency characteristics and be as close to the MCU as possible. Bypassing requirements vary, depending on how heavily the MCU pins are loaded. The MC68HC11KW1 has four VDD pins and four VSS pins. One pair of these pins is reserved for supplying power to the analog-to-digital converter (VDDAD, VSSAD); the remaining pins are used for the internal logic, and to supply power to the port logic on either half of the chip ...
Page 25
... VDD power applied to the MCU. Reset must be driven low before V remain low until V has been restored to a valid level 4.8 V NiCd Figure 2-4 RAM stand-by connections MC68HC11KW1 and V is greater than one MOS threshold STBY DD rather than V . This allows RAM contents to be retained STBY DD 4 ...
Page 26
... Port signals The MC68HC11KW1 includes 80 pins that are arranged into ten 8-bit ports ( and K). All the port pins are bidirectional, except for PG7, PG6 and port E pins [7:0]; these are input only. Most of the bidirectional ports serve a purpose other than I/O, depending on the operating mode or peripheral function selected ...
Page 27
... PJ7 PJ6 PJ5 PJ4 PJ3 PJ[2,0] PK7 PK6 PK5 PK4 PK3 PK[2,0] MC68HC11KW1 Single chip and Expanded multiplexed and bootstrap mode special test mode PA7/PAI and/or OC1 PA6/OC2 and/or OC1 PA5/OC3 and/or OC1 PA4/OC4 and/or OC1 PA3/OC5/IC4 and/or OC1 PA2/IC1 PA1/IC2 ...
Page 28
... PORTD can be read at any time; inputs return the pin level and outputs return the pin driver input level. If PORTD is written, the data is stored in internal latches. The pins are driven only if port D is configured for general purpose output. MOTOROLA 2-8 PIN DESCRIPTIONS TPG MC68HC11KW1 ...
Page 29
... PORTG can be read at any time and always returns the pin level. If PORTG is written, the data is stored into an internal latch. The pin is driven only configured as an output. Pins [5:0] have on-chip pull-up devices that can be enabled or disabled via the port pull-up assignment register (PPAR). Refer to Section 6, Section 10 (A/D) and Section 4. MC68HC11KW1 PIN DESCRIPTIONS 2 TPG ...
Page 30
... Out of reset, port K pins [7:0] are general purpose high-impedance inputs. When the functions associated with these pins are disabled, the bits in DDRK govern the I/O state of the associated pin. For further information, refer to Section 6 and Section 9 (Timing system). MOTOROLA 2-10 PIN DESCRIPTIONS TPG MC68HC11KW1 ...
Page 31
... M68HC11 CPU registers are an integral part of the CPU and are not addressed as if they were memory locations. The seven registers are shown in Figure 3-1 and are discussed in the following paragraphs. 7 Accumulator Condition code register Figure 3-1 Programming model MC68HC11KW1 CENTRAL PROCESSING UNIT Accumulator B 0 Double accumulator D 0 Index register X 0 Index register Y ...
Page 32
... SP is decremented. Each time a byte is pulled from the stack, the SP is incremented. At any given time, the SP holds the 16-bit address of the next free location in the stack. Figure 3 summary of SP operations. MOTOROLA 3-2 CENTRAL PROCESSING UNIT TPG MC68HC11KW1 ...
Page 33
... High order byte of 16-bit extended address ll Low order byte of 16-bit extended address rr Signed relative offset ($80 to $7F (–128 to +127)); offset is relative to the address following the offset byte Figure 3-2 Stacking operations MC68HC11KW1 CENTRAL PROCESSING UNIT BSR, Branch to subroutine Main program PC ...
Page 34
... Refer to Table 3-2, which shows the condition codes that are affected by a particular instruction. MOTOROLA 3-4 Table 3-1 Reset vector comparison POR or RESET pin Clock monitor $FFFE, $FFFF $FFFC, $FFFD $BFFE, $BFFF $BFFE, $BFFF CENTRAL PROCESSING UNIT COP watchdog $FFFA, $FFFB $BFFE, $BFFF TPG MC68HC11KW1 ...
Page 35
... Normally, the I-bit is zero after a return from interrupt is executed. Although the I-bit can be cleared within an interrupt service routine, ‘nesting’ interrupts in this way should only be done when there is a clear understanding of latency and of the arbitration mechanism. Refer to Section 5. MC68HC11KW1 CENTRAL PROCESSING UNIT 3 TPG ...
Page 36
... A byte is eight bits wide and can be accessed at any byte location. A word is composed of two consecutive bytes with the most significant byte at the lower value address. Because the M68HC11 is an 8-bit CPU, there are no special requirements for alignment of instructions or operands. MOTOROLA 3-6 CENTRAL PROCESSING UNIT TPG MC68HC11KW1 ...
Page 37
... In most applications, this 256-byte area is reserved for frequently referenced data. In M68HC11 MCUs, the memory map can be configured for combinations of internal registers, RAM, or external memory to occupy these addresses. MC68HC11KW1 CENTRAL PROCESSING UNIT 3 TPG ...
Page 38
... Instruction set Refer to Table 3-2, which shows all the M68HC11 instructions in all possible addressing modes. For each instruction, the table shows the operand construction, the number of machine code bytes, and execution time in CPU E clock cycles. MOTOROLA 3-8 CENTRAL PROCESSING UNIT TPG MC68HC11KW1 ...
Page 39
... BCLR (opr) Clear bit(s) (msk) BCS (rel) Branch if carry set BEQ (rel) Branch if equal to zero BGE (rel) Branch if zero BGT (rel) Branch if > zero BHI (rel) Branch if higher MC68HC11KW1 CENTRAL PROCESSING UNIT Instruction Addressing Description mode Opcode Operand INH 1B — (00:B) ...
Page 40
... — — — — — — — — — 2 — — — — — 2 — — — — MC68HC11KW1 TPG ...
Page 41
... INCB Increment accumulator B INS Increment stack pointer INX Increment index register X INY Increment index register Y JMP (opr) Jump JSR (opr) Jump to subroutine LDAA (opr) Load accumulator A MC68HC11KW1 CENTRAL PROCESSING UNIT Instruction Addressing Description mode Opcode Operand D – (M:M+1) IMM DIR 1A 93 ...
Page 42
... — 3 — — — — — — — — 37 — 3 — — — — — — — — 3C — 4 — — — — — — — — — 5 — — — — — — — — MC68HC11KW1 TPG ...
Page 43
... Store accumulator A STAB (opr) Store accumulator B STD (opr) Store accumulator D STOP Stop internal clocks STS (opr) Store stack pointer STX (opr) Store index register X STY (opr) Store index register Y MC68HC11KW1 CENTRAL PROCESSING UNIT Instruction Addressing Description mode Opcode Operand A A INH 32 — ...
Page 44
... MC68HC11KW1 TPG ...
Page 45
... ROM. Test is a special expanded mode that allows privileged access to internal resources. 4.1.1 Single chip operating mode In single chip operating mode, the MC68HC11KW1 microcontroller has no external address or data bus. Ports B, C and F are available for general-purpose parallel I/O. 4.1.2 Expanded operating mode In expanded operating mode, the MCU can access a 64K byte physical address space ...
Page 46
... In bootstrap mode, the interrupt vectors point to RAM. This allows the use of interrupts through a jump table. Further baud rate options are available on the MC68HC11KW1 by using a different value for the synchronization byte, as shown in Table 4-1. Refer also to Motorola application note AN1060, M68HC11 Bootstrap Mode (the bootloader mode is similar to that used on the MC68HC11K4) ...
Page 47
... On-chip memory The MC68HC11KW1 MCU includes 768 bytes of on-chip RAM and 640 bytes of EEPROM. The bootloader ROM occupies a 448 byte block of the memory map. The CONFIG register is implemented as a separate EEPROM byte. Start address $0000 $00A0 $03A0 $0D80 $1000 $BE40 ...
Page 48
... RAM The MC68HC11KW1 has 768 bytes of fully static RAM that are used for storing instructions, variables and temporary data during program execution. RAM can be placed at any 4K boundary in the 64K byte address space by writing an appropriate value to the INIT register. ...
Page 49
... Capture 4/compare 5 (TI4/O5) low $001F Timer control 1 (TCTL1) $0020 Timer control 2 (TCTL2) $0021 EDG4B EDG4A EDG1B EDG1A EDG2B EDG2A EDG3B EDG3A 0000 0000 Timer interrupt mask 1 (TMSK1) $0022 MC68HC11KW1 OPERATING MODES AND ON-CHIP MEMORY bit 6 bit 5 bit 4 bit 3 PA7 PA6 PA5 ...
Page 50
... DLY CME FCME CR1 CR0 0001 0000 (4) (3) (2) (1) (bit 0) undefined EEPG 0000 0000 M FCM FCOP 0 0000 x000 NOCO 1 EEON 11xx xx1x P (12) (11) (10) (9) (8) undefined uu00 0000 (12) (11) (10) (9) (8) undefined uu00 0000 MC68HC11KW1 State TPG ...
Page 51
... Pulse width polarity select (PWPOL) $0061 PCLK4 PCLK3 PCLK2 PCLK1 PPOL4 PPOL3 PPOL2 PPOL1 0000 0000 Pulse width scale (PWSCAL) $0062 Pulse width enable (PWEN) $0063 TPWSL DISCP Pulse width count 1 (PWCNT1) $0064 MC68HC11KW1 OPERATING MODES AND ON-CHIP MEMORY bit 6 bit 5 bit 4 bit 3 (14) (13) ...
Page 52
... PG3 PG2 PG1 PG0 undefined OL2 OM3 OL3 OM4 OL4 0000 0000 (12) (11) (10) (9) (bit 8) 0000 0000 (4) (3) (2) (1) (bit 0) 0000 0000 (12) (11) (10) (9) (bit 8) 1111 1111 (4) (3) (2) (1) (bit 0) 1111 1111 (12) (11) (10) (9) (bit 8) 1111 1111 MC68HC11KW1 State TPG ...
Page 53
... Timer 3 mask (T3MSK) $009C Timer 3 flag (T3FLG) $009D OC1F OC2F OC3F Port K data (PORTK) $009E Data direction K (DDRK) $009F KEY x State on reset depends on mode selected u State of bit on reset is undefined MC68HC11KW1 OPERATING MODES AND ON-CHIP MEMORY bit 6 bit 5 bit 4 bit 3 (bit 7) (6) (5) (4) (3) ...
Page 54
... Table 4-3 Registers with limited write access Register name through a pull-up resistor of 4 The MODA pin also functions as DD OPERATING MODES AND ON-CHIP MEMORY Must be written in Write first 64 cycles once only (1) — (2) — No Yes (3) No (4) — (5) — (6) No (6) No MC68HC11KW1 TPG ...
Page 55
... Normal single chip or special bootstrap mode. (Ports active.) Table 4-4 Hardware mode select summary Inputs MODB MODA PSEL[4:0] — Priority select bits (refer to Section 5) MC68HC11KW1 OPERATING MODES AND ON-CHIP MEMORY bit 7 bit 6 bit 5 bit 4 bit 3 Control bits in HPRIO (latched at reset) Mode RBOOT SMOD Single chip 0 ...
Page 56
... Pull-ups can be enabled using PPAR. 0 (clear) – All pull-ups disabled (not controlled by PPAR). MOTOROLA 4-12 Address bit 7 bit 6 bit 5 $003F 1 1 CLKX PAREN NOSEC OPERATING MODES AND ON-CHIP MEMORY bit 4 bit 3 bit 2 bit 1 bit 0 on reset NOCO 1 EEON 11xx xx1x P MC68HC11KW1 State TPG ...
Page 57
... REG[3:0] — 160-byte register block position These four bits specify the upper hexadecimal digit of the address for the 160-byte block of internal registers. The register block is positioned at the beginning of any 4K page in the memory map. Refer to Table 4-5. MC68HC11KW1 OPERATING MODES AND ON-CHIP MEMORY bit 7 bit 6 ...
Page 58
... Register block RAM B RAM A MC68HC11KW1 TPG ...
Page 59
... The time protected control bits IRQE, DLY, FCME and CR[1:0] can be written only once in the first 64 cycles after a reset and then they become read-only bits. This minimizes the possibility of any accidental changes to the system configuration. They may be written at any time in special modes. MC68HC11KW1 OPERATING MODES AND ON-CHIP MEMORY bit 7 bit 6 ...
Page 60
... Clock monitor enabled; cannot be disabled until next reset. 0 (clear) – Clock monitor follows the state of the CME bit. When FCME is set, slow or stopped clocks will cause a clock failure reset sequence. To utilize STOP mode, FCME should always be cleared. MOTOROLA 4-16 OPERATING MODES AND ON-CHIP MEMORY TPG MC68HC11KW1 ...
Page 61
... In single chip modes this bit determines whether the E clock drives out from the chip. 1 (set) – E pin is driven low. 0 (clear) – E clock is driven out from the chip. Refer to the following table for a summary of the operation immediately following reset. MC68HC11KW1 OPERATING MODES AND ON-CHIP MEMORY bit 7 bit 6 bit 5 bit 4 bit 3 ...
Page 62
... BULKP BIT6 BPRT4 PTCON BPRT3 BPRT2 BPRT1 BPRT0 1111 1111 OPERATING MODES AND ON-CHIP MEMORY IRVNE IRVNE affects only can be written E Once IRV Once E Unlimited IRV Unlimited 16 MHz 4 MHz 2.7 MHz 2 MHz bit 4 bit 3 bit 2 bit 1 bit 0 on reset MC68HC11KW1 State TPG ...
Page 63
... Protection is enabled for associated block; it cannot be programmed or erased. 0 (clear) – Protection disabled for associated block. Each of these five bits protects a block of EEPROM against writing or erasure, as follows: Table 4-8 EEPROM block protect MC68HC11KW1 OPERATING MODES AND ON-CHIP MEMORY Bit Block Block size name ...
Page 64
... Refer to the following table: MOTOROLA 4-20 Address bit 7 bit 6 bit 5 $0024 TOI RTII PAOVI PR[1:0] Prescale factor OPERATING MODES AND ON-CHIP MEMORY bit 4 bit 3 bit 2 bit 1 bit 0 on reset PAII 0 0 PR1 PR0 0000 0000 MC68HC11KW1 State TPG ...
Page 65
... PR3A and PR3B — Timer 3 prescaler select These bits are used to select the prescaler divide-by ratio for Timer 3. They can only be written to once after reset. If PR3B and PR3A are both cleared, then Timer 3 is synchronized to the prescaled Timer 1 rate. MC68HC11KW1 OPERATING MODES AND ON-CHIP MEMORY bit 7 bit 6 ...
Page 66
... Memory expansion logic The MC68HC11KW1 has the ability to extend the address range of the M68HC11 CPU beyond the physical 64K byte limit of the 16 CPU address lines. The extra addressing capability is provided by a register-based paging scheme using expansion address lines and the physical 64K bytes of CPU address space. Two additional on-chip blocks are provided with the MC68HC11KW1. The fi ...
Page 67
... ADDR14 must be inverted to allow 32K bytes of contiguous memory. The MC68HC11KW1 CPU drives the inverted CPU ADDR14 signal onto the XA14 pin when the window is active. In this case, the XA14 signal must be connected to the address line 14 of the memory device. ...
Page 68
... ADDR[13:0] ADDR[14:0] XA[16:14] XA[17:15] ADDR[13:0] ADDR[14:0] XA[17:14] XA[18:15] ADDR[13:0] — XA[18:14] — — — — — memory. OPERATING MODES AND ON-CHIP MEMORY 32K bytes (window based at $4000) ADDR[13:0] XA[15:14] ADDR[13:0] XA[16:14] ADDR[13:0] XA[17:14] ADDR[13:0] XA[18:14] — — — — TPG MC68HC11KW1 ...
Page 69
... Registers, RAM and EEPROM $1000 $4000 Chip select 1 $6000 $FFC0 Vectors $FFFF Figure 4-3 Memory map example of memory expansion MC68HC11KW1 OPERATING MODES AND ON-CHIP MEMORY Window 1 $00000 $02000 $04000 $06000 $08000 Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 Bank 6 Bank 7 XA[15:13] XA[15:13] ...
Page 70
... V DD 27C512 VCC XA15 A15 XA14 A14 OE XA13 A13 CE A12 A11 VSS A10 ADDR9 A9 ADDR8 A8 ADDR7 DATA7 A7 D7 ADDR6 DATA6 A6 D6 ADDR5 DATA5 A5 D5 ADDR4 DATA4 A4 D4 ADDR3 DATA3 A3 D3 ADDR2 DATA2 A2 D2 ADDR1 DATA1 A1 D1 ADDR0 DATA0 A0 D0 MC68HC11KW1 TPG ...
Page 71
... PGAR = $1F XA[17:13] MMWBR = $84 window 1 @ $4000, window 2 @ $8000 MMSIZ = $42 window bytes, window 2 = 16K bytes Figure 4-5 Memory map example of memory expansion MC68HC11KW1 OPERATING MODES AND ON-CHIP MEMORY Window 1 $00000 $02000 $04000 $06000 $08000 Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 Bank 6 Bank 7 XA[15:13] ...
Page 72
... A15 XA14 OE A14 XA13 A13 W ADDR12 A12 ADDR11 A10 V SS ADDR10 A10 ADDR9 A9 NC ADDR8 A8 ADDR7 DATA7 A7 D7 ADDR6 DATA6 A6 D6 ADDR5 DATA5 A5 D5 ADDR4 DATA4 A4 D4 ADDR3 DATA3 A3 D3 ADDR2 DATA2 A2 D2 ADDR1 DATA1 A1 D1 ADDR0 DATA0 A0 D0 MC68HC11KW1 TPG ...
Page 73
... These bits select the bank size for window 1. The window starting address depends on the contents of the MMWBR register and continues for the same number of bytes as the selected window size. Refer to Table 4-10. Table 4-10 Window size select WxSZ[1: MC68HC11KW1 OPERATING MODES AND ON-CHIP MEMORY bit 7 bit 6 bit 5 bit 4 bit 3 0 Window size Window disabled 8K – ...
Page 74
... OPERATING MODES AND ON-CHIP MEMORY bit 4 bit 3 bit 2 bit 1 bit 0 on reset 0 W1A15 W1A14 W1A13 0 0000 0000 $0000 $0000 $4000 $4000 $8000 $8000 $8000 $8000 MC68HC11KW1 State TPG ...
Page 75
... On-chip registers, RAM, and EEPROM have higher priority than expansion windows window overlaps RAM, registers or EEPROM, they appear in all banks at their CPU address. – Window 1 has a higher priority than window 2, therefore any overlapped portion of window 2 is inaccessible. MC68HC11KW1 OPERATING MODES AND ON-CHIP MEMORY bit 7 bit 6 bit 5 ...
Page 76
... CSCTL register. When an MCU pin is not used for chip select functions, it can be used for general-purpose I/O. The MC68HC11KW1 has four software configured chip selects that are enabled in expanded modes. The chip select for I/O (CSIO) is used for I/O expansion. The program chip select (CSPROG) is used with an external memory that contains the reset vectors and program ...
Page 77
... Polarity of the active state is programmable for active high or active low. Clock stretching can be set from zero to three cycles. Refer to Section 4.5.4 for descriptions of bits IOEN, IOPL, IOCSA, and IOSZ. MC68HC11KW1 OPERATING MODES AND ON-CHIP MEMORY GCSPR = 0 ...
Page 78
... Table 4-13 Program chip select size PCSZA PCSZB Size (bytes) Address range 0 0 64K $0000 – $FFFF 0 1 32K $8000 – $FFFF 1 0 16K $C000 – $FFFF $E000 – $FFFF OPERATING MODES AND ON-CHIP MEMORY bit 4 bit 3 bit 2 bit 1 bit 0 on reset MC68HC11KW1 State TPG ...
Page 79
... G1A18 G1A17 G1A16 G1A15 G1A14 G1A13 G1A12 G1A11 0000 0000 Gen. purpose chip select 1 addr. (GPCS1A) G1A[18:11] — General-purpose chip select 1 address These bits select the starting address of general-purpose chip select 1 range. Refer to Table 4-15. MC68HC11KW1 OPERATING MODES AND ON-CHIP MEMORY Condition Priority ...
Page 80
... These bits select the size for general-purpose chip select 1. Refer to Table 4-15. MOTOROLA 4-36 Address bit 7 bit 6 bit 5 $005D G1DG2 G1DPC G1POL G1AV G1SZA G1SZB G1SZC G1SZD 0000 0000 OPERATING MODES AND ON-CHIP MEMORY bit 4 bit 3 bit 2 bit 1 bit 0 on reset MC68HC11KW1 State TPG ...
Page 81
... G2DPC — General-purpose chip select 2 drives program chip select 1 (set) – CSGP2 and CSPROG are OR'ed and driven out the CSPROG pin. 0 (clear) – Does not affect program chip select. MC68HC11KW1 OPERATING MODES AND ON-CHIP MEMORY Valid bits Size (bytes) (MXGS1 = 0) D ...
Page 82
... Default to 512K OPERATING MODES AND ON-CHIP MEMORY Valid bits Valid bits (MXGS2 = 0) (MXGS2 = 1) None None G2A[15:11] G2A[18:11] G2A[15:12] G2A[18:12] G2A[15:13] G2A[18:13] G2A[15:14] G2A[18:14] G2A15 G2A[18:15] None G2A[18:16] None G2A[18:17] None G2A18 None None None None None None None None MC68HC11KW1 TPG ...
Page 83
... GP2SA, GP2SB — CSGP2 stretch select PCSA, PCSB — CSPROG stretch select In normal modes (SMOD = 0), PCSB is set on reset to give a one cycle stretch. In special modes (SMOD = 1), PCSB is cleared on reset. MC68HC11KW1 OPERATING MODES AND ON-CHIP MEMORY General 2 CS pin asserted when address is in: ...
Page 84
... G2DPC in GPCS2C allows CSGP2 and CSPROG to be logically OR'ed and driven out the CSPROG pin. MXGS2 in MMSIZ allows CSGP2 to follow either 64K CPU addresses or 512K expansion addresses. MXGS1 in MMSIZ allows CSGP1 to follow either 64K CPU addresses or 512K expansion addresses. OPERATING MODES AND ON-CHIP MEMORY TPG MC68HC11KW1 ...
Page 85
... BYTE — EEPROM byte erase mode 1 (set) – Erase only one byte of EEPROM. 0 (clear) – Row or bulk erase mode used. MC68HC11KW1 OPERATING MODES AND ON-CHIP MEMORY , a separate external power supply is not required. DD bit 7 bit 6 bit 5 ...
Page 86
... EEPROM must be erased by a separate erase operation before programming. The following MOTOROLA 4-42 Table 4-19 Erase mode selection Byte Row Action 0 0 Bulk erase (all 640 bytes Row erase (16 bytes Byte erase 1 1 Byte erase OPERATING MODES AND ON-CHIP MEMORY TPG MC68HC11KW1 ...
Page 87
... Turn off high voltage and set to READ mode 4.6.1.3 EEPROM row erase The following example shows how to perform a fast erase of 16 bytes of EEPROM: ROWE LDAB #$0E ROW=ERASE=EELAT=1 STAB $003B Set to ROW erase mode MC68HC11KW1 OPERATING MODES AND ON-CHIP MEMORY (See Section A.6). 4 TPG MOTOROLA 4-43 ...
Page 88
... Turn on high voltage Delay tEEPROG Turn off high voltage and set to READ mode Address bit 7 bit 6 bit 5 $003F 1 1 CLKX PAREN NOSEC OPERATING MODES AND ON-CHIP MEMORY bit 4 bit 3 bit 2 bit 1 bit 0 on reset NOCO 1 EEON 11xx xx1x P MC68HC11KW1 State TPG ...
Page 89
... Note: A mask option on the MC68HC11KW1 determines whether or not the security feature is made available. If the feature is available, then the secure mode can be invoked by programming the NOSEC bit to zero. Otherwise, the NOSEC bit is permanently set to one, disabling security ...
Page 90
... If the MODA and MODB pins are configured for special test mode, the part will start in bootstrap mode. MOTOROLA 4-46 Address bit 7 bit 6 bit 5 $003F 1 1 CLKX PAREN NOSEC OPERATING MODES AND ON-CHIP MEMORY bit 4 bit 3 bit 2 bit 1 bit 0 on reset NOCO 1 EEON 11xx xx1x P MC68HC11KW1 State TPG ...
Page 91
... RESET pin low whenever V voltage level detector, or other external reset circuits, are the usual source of reset in a system. The POR circuit only initializes internal circuitry during power on. Refer to Figure 2-3. MC68HC11KW1 5 is below the minimum operating level. This external ...
Page 92
... Table 5-1 COP timer rate select 15 by EXTAL = 16 MHz: timeout 8.192 32.768 131.072 524.288 MHz clock due to the asynchronous implementation of the COP circuitry. For example, with MHz, the uncertainty is –0/+8.192 ms. See also the M68HC11 Reference Manual, (M68HC11RM/AD). RESETS AND INTERRUPTS (1) 15 TPG MC68HC11KW1 ...
Page 93
... STOP mode was initiated. Before executing a STOP instruction, clear the CME bit in the OPTION register to zero to disable the clock monitor. After recovery from STOP, set the CME bit to logic one to enable the clock monitor. MC68HC11KW1 bit 7 bit 6 ...
Page 94
... CME — Clock monitor enable 1 (set) – Clock monitor enabled. 0 (clear) – Clock monitor disabled. MOTOROLA 5-4 Address bit 7 bit 6 bit 5 bit 4 $0039 ADPU CSEL IRQE DLY RESETS AND INTERRUPTS State bit 3 bit 2 bit 1 bit 0 on reset CME FCME CR1 CR0 0001 0000 MC68HC11KW1 TPG ...
Page 95
... SMOD = 0 (single chip or expanded mode), these bits can only be written using the EEPROM programming sequence, and none of the bits are readable or active until latched via the next reset. Bits [ — Not implemented; always read one. MC68HC11KW1 15 before it enters the COP watchdog system. These control ...
Page 96
... These initial states then control on-chip peripheral systems to force them to known start-up states, as described in the following paragraphs. MOTOROLA 5-6 Normal mode Cause of reset vector $FFFE, $FFFF $FFFC, $FFFD $FFFA, $FFFB RESETS AND INTERRUPTS Special test or bootstrap $BFFE, $BFFF $BFFC, $BFFD $BFFA, $BFFB MC68HC11KW1 TPG ...
Page 97
... The I4/O5 bit in the PACTL register is cleared to configure the I4/O5 function as OC5; however, the OM5:OL5 control bits in the TCTL1 register are clear so OC5 does not control the PA3 pin. MC68HC11KW1 RESETS AND INTERRUPTS 5 ...
Page 98
... The TDRE and TC status bits in the SCI status register are both set, indicating that there is no transmit data in either the transmit data register or the transmit serial shift register. The RDRF, IDLE, OR, NF, FE, PF, and RAF receive-related status bits are cleared. MOTOROLA 5-8 RESETS AND INTERRUPTS TPG MC68HC11KW1 ...
Page 99
... Illegal opcode interrupt — see Section 5.4.3 for details of handling – Software interrupt (SWI) — see Section 5.4.4 for details of handling The maskable interrupt sources have the following priority arrangement: 5) IRQ 6) Real-time interrupt 7) Timer 1 input capture 1 MC68HC11KW1 RESETS AND INTERRUPTS 5 TPG MOTOROLA 5-9 ...
Page 100
... Bootloader ROM enabled, at $BE40–$BFFF. 0 (clear) – Bootloader ROM disabled and not in map. MOTOROLA 5-10 Address bit 7 bit 6 bit 5 bit 4 $003C RBOOT SMOD MDA PSEL4 PSEL3 PSEL2 PSEL1 PSEL0 xxx0 0110 RESETS AND INTERRUPTS State bit 3 bit 2 bit 1 bit 0 on reset MC68HC11KW1 TPG ...
Page 101
... MC68HC11KW1 Interrupt source promoted Reserved (default to IRQ Reserved (default to IRQ Reserved (default to IRQ IRQ (external pin Real-time interrupt 0 0 Timer 1 input capture Timer 1 input capture Timer 1 input capture Timer 1 output compare Timer 1 output compare Timer 1 output compare Timer 1 output compare Timer 1 output compare 5/input capture 4 ...
Page 102
... C4I OC1I I OC2I OC3I I TO2I I C4I OC1I I OC2I OC3I RIE RIE I TIE TCIE ILIE I SPIE I PAII I PAOVI I TOI I I4/O5I I OC4I I OC3I I OC2I I OC1I I IC3I I IC2I I IC1I I RTII I None X None None None None None NOCO None P None CME None None TPG MC68HC11KW1 ...
Page 103
... Interrupts Excluding reset type interrupts, the MC68HC11KW1 has 23 interrupt vectors that support 32 interrupt sources. The 20 maskable interrupts are generated by on-chip peripheral systems. These interrupts are recognized when the global interrupt mask bit (I) in the condition code register (CCR) is clear. The three nonmaskable interrupt sources are illegal opcode trap, software interrupt, and XIRQ pin ...
Page 104
... SWI is an instruction, and thus cannot be interrupted until complete. SWI is not inhibited by the global mask bits in the CCR. Because execution of SWI sets the I mask bit, once an SWI interrupt begins, other interrupts are inhibited until SWI is complete, or until user software clears the I bit in the CCR. MOTOROLA 5-14 RESETS AND INTERRUPTS TPG MC68HC11KW1 ...
Page 105
... NOCOP being set. Timers 2 and 3 can be stopped under the control of bits in the TCTL4 and TCTL6 registers, respectively. Several other systems can also reduced power consumption state depending on the state of software-controlled configuration control bits. Power consumption by the analog-to-digital (A/D) converter is not affected significantly by the WAIT condition. MC68HC11KW1 RESETS AND INTERRUPTS 5 TPG ...
Page 106
... This same delay also applies to power-on-reset, regardless of the state of the DLY control bit, but does not apply to a reset while the clocks are running. See Section 4.3.2.4. MOTOROLA 5- worst case current consumption power is maintained. The CPU state and I/O pin DD RESETS AND INTERRUPTS are supplied then the interval TPG MC68HC11KW1 ...
Page 107
... External reset Delay (4064 cycles) Load program counter with contents of $FFFE, $FFFF (vector fetch) 1A Figure 5-1 Processing flow out of reset ( MC68HC11KW1 Priority Clock monitor fail (CME = 1) Load program counter with contents of $FFFC, $FFFD (vector fetch) Set S, X, and I bits in CCR. Reset MCU hardware ...
Page 108
... Start next instruction 1A sequence Figure 5-2 Processing flow out of reset ( RESETS AND INTERRUPTS Stack Yes CPU registers Yes Stack CPU registers Interrupt No yet? Yes Set I-bit Resolve interrupt priority and fetch vector for highest pending source (Figure 5-3) MC68HC11KW1 TPG ...
Page 109
... Yes IRQ? No Yes RTII = 1? No Yes IC1I = 1? No Yes IC2I = 1? No Yes IC3I = 1? No Yes OC1I = Figure 5-3 Interrupt priority resolution ( MC68HC11KW1 XIRQ pin Yes low? No Yes RTIF = 1? No Yes IC1F = 1? No Yes IC2F = 1? No Yes IC3F = 1? No Yes OC1F = 1? No RESETS AND INTERRUPTS Set X-bit in CCR ...
Page 110
... RESETS AND INTERRUPTS 2B Fetch vector at Yes $FFE6, $FFE7 Fetch vector at Yes $FFE4, $FFE5 Fetch vector at Yes $FFE2, $FFE3 Fetch vector at Yes $FFE0, $FFE1 Fetch vector at $FFD4, $FFD5 Fetch vector at $FFD2, $FFD3 Yes Fetch vector at $FFDE, $FFDF Yes Fetch vector at $FFD0, $FFD1 2D MC68HC11KW1 TPG ...
Page 111
... No Spurious interrupt — take IRQ vector † Flag polling is required to determine the source of this interrupt (refer to Section 9). ‡ Refer to Figure 5-6 for further details on SCI interrupts. Figure 5-5 Interrupt priority resolution ( MC68HC11KW1 Yes PAOVF = 1? No Yes PAIF = 1? No Yes ...
Page 112
... Figure 5-6 Interrupt source resolution within the SCI subsystem MOTOROLA 5-22 Yes Yes Yes RIE = 1? No Yes Yes TIE = 1? No Yes Yes TCIE = 1? No Yes Yes ILIE = 1? No RESETS AND INTERRUPTS Yes Yes Yes Valid SCI interrupt request MC68HC11KW1 TPG ...
Page 113
... PARALLEL INPUT/OUTPUT The MC68HC11KW1 has input/output lines and 10 input-only lines, depending on the operating mode. To enhance the I/O functions, the data bus of this microcontroller is non-multiplexed. The following table is a summary of the configuration and features of each port. Input Port pins A — B — ...
Page 114
... PA4 Address bit 7 bit 6 bit 5 bit 4 $0001 DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 0000 0000 PARALLEL INPUT/OUTPUT State bit 3 bit 2 bit 1 bit 0 on reset PA3 PA2 PA1 PA0 undefined State bit 3 bit 2 bit 1 bit 0 on reset MC68HC11KW1 TPG ...
Page 115
... Data direction B (DDRB) $0002 DDB[7:0] — Data direction for port B 1 (set) – The corresponding pin is configured as an output. 0 (clear) – The corresponding pin is configured as an input. MC68HC11KW1 Alternative function ADDR8 ADDR9 In expanded or test mode, the pins ADDR10 become the high ...
Page 116
... PC4 Address bit 7 bit 6 bit 5 bit 4 $0007 DDC7 DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 0000 0000 PARALLEL INPUT/OUTPUT State bit 3 bit 2 bit 1 bit 0 on reset PC3 PC2 PC1 PC0 undefined State bit 3 bit 2 bit 1 bit 0 on reset MC68HC11KW1 TPG ...
Page 117
... Data direction D (DDRD) $0009 DDD[7:0] — Data direction for port D 1 (set) – The corresponding pin is configured as an output. 0 (clear) – The corresponding pin is configured as an input. MC68HC11KW1 Alternative function RXD See Section 7 for TXD more information. MISO MOSI ...
Page 118
... AN5 See Section 10 for more information. PE4 AN6 PE5 AN7 PE6 AN8 PE7 AN9 Address bit 7 bit 6 bit 5 bit 4 $000A PE7 PE6 PE5 PE4 PARALLEL INPUT/OUTPUT State bit 3 bit 2 bit 1 bit 0 on reset PE3 PE2 PE1 PE0 undefined MC68HC11KW1 TPG ...
Page 119
... Data direction F (DDRF) $0003 DDF[7:0] — Data direction for port F 1 (set) – The corresponding pin is configured as an output. 0 (clear) – The corresponding pin is configured as an input. MC68HC11KW1 Alternative function ADDR0 ADDR1 In expanded or test mode, the pins ADDR2 become the low ...
Page 120
... XA16 PG4 XA17 PG5 XA18 PG6 AN0 See Section 10 for more information. PG7 AN1 Address bit 7 bit 6 bit 5 $007E PG7 PG6 PG5 PARALLEL INPUT/OUTPUT bit 4 bit 3 bit 2 bit 1 bit 0 on reset PG4 PG3 PG2 PG1 PG0 undefined MC68HC11KW1 State TPG ...
Page 121
... Section 4.4. Bits [7:6] — Not implemented; always read zero PGAR[5:0] — Port G pin assignment 1 (set) – Corresponding port G pin is expansion address line (XA[18:13]). 0 (clear) – Corresponding port G pin is general-purpose I/O. MC68HC11KW1 bit 7 bit 6 bit 5 bit 4 bit DDG5 DDG4 DDG3 DDG2 DDG1 DDG0 0000 0000 ...
Page 122
... PH4 Address bit 7 bit 6 bit 5 bit 4 $007D DDH7 DDH6 DDH5 DDH4 DDH3 DDH2 DDH1 DDH0 0000 0000 PARALLEL INPUT/OUTPUT State bit 3 bit 2 bit 1 bit 0 on reset PH3 PH2 PH1 PH0 undefined State bit 3 bit 2 bit 1 bit 0 on reset MC68HC11KW1 TPG ...
Page 123
... Address Data direction J (DDRJ) $008F DDJ[7:0] — Data direction for port J 1 (set) – The corresponding pin is configured as an output. 0 (clear) – The corresponding pin is configured as an input. MC68HC11KW1 Alternative function C4 OC3 See Section 9 for OC2 more information. OC1 ...
Page 124
... PK4 Address bit 7 bit 6 bit 5 bit 4 $009F DDK7 DDK6 DDK5 DDK4 DDK3 DDK2 DDK1 DDK0 0000 0000 PARALLEL INPUT/OUTPUT State bit 3 bit 2 bit 1 bit 0 on reset PK3 PK2 PK1 PK0 undefined State bit 3 bit 2 bit 1 bit 0 on reset MC68HC11KW1 TPG ...
Page 125
... I/O and set as high impedance inputs). Note: The pull-up resistors are disabled when the PAREN bit in the CONFIG register is equal to ‘0’. The approximate value of these resistors is 14–17Kohms. MC68HC11KW1 bit 7 bit 6 bit 5 bit 4 ...
Page 126
... These two bits control the frequency of the XCLK signal, which is output on the XOUT pin if enabled by the CLKX bit in CONFIG. MOTOROLA 6-14 Address bit 7 bit 6 bit 5 bit 4 $0038 LIRDV CWOM 0 IRVNE LSBF SPR2 XDV1 XDV0 000x 0000 PARALLEL INPUT/OUTPUT State bit 3 bit 2 bit 1 bit 0 on reset MC68HC11KW1 TPG ...
Page 127
... COP system disabled. 0 (clear) – COP system enabled (forces reset on timeout). EEON — EEPROM enable (refer to Section 4) 1 (set) – EEPROM is present in the memory map. 0 (clear) – EEPROM is disabled from the memory map. MC68HC11KW1 bit 7 bit 6 bit 5 bit 4 bit CLKX PAREN NOSEC ...
Page 128
... THIS PAGE LEFT BLANK INTENTIONALLY MOTOROLA 6-16 PARALLEL INPUT/OUTPUT TPG MC68HC11KW1 ...
Page 129
... Figure 7-1. See Table 7-1 for example baud rate control values. EXTAL 13-bit counter Reset 13-bit compare SCBDH/L: SCI baud control Figure 7-1 SCI baud rate generator circuit diagram MC68HC11KW1 SERIAL COMMUNICATIONS INTERFACE 7 Alternative Pin function PD0 ...
Page 130
... An advanced data recovery scheme distinguishes valid data from noise in the serial data stream. The data input is selectively sampled to detect receive data, and majority sampling logic determines the value and integrity of each bit. MOTOROLA 7-2 SERIAL COMMUNICATIONS INTERFACE TPG MC68HC11KW1 ...
Page 131
... LOOPS WOMS † M WAKE ILT PE PT TIE TCIE RIE ILIE TE RE RWU SBK SCSR1 MC68HC11KW1 SERIAL COMMUNICATIONS INTERFACE SCDRH/SCDRL T8 (transmit buffer) 10/11-bit TX shift register LOOPS M PE Transmitter PT control TE SBK Flag control WAKE Receiver RWU control M LOOPS ILT 10/11-bit RX shift register Data ...
Page 132
... When a receiver finds that the message is not intended for it, it sets the RWU bit. Once set, the RWU control bit disables all but the necessary receivers for the remainder of the message, thus reducing software overhead MOTOROLA 7-4 SERIAL COMMUNICATIONS INTERFACE TPG MC68HC11KW1 ...
Page 133
... SCI. If the SCI is being used with 7 or 8-bit data, only SCDRL needs to be accessed. Note that if 9-bit data format is used, the upper register should be written first to ensure that it is transferred to the transmitter shift register with the lower register. MC68HC11KW1 SERIAL COMMUNICATIONS INTERFACE 7 ...
Page 134
... BTST BSPL SYNC SBR12 SBR11 SBR10 SBR9 SBR8 0000 0000 $0071 SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 0000 0100 EXTAL SCI baud rate = ----------------------------- - 16 2BR SERIAL COMMUNICATIONS INTERFACE State bit 3 bit 2 bit 1 bit 0 on reset MC68HC11KW1 TPG ...
Page 135
... Bit 5 — Not implemented; always reads zero M — Mode (select character format) 1 (set) – Start bit, 9 data bits, 1 stop bit. 0 (clear) – Start bit, 8 data bits, 1 stop bit. MC68HC11KW1 SERIAL COMMUNICATIONS INTERFACE EXTAL frequency: 16 MHz rate Dec value Hex value 110 ...
Page 136
... Parity odd (an odd number of ones causes parity bit to be zero, an even number of ones causes parity bit to be one). 0 (clear) – Parity even (an even number of ones causes parity bit to be zero, an odd number of ones causes parity bit to be one). MOTOROLA 7-8 SERIAL COMMUNICATIONS INTERFACE TPG MC68HC11KW1 ...
Page 137
... Wake-up enabled and receiver interrupts inhibited. 0 (clear) – Normal SCI receiver. SBK — Send break 1 (set) – Break codes generated as long as SBK is set. 0 (clear) – Break generator off. MC68HC11KW1 SERIAL COMMUNICATIONS INTERFACE bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 TIE TCIE ...
Page 138
... The IDLE flag is inhibited when RWU = 1. Clear IDLE by reading SCSR1 with IDLE set and then reading SCDR. MOTOROLA 7-10 Address bit 7 bit 6 bit 5 bit 4 $0074 TDRE TC RDRF IDLE SERIAL COMMUNICATIONS INTERFACE State bit 3 bit 2 bit 1 bit 0 on reset 1100 0000 MC68HC11KW1 TPG ...
Page 139
... In the SCSR2 only bit 0 is used, to indicate receiver active. The other seven bits always read zero. Bits [7:1] — Not implemented; always read zero RAF — Receiver active flag (read only) 1 (set) – A character is being received. 0 (clear) – A character is not being received. MC68HC11KW1 SERIAL COMMUNICATIONS INTERFACE bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 ...
Page 140
... When TIE and TDRE are one, an interrupt is requested. MOTOROLA 7-12 Address bit 7 bit 6 bit 5 bit 4 $0076 $0077 R7T7 R6T6 R5T5 R4T4 SERIAL COMMUNICATIONS INTERFACE State bit 3 bit 2 bit 1 bit 0 on reset undefined R3T3 R2T2 R1T1 R0T0 undefined MC68HC11KW1 TPG ...
Page 141
... The last receiver status flag and interrupt source come from the IDLE flag. The RXD line is idle if it has constantly been at logic one for a full character time. The IDLE flag is set only after the RXD line has been busy and becomes idle. This prevents repeated interrupts for the time RXD remains idle. MC68HC11KW1 SERIAL COMMUNICATIONS INTERFACE 7 ...
Page 142
... No valid SCI interrupt request Figure 7-3 Interrupt source resolution within SCI MOTOROLA 7-14 Yes Yes Yes RIE = 1? No Yes Yes TIE = 1? No Yes Yes TCIE = 1? No Yes Yes ILIE = 1? No SERIAL COMMUNICATIONS INTERFACE Yes Yes Yes Valid SCI interrupt request MC68HC11KW1 TPG ...
Page 143
... The SPI status block represents the SPI status functions (transfer complete, write collision, and mode fault) performed by the serial peripheral status register (SPSR). The SPI control block represents those functions that control the SPI system through the serial peripheral control register (SPCR). MC68HC11KW1 SERIAL PERIPHERAL INTERFACE 8 ...
Page 144
... SPI clock (master) Clock logic MSTR SPE SPIE SPCR – SPI control register Internal bus Figure 8-1 SPI block diagram SERIAL PERIPHERAL INTERFACE MISO S PD2 M M MOSI PD3 S Pin control logic S SCK PD4 M SS PD5 SPDR – SPI data register TPG MC68HC11KW1 ...
Page 145
... Any SPI output line must have its corresponding data direction bit in DDRD register set. If the DDR bit is clear, that line is disconnected from the SPI logic and becomes a general-purpose input. All SPI input lines are forced to act as inputs regardless of the state of the corresponding DDR bits in DDRD register. MC68HC11KW1 SERIAL PERIPHERAL INTERFACE 2 3 ...
Page 146
... SS must go high between successive characters in an SPI message. When CPHA = 1, SS can be left low between successive SPI characters. In cases where there is only one SPI slave MCU, its SS line can be tied to V used. MOTOROLA 8-4 as long as only CPHA = 1 clock mode is SS SERIAL PERIPHERAL INTERFACE TPG MC68HC11KW1 ...
Page 147
... SCK cycle. The transfer ends when SPIF is set, for a slave in which CPHA=1. 8.5 SPI registers The three SPI registers, SPCR, SPSR, and SPDR, provide control, status, and data storage functions. Refer to the following information for a description of how these registers are organized. MC68HC11KW1 SERIAL PERIPHERAL INTERFACE 8 TPG MOTOROLA ...
Page 148
... MSTR — Master mode select 1 (set) – Master mode 0 (clear) – Slave mode MOTOROLA 8-6 Address bit 7 bit 6 bit 5 bit 4 $0028 SPIE SPE DWOM MSTR CPOL CPHA SPR1 SPR0 0000 01uu SERIAL PERIPHERAL INTERFACE State bit 3 bit 2 bit 1 bit 0 on reset MC68HC11KW1 TPG ...
Page 149
... These two bits select the SPI clock rate, as shown in Table 8-1. Note that SPR2 is located in the OPT2 register, and that its state on reset is zero. SPR[2: MC68HC11KW1 SERIAL PERIPHERAL INTERFACE Table 8-1 SPI clock rates E clock SPI clock frequency ( baud rate) divide ratio for 4MHz 2 2.0 MHz 4 1.0 MHz ...
Page 150
... To clear the MODF bit, read the SPSR (with MODF set), then write to the SPCR. Refer to Section 8.3.4 and Section 8.4. Bits [5, 3:0] — Not implemented; always read zero. MOTOROLA 8-8 Address bit 7 bit 6 bit 5 bit 4 $0029 SPIF WCOL 0 MODF SERIAL PERIPHERAL INTERFACE State bit 3 bit 2 bit 1 bit 0 on reset 0000 0000 MC68HC11KW1 TPG ...
Page 151
... No visibility of internal reads on external bus. In single chip mode this bit determines whether the E clock drives out from the chip. 1 (set) – E pin is driven low. 0 (clear) – E clock is driven out from the chip. MC68HC11KW1 SERIAL PERIPHERAL INTERFACE bit 7 bit 6 bit 5 bit 4 bit 3 ...
Page 152
... SPCR, this bit specifies the SPI clock rate. Refer to Table 8-1. XDV[1, 0] — XOUT clock divide select (refer to Section 4) These two bits control the frequency of the XCLK signal, which is output on the XOUT pin if enabled by the CLKX bit in CONFIG. 8 MOTOROLA 8-10 SERIAL PERIPHERAL INTERFACE TPG MC68HC11KW1 ...
Page 153
... TIMING SYSTEM The MC68HC11KW1 contains three 16-bit timers. Figure 9-1 provides a diagram of the entire timing system. The main timer, Timer 1, is described in the following paragraphs; refer to Section 9.2 and Section 9.3 for descriptions of Timer 2 and Timer 3. 9.1 Timer 1 Timer 1 is the standard M68HC11 timing system, composed of several clock divider chains. The main clock divider chain includes a 16-bit free-running counter, driven by a programmable prescaler ...
Page 154
... E clock Internal bus clock PH2 (for CPU, PWM, A/D and memory) SPI 6 Pulse accumulator ÷ 2 Prescaler Real time interrupt RTR[1:0] Set Q FF2 + Reset Q Force COP Clock TCNT2 Clock TCNT3 TCNT1 MC68HC11KW1 reset T2OF IC/OC T3OF IC/OC T1OF IC/OC TPG ...
Page 155
... I/ output compare pins. When one of these pins is being used for an output compare function, it cannot be written directly were a general-purpose output. Each of the output compare functions (OC[5:2]) is related to one of the port A output pins. Output MC68HC11KW1 tapped off from the free-running counter chain. The COP Clock 16 ...
Page 156
... PACTL register. Otherwise, PA3 is configured as a fifth output compare out of reset, with bit I4/O5 being cleared. If the DDA3 bit is set (configuring PA3 as an output), and IC4 is enabled, then writes to PA3 cause edges on the pin to result in input captures. Writing to TI4/O5 has no effect when the TI4/O5 register is acting as IC4. MOTOROLA 9-4 TIMING SYSTEM TPG MC68HC11KW1 ...
Page 157
... TIC3 (lo) † Interrupt requests 1–9 (these are further qualified by the I-bit in the CCR) ‡ Port A pin actions are controlled by OC1M, OC1D, PACTL, TCTL1 and TCTL2 registers Figure 9-2 Timer 1 capture/compare block diagram MC68HC11KW1 TOI TOF 16-bit Taps for RTI, COP and PA ...
Page 158
... EDG4B EDG4A EDG1B EDG1A EDG2B EDG2A EDG3B EDG3A 0000 0000 EDGxB EDGxA Configuration 0 0 ICx disabled 0 1 ICx captures on rising edges only 1 0 ICx captures on falling edges only 1 1 ICx captures on any edge TIMING SYSTEM State bit 3 bit 2 bit 1 bit 0 on reset MC68HC11KW1 TPG ...
Page 159
... PA3 pin. To enable input capture pin, set the I4/O5 bit in the pulse accumulator control register (PACTL) to logic level one. To use output compare register, set the I4/O5 bit to a logic level zero. Refer to Section 9.6.1. The TI4/O5 register pair resets to ones ($FFFF). MC68HC11KW1 bit 7 bit 6 bit 5 ...
Page 160
... OC1M, and the output compare 1 data register, OC1D. OC1M specifies which port A outputs are to be used, and OC1D specifies what data is placed on these port pins. MOTOROLA 9-8 TIMING SYSTEM TPG MC68HC11KW1 ...
Page 161
... The CFORC bits should not normally be used on an output compare function that is programmed to toggle its output on a successful compare, because a normal compare occurring immediately before or after the force would produce a double toggle. This may be undesirable if it happens quickly, since the resulting output pulse would be very short. MC68HC11KW1 bit 7 bit 6 bit 5 ...
Page 162
... OC1M7 OC1M6 OC1M5 OC1M4 OC1M3 Address bit 7 bit 6 bit 5 bit 4 $000D OC1D7 OC1D6 OC1D5 OC1D4 OC1D3 TIMING SYSTEM State bit 3 bit 2 bit 1 bit 0 on reset 0000 0000 State bit 3 bit 2 bit 1 bit 0 on reset 0000 0000 MC68HC11KW1 TPG ...
Page 163
... OM[2:5] — Output mode OL[2:5] — Output level OMx These control bit pairs are encoded to specify the action taken after a successful OCx compare. OC5 functions only if the I4/O5 bit in the PACTL register is clear. MC68HC11KW1 bit 7 bit 6 bit 5 bit 4 bit 3 (14) (13) (12) ...
Page 164
... If the ICxI enable bit is set when the ICxF flag bit is set, a hardware interrupt sequence is requested. MOTOROLA 9-12 Address bit 7 bit 6 bit 5 bit 4 $0022 OC1I OC2I OC3I OC4I TIMING SYSTEM State bit 3 bit 2 bit 1 bit 0 on reset I4/O5I IC1I IC2I IC3I 0000 0000 MC68HC11KW1 TPG ...
Page 165
... Selected edge has been detected on corresponding port pin. 0 (clear) – Selected edge has not been detected on corresponding port pin. These flags are set each time a selected active edge is detected on the ICx input line MC68HC11KW1 bit 7 bit 6 bit 5 bit 4 bit 3 ...
Page 166
... Timer 3 prescale bits in the register TCTL6. See Section 9.3.5. The default state is that the Timer 1 prescale rate is used for Timer 3. MOTOROLA 9-14 Address bit 7 bit 6 bit 5 bit 4 $0024 TOI RTII PAOVI PAII PR[1:0] Prescaler TIMING SYSTEM State bit 3 bit 2 bit 1 bit 0 on reset 0 0 PR1 PR0 0000 0000 MC68HC11KW1 TPG ...
Page 167
... The functions of Timer 2 share I/O with the pins of port J as follows: The Timer 2 prescaler stage divider with the E clock as its input. Prescaling factors can be selected by the P2RA and P2RB bits in the TCTL4 register. Timer 2 also offers an MC68HC11KW1 bit 7 bit 6 bit 5 ...
Page 168
... Immediately before the switch it was sourced by the internal E clock, so the first 16-stage count cycle has an offset equal to the number of E clock cycles after reset before the first write to TCTL4. The T2STP bit can be used to reset the counter to zero, if required. 9 MOTOROLA 9-16 TIMING SYSTEM TPG MC68HC11KW1 ...
Page 169
... I1/O4 † Interrupt requests 1, 2 & 3 (these are further qualified by the I-bit in the CCR). ‡ Port J pin actions are controlled by the TCTL3 and TCTL4 registers. Figure 9-3 Timer 2 capture/compare block diagram MC68HC11KW1 TCNT2 (hi) TCNT2 (lo) 16-bit free running counter F23FRC ...
Page 170
... This may be undesirable if it happens quickly, since the resulting output pulse would be very short. MOTOROLA 9-18 Address bit 7 bit 6 bit 5 bit 4 $0031 FT3C1 FT3C2 FT3C3 FT3C4 FT2C1 FT2C3 FT2C3 FT2C4 0000 0000 TIMING SYSTEM State bit 3 bit 2 bit 1 bit 0 on reset MC68HC11KW1 TPG ...
Page 171
... Coherency requires a complete 16-bit read or write. However, if coherency is not needed, byte accesses can be used. For output compare functions, write a comparison value to output compare registers T2OC1–T2OC3 and TI1/O4. When TCNT2 value matches the comparison value, the specified pin actions occur. MC68HC11KW1 bit 7 bit 6 bit 5 bit 4 ...
Page 172
... Clear OCx output line Set OCx output line to 1 TIMING SYSTEM State bit 3 bit 2 bit 1 bit 0 on reset (11) (10) (9) (bit 8) 0000 0000 (3) (2) (1) (bit 0) 0000 0000 State bit 3 bit 2 bit 1 bit 0 on reset OM3 OL3 OM4 OL4 0000 0000 MC68HC11KW1 TPG ...
Page 173
... ECEB and ECEA — Event counter edge control These control bits configure the input clock source for the Timer 2 counter. They can be written to only once after reset. ECEB ECEA MC68HC11KW1 bit 7 bit 6 bit 5 bit 4 bit 3 EDGA Configuration 0 IC1 disabled ...
Page 174
... When I1/O4 in TCTL4 is set, C4I is the input capture 1 interrupt enable bit. When I1/O4 in TCTL4 is zero, C4I is the output compare 4 interrupt enable bit. MOTOROLA 9-22 Address bit 7 bit 6 bit 5 bit 4 $008C OC1I OC2I OC3I C4I TIMING SYSTEM State bit 3 bit 2 bit 1 bit 0 on reset TO2I 0000 0000 MC68HC11KW1 TPG ...
Page 175
... Selected edge has not been detected on pin PJ7. TO2F — Timer 2 overflow flag 1 (set) – TCNT2 has overflowed from $FFFF to $0000. 0 (clear) – No Timer 2 overflow has occurred. Bits [2:0] — Not implemented; always read zero. MC68HC11KW1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 C4F ...
Page 176
... PK3 ECIN PK4 OC1 PK5 OC2 PK6 OC3 PK7 C4 Address bit 7 bit 6 bit 5 bit 4 $009A (bit 15) (14) (13) (12) $009B (bit 7) (6) (5) (4) TIMING SYSTEM State bit 3 bit 2 bit 1 bit 0 on reset (11) (10) (9) (bit 8) 1111 1111 (3) (2) (1) (bit 0) 1111 1111 MC68HC11KW1 TPG ...
Page 177
... I1/O4 † Interrupt requests 1 and 2 (these are further qualified by the I-bit in the CCR). ‡ Port K pin actions are controlled by the TCTL5 and TCTL6 registers. Figure 9-4 Timer 3 capture/compare block diagram MC68HC11KW1 TCNT3 (hi) TCNT3 (lo) Clock select 16-bit free running counter ...
Page 178
... State bit 3 bit 2 bit 1 bit 0 on reset (11) (10) (9) (bit 8) 0000 0000 (3) (2) (1) (bit 0) 0000 0000 MC68HC11KW1 TPG ...
Page 179
... This pair of bits configures the input capture edge detector circuits for IC1. IC1 functions only if the I1/O4 bit is set. EDGB Note: The maximum frequency of the input clock must be less than E/2 when counting on one edge, and less that E/4 when counting on both edges. MC68HC11KW1 bit 7 bit 6 bit 5 bit 4 bit 3 OM1 OL1 OM2 OL2 ...
Page 180
... PR3B PR3A Prescaler 0 0 Use Timer 1 rate ECEA Configuration 0 0 Timer 2 uses internal clock and prescaler 0 1 Count on rising edges of external clock only 1 0 Count on falling edges of external clock only 1 1 Count on any edge of external clock TIMING SYSTEM TPG MC68HC11KW1 ...
Page 181
... When I1/O4 in TCTL4 is zero, C4I is the output compare 4 interrupt enable bit. TO3I — Timer 3 overflow interrupt enable 1 (set) – Timer 3 overflow interrupt requested when T3OF is set. 0 (clear) – T3OF interrupts disabled. Bits [2:0] — Not implemented; always read zero. MC68HC11KW1 bit 7 bit 6 bit 5 bit 4 bit 3 OC1I OC2I ...
Page 182
... No Timer 3 overflow has occurred. Bits [2:0] — Not implemented; always read zero. MOTOROLA 9-30 Address bit 7 bit 6 bit 5 bit 4 $009D OC1F OC2F OC3F C4F TIMING SYSTEM State bit 3 bit 2 bit 1 bit 0 on reset TO2F 0000 0000 MC68HC11KW1 TPG ...
Page 183
... TMSK2 enable the corresponding interrupt sources. TOI — Timer overflow interrupt enable (refer to Section 9.1.3.9) RTII — Real-time interrupt enable 1 (set) – Real time interrupt requested when RTIF is set. 0 (clear) – Real time interrupts disabled. MC68HC11KW1 Table 9-2 RTI periodic rates RTR[1: 4MHz E = xMHz 1.02ms ...
Page 184
... PAIF — Pulse accumulator input edge interrupt flag (refer to Section 9.6) Bits [3:0] — Not implemented; always read zero MOTOROLA 9-32 Address bit 7 bit 6 bit 5 bit 4 $0025 TOF RTIF PAOVF PAIF TIMING SYSTEM State bit 3 bit 2 bit 1 bit 0 on reset 0000 0000 MC68HC11KW1 TPG ...
Page 185
... COP function. 9.6 Pulse accumulator The MC68HC11KW1 has an 8-bit counter that can be configured to operate either as a simple event counter, or for gated time accumulation, depending on the state of the PAMOD bit in the PACTL register. Refer to the pulse accumulator block diagram, Figure 9-5. ...
Page 186
... TOF RTIF PAOVF PAIF & Overflow 2:1 Clock MUX Enable PACTL Figure 9-5 Pulse accumulator block diagram TIMING SYSTEM PACNT overflow 4.096 ms & 1 TOI Interrupt requests RTII PAOVI & 2 PAII 0 0 PR1 PR0 PACNT Internal data bus MC68HC11KW1 TPG ...
Page 187
... I4/O5 — Input capture 4/output compare 5 1 (set) – Input capture 4 function is enabled (no OC5). 0 (clear) – Output compare 5 function is enabled (no IC4). RTR[1:0] — RTI interrupt rate selects (refer to Section 9.4) MC68HC11KW1 bit 7 bit 6 bit 5 bit 4 bit 3 0 PAEN PAMOD PEDGE 0 ...
Page 188
... TOF RTIF PAOVF PAIF TIMING SYSTEM State bit 3 bit 2 bit 1 bit 0 on reset (3) (2) (1) (bit 0) undefined State bit 3 bit 2 bit 1 bit 0 on reset 0 0 PR1 PR0 0000 0000 State bit 3 bit 2 bit 1 bit 0 on reset 0000 0000 MC68HC11KW1 TPG ...
Page 189
... By configuring the PWMs for 16-bit mode with E equal to 4MHz, PWM periods greater than one minute are possible. In 16-bit mode, duty cycle resolution parts per million can be achieved (at a PWM frequency of 60Hz). In the same system, a PWM frequency of 1kHz corresponds to a duty cycle resolution of 0.025%. MC68HC11KW1 Pin Alternative function PH0 PW1 ...
Page 190
... When concatenated, channel 1 is the high-order byte and the channel 2 pin (PH1) is the output. MOTOROLA 9-38 Address bit 7 bit 6 bit 5 bit 4 $0060 CON34 CON12 PCKA2 PCKA1 TIMING SYSTEM State bit 3 bit 2 bit 1 bit 0 on reset 0 PCKB3 PCKB2 PCKB1 0000 0000 MC68HC11KW1 TPG ...
Page 191
... PWDTY3 8-bit comparator PWPER3 reset 8-bit comparator PWDTY4 8-bit comparator PWPER4 reset carry Figure 9-6 PWM timer block diagram MC68HC11KW1 PCKB1 PCKB2 PCKB3 Clock B Prescale select ÷ 16, 32, 64, 128 Prescale select reset 8-bit counter ÷ PCKA1 EQ 8-bit comparator ...
Page 192
... Bit 3 — Not implemented; always reads zero PCKB[3:1] — Prescaler for clock B Determines the frequency of clock B. Refer to Table 9-4. 9 PCKA[2: MOTOROLA 9-40 Table 9-4 Clock A and clock B prescalers Clock A PCKB[ TIMING SYSTEM Clock B E E/2 E/4 E/8 E/16 E/32 E/64 E/128 TPG MC68HC11KW1 ...
Page 193
... PWSCAL — PWM timer prescaler register Address Pulse width scale (PWSCAL) $0062 Scaled clock S is generated by dividing clock A by the value in PWSCAL, then dividing the result by two. If PWSCAL = $00, clock A is divided by 256, then divided by two to generate clock S. MC68HC11KW1 bit 7 bit 6 bit 5 bit 4 bit 3 ...
Page 194
... PWEN[4:1] — Pulse width channels 4–1 1 (set) – Channel enabled on the associated port pin. 0 (clear) – Channel disabled. MOTOROLA 9-42 Address bit 7 bit 6 bit 5 bit 4 $0063 TPWSL DISCP 0 0 TIMING SYSTEM State bit 3 bit 2 bit 1 bit 0 on reset PWEN4PWEN3PWEN2PWEN1 0000 0000 MC68HC11KW1 TPG ...
Page 195
... This register can be written at any time, and the written value will take effect from the start of the next PWM timer cycle. Reads of this register return the most recent value written. MC68HC11KW1 bit 7 bit 6 ...
Page 196
... PWDTYx PWPERx Figure 9-7 PWM duty cycle TIMING SYSTEM State bit 3 bit 2 bit 1 bit 0 on reset (3) (2) (1) (bit 0) 1111 1111 (3) (2) (1) (bit 0) 1111 1111 (3) (2) (1) (bit 0) 1111 1111 (3) (2) (1) (bit 0) 1111 1111 MC68HC11KW1 TPG ...
Page 197
... The analog-to-digital converter system consists of a single 10-bit successive approximation type converter and a 16-channel multiplexer. Ten of the channels are connected to pins on the MC68HC11KW1 (ports E and G), two are unused and the remaining four channels are dedicated to internal reference points or test functions. The A/D converter shares input pins with port E and ...
Page 198
... CC, CB, CA) in the ADCTL register. The CONV8 bit selects either four or eight conversions. All “reserved” channels are connected to V MOTOROLA 10-2 converts to $0000. An input voltage greater than V RL ANALOG-TO-DIGITAL CONVERTER converts to $FFC0 (full scale) and RH will convert the supply voltage and RH MC68HC11KW1 . RL TPG ...
Page 199
... SCAN bit determines whether continuous or single scanning is selected. The channel is selected by the CD – CA bits in the ADCTL register. If channels eight and nine are selected, then the result registers previously used for two of the other channels become overwritten with channel eight and nine results. MC68HC11KW1 ANALOG-TO-DIGITAL CONVERTER CONV8 = 0 Channel signal ...
Page 200
... CC). In the second two variations, the CONV8 bit is set and a group of eight channels is selected, depending on the state of the CD bit. The state of the SCAN bit determines whether continuous or single scanning is selected. Refer to Table 10-1. MOTOROLA 10-4 ANALOG-TO-DIGITAL CONVERTER TPG MC68HC11KW1 ...