AD1847JST Analog Devices, AD1847JST Datasheet
AD1847JST
Specifications of AD1847JST
Related parts for AD1847JST
AD1847JST Summary of contents
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... GAIN/ATTEN R /MUTE REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. ...
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AD1847–SPECIFICATIONS STANDARD TEST CONDITIONS UNLESS OTHERWISE NOTED Temperature 25 Digital Supply (V ) 5.0 DD Analog Supply (V ) 5.0 CC Word Rate ( Input Signal 1007 Analog Output Passband 20 FFT Size 4096 V 2.4 IH ...
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ANALOG-TO-DIGITAL CONVERTERS Resolution Dynamic Range (–60 dB Input, THD+N Referenced to Full Scale, A-Weighted) THD+N (Referenced to Full Scale) Signal-to-Intermodulation Distortion† ADC Crosstalk† Line Inputs (Input L, Ground R, Read R; Input R, Ground L, Read L) Line1 to Line2 ...
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AD1847 SYSTEM SPECIFICATIONS System Frequency Response† (Line In to Line Out kHz) Differential Nonlinearity† Phase Linearity Deviation† STATIC DIGITAL SPECIFICATIONS High Level Input Voltage ( Digital Inputs XTAL1/2I Low Level Input Voltage (V ) ...
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... R_LINE1 CONNECT –5– AD1847 ORDERING GUIDE Temperature Package Range Description +70 C 44-Lead PLCC +70 C 44-Lead TQFP WARNING! ESD SENSITIVE DEVICE 44-Lead TQFP 1 PIN 1 IDENTIFIER 2 TSI AD1847JST Top View 8 (Not to Scale) 9 REFI 10 REF 11 Package Option* P-44A ST- GNDD 31 XCTL1 30 XCTL0 29 GNDD ...
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AD1847 PIN DESCRIPTIONS Parallel Interface Pin Name PLCC TQFP I/O SCLK 1 39 I/O SDFS 6 44 I/O SDI SDO RESET PWRDOWN TSO 7 ...
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Miscellaneous Pin Name PLCC TQFP I/O XTAL1I XTAL1O XTAL2I XTAL2O XCTL1:O 37 & & REF REFI ...
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AD1847 Changes in DAC output attenuation take effect only on zero crossings of the digital signal, thereby eliminating “zipper” noise on playback. Each channel has its own independent zero-crossing detector and attenuator change control circuitry. A timer guar- antees that ...
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CONTROL REGISTERS Control Register Mapping The AD1847 has six 16-bit and thirteen 8-bit on-chip user- accessible control registers. Control information is sent to the AD1847 in the 16-bit Control Word. Status information is sent from the AD1847 in the 16-bit ...
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AD1847 Control Word (16-Bit) Data 15 Data 14 Data 13 CLOR MCE Data 7 Data 6 DATA7 DATA6 DATA5 DATA7:0 Index Register Data. These bits are the data for the desired AD1847 Index Register referenced by the Index Address. Written ...
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Status Word (16-Bit) Data 15 Data 14 res res Data 7 Data 6 res res INIT Initialization. This bit is an indication to the host that frame syncs will stop and the serial bus will be shut down. INIT is ...
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AD1847 Index Readback (16-Bit) Data 15 Data 14 CLOR MCE Data 7 Data 6 DATA7 DATA6 DATA7:0 Index Register Data. These bits are the readback data from the desired AD1847 Index Register referenced by the Index Address from the previous ...
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Left Input Control Register (Index Address 0) IA3:0 Data 7 Data 6 0000 LSS1 LSS0 LIG3:0 Left Input Gain Select. The least significant bit of this 16-level gain select represents +1.5 dB. Maximum gain is +22.5 dB. res Reserved for ...
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AD1847 Left Auxiliary #2 Input Control Register (Index Address 4) IA3:0 Data 7 Data 6 0100 LMX2 res LX2G4:0 Left Auxiliary #2 Gain Select. The least significant bit of this 32-level gain/attenuate select represents –1.5 dB. LX2G4 produces ...
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Data Format Register (Index Address 8) IA3:0 Data 7 Data 6 1000 res FMT The contents of this register can NOT be changed except when the AD1847 is in the Mode Change Enable (MCE) state (i.e., the MCE bit in ...
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AD1847 Interface Configuration Register (Index Address 9) IA3:0 Data 7 Data 6 1001 res res PEN Playback Enable. This bit will enable the playback of data in the format selected. PEN may be set and reset without setting the MCE ...
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Miscellaneous Information Register (Index Address 12) IA3:0 Data 7 Data 6 1100 FRS TSSEL The Miscellaneous Information Register can only be changed when the AD1847 is in the Mode Change Enable (MCE) state. Changes to this register are updated at ...
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... DSP drivers for slots 0, 1 Playback Data and 2 (and slots 16, 17, and 18). Right Processed Playback Data An application note is available from Analog Devices with addi- DSP Status tional information on interfacing to the AD1847 serial port. Left Processed This application note can be obtained through your local Ana- ...
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Control Word Data 15 Data 14 CLOR MCE Data 7 Data 6 DATA7 DATA6 Left Playback Data Data 15 Data 14 DATA15 DATA14 Data 7 Data 6 DATA7 DATA6 Right Playback Data Data 15 Data 14 DATA15 DATA14 Data 7 ...
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AD1847 IA3:0 Data 7 Data 6 0000 LSS1 LSS0 0001 RSS1 RSS0 0010 LMX1 res 0011 RMX1 res 0100 LMX2 res 0101 RMX2 res 0110 LDM res 0111 RDM res 1000 res FMT 1001 res res 1010 XCTL1 XCTL0 1011 ...
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MHz 2 XTAL1I,O XTAL2I,O SCLK SDFS AD1847 SDI (MASTER) SDO TSO CLKOUT TSI XTAL2I SCLK XTAL1O SDFS XTAL2O SDI (SLAVE 1) SDO TSO XTAL1I TSI XTAL2I SCLK XTAL1O XTAL2O N/C SDFS SDI (SLAVE 2) SDO TSO XTAL1I Figure ...
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AD1847 When the AD1847 is in bus slave mode (BM = LO), the TSI pin should be connected to the TSO pin of the AD1847 master or slave which has been assigned to the preceding time slots. The signal on ...
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... APPLICATIONS CIRCUITS The AD1847 Stereo Codec has been designed to require a mini- mum of external circuitry. The recommended circuits are shown in Figures 14 through 22. Analog Devices estimates that the to- tal cost of all the components shown in these Figures, including crystals less than $3 in 10,000 quantities. ...
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AD1847 Circuits for 2 V line-level inputs and auxiliaries are shown in rms Figure 14 and Figure 15. Note that these are divide-by-two resistive dividers. The input resistor and 560 pF (1000 pF) capacitor provide the single-pole of antialias filtering ...
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... F Figure 22. Recommended Power Supply Bypassing REV. B Analog Devices recommends a split ground plane as shown in Figure 23. The analog plane and the digital plane are connected directly under the AD1847. Splitting the ground plane directly under the SoundPort Codec is optimal because analog pins will ...
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AD1847 FREQUENCY RESPONSE PLOTS 10 0 –10 –20 –30 –40 –50 dB –60 –70 –80 –90 –100 –110 –120 0.0 0.1 0.2 0.3 0.4 0.5 0.6 SAMPLE FREQUENCY – F Figure 24. AD1847 Analog-to-Digital Frequency Response (Full-Scale Line-Level Inputs, 0 ...
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SCLK SDFS PD1 H BIT 15 BIT 14 SDI t DV SDO BIT 14 BIT 15 Figure 28. Time Slot Timing Diagram SCLK SDFS t PD1 SDI SDO LAST VALID TIME SLOT ...
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AD1847 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 44-Lead PLCC (P-44A) 0.048 (1.21) 0.056 (1.42) 0.042 (1.07) 0.042 (1.07 PIN 1 39 IDENTIFIER 0.048 (1.21) 0.042 (1.07) TOP VIEW 0.020 0.656 (16.66) ...