LXT388LE Intel Corporation, LXT388LE Datasheet

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LXT388LE

Manufacturer Part Number
LXT388LE
Description
Communications, Dual T1/E1/J1 Transceiver
Manufacturer
Intel Corporation
Datasheet

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LXT388
Dual T1/E1/J1 Transceiver
The LXT388 is a dual short haul Pulse Code Modulation (PCM) transceiver for use in both
1.544 Mbps (T1) and 2.048 Mbps (E1) applications. It incorporates four receivers and two
transmitters in a single LQFP-100 package.
The transmit drivers provide low impedance independent of the transmit pattern and supply
voltage variations. The LXT388 transmits shaped waveforms meeting G.703 and T1.102
specifications. The LXT388 meets the latest transmit return loss specifications, such as ETSI
ETS-300166.
The LXT388 differential receivers provide high noise margin for T1/E1 short-haul operation. In
addition, the LXT388 includes two extra receiver/jitter attenuation blocks that can be used for
Driver Performance Monitoring (DPM) in the active channels. These blocks can also be used to
provide jitter attenuation in the receive and transmit paths simultaneously.
Jitter attenuation performance meets the latest international specifications such as CTR12/13.
The jitter attenuator was optimized for Synchronous Optical NETwork/Synchronous Digital
Hierarchy (SONET/SDH) applications including a 32/64 bit FIFO and a second order DPLL.
The LXT388 includes Intel
increase quality of service and eliminates relays in redundancy and 1+1 protection applications.
Fast tristate-able drivers and a constant delay jitter attenuator are critical to achieving Intel
HPS.
Applications
Product Features
As of January 15, 2001, this document replaces the Level One document
LXT388 — Dual T1/E1/J1 Transceiver.
SONET/SDH tributary interfaces
Digital cross connects
Public/private switching trunk line
interfaces
Driver Performance Monitor (DPM)
Tx and Rx Jitter Attenuator
Single rail 3.3V supply with 5V tolerant
inputs
Superior crystal-less jitter attenuator
— Meets ETSI CTR12/13, ITU G.736,
— Optimized for SONET/SDH
— Constant throughput delay jitter
G.742, G.823 and AT&T Pub 62411
specifications
applications, meets ITU G.783 mapping
jitter specification
attenuator
Hitless Protection Switching (Intel HPS) feature which helps
Microwave transmission systems
M13, E1-E3 MUX
Intel
relays
HDB3, B8ZS, or AMI line encoder/decoder
Analog/digital and remote loopback testing
functions
LOS per ITU G.775, ETS 300 233 and
T1.231
JTAG Boundary Scan test port per IEEE
1149.1
100 pin LQFP package
Low power consumption of 150mW per
channel (typical)
HPS for 1 to 1 protection without
Order Number:
Datasheet
February 2001
249269-002

Related parts for LXT388LE

LXT388LE Summary of contents

Page 1

LXT388 Dual T1/E1/J1 Transceiver The LXT388 is a dual short haul Pulse Code Modulation (PCM) transceiver for use in both 1.544 Mbps (T1) and 2.048 Mbps (E1) applications. It incorporates four receivers and two transmitters in a single LQFP-100 package. ...

Page 2

... Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800- 548-4725 or by visiting Intel’s website at http://www.intel.com. Copyright © Intel Corporation, 2001 *Third-party brands and names are the property of their respective owners. ...

Page 3

Contents 1.0 Pin Assignments and Signal Description 2.0 Functional Description 2.1 Initialization..........................................................................................................21 2.1.1 Reset Operation .....................................................................................21 2.2 Receiver ..............................................................................................................22 2.2.1 Loss of Signal Detector ..........................................................................23 2.2.2 Alarm Indication Signal (AIS) Detection .................................................23 2.2.3 In Service Code Violation Monitoring .....................................................24 2.3 ...

Page 4

LXT388 — Dual T1/E1/J1 Transceiver 5.0 Test Specifications 5.1 Recommendations and Specifications ................................................................ 77 6.0 Mechanical Specifications Figures 1 LXT388 Block Diagram ......................................................................................... 9 2 LXT388 Low-Profile Quad Flate Package (LQFP) 100 Pin Assignments and Package Markings............................................................................................... 10 3 Pullup ...

Page 5

Tables 1 Assignments and Signal Descriptions - Power and N/C .....................................11 2 Pin Assignments and Signal Descriptions - Digital Interface...............................11 3 Pin Assignments and Signal Descriptions - Analog Interface .............................15 4 Pin Assignments and Signal Descriptions - JTAG Port.......................................15 5 ...

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LXT388 — Dual T1/E1/J1 Transceiver 50 Intel Mode Read Timing Characteristics ............................................................. 63 51 JTAG Timing Characteristics .............................................................................. 63 52 Intel Mode Write Timing Characteristics ............................................................. 65 53 Motorola Bus Read Timing Characteristics......................................................... 67 54 Motorola Mode Write Timing Characteristics ...

Page 7

Revision History Revision Date -002 02/12/01 Datasheet Dual T1/E1/J1 Transceiver — LXT388 Description Figure 2, changed pin 70 from TCK to TDI. Figure 2, changed pin 71 from GND to TCK. Moved Product Features from page 9 to page 1. ...

Page 8

LXT388 — Dual T1/E1/J1 Transceiver 8 Datasheet ...

Page 9

Figure 1. LXT388 Block Diagram JTAG SERIAL/ PARALLEL PORT RTIP RRING TTIP TRING RTIP RRING MONITORING / JA Datasheet Dual T1/E1/J1 Transceiver — LXT388 HARDWARE / SOFTWARE CONTROL LOS DATA SLICER JITTER DATA CLOCK ATTENUATOR CLOCK RECOVERY ...

Page 10

... Part # Unique identifier for this product family. Rev # Identifies the particular silicon “stepping” — refer to the specification update for additional stepping information. Lot # Identifies the batch. FPO # Identifies the Finish Process Order. 10 Rev # LXT388LE XX XXXXXX XXXXXXXX Definition 75 VCC 74 GND 73 TDO ...

Page 11

Table 1. Assignments and Signal Descriptions - Power and N/C Pin # 1 Symbol I/O LQFP 5, 7, 10, 11, 65, 66, GND S Power Supply Ground. Connect all pins to power supply ground VCC ...

Page 12

LXT388 — Dual T1/E1/J1 Transceiver Table 2. Pin Assignments and Signal Descriptions - Digital Interface (Continued) Pin # 1 Symbol I/O LQFP RPOS1 RDATA1 DO RNEG1 BPV1 DO 18 LOS1 DO 19 TCLK0 DI DI TPOS0/ ...

Page 13

Table 2. Pin Assignments and Signal Descriptions - Digital Interface (Continued) Pin # 1 Symbol I/O LQFP Receive Clock. Normal Mode: This pin provides the recovered clock from the signal received at RTIP and RRING. Under LOS conditions there is ...

Page 14

LXT388 — Dual T1/E1/J1 Transceiver Table 2. Pin Assignments and Signal Descriptions - Digital Interface (Continued) Pin # 1 Symbol I/O LQFP 58 LOS2 DO RNEG2 BPV2 DO RPOS2 RDATA2 DO 61 RCLK2 DO TNEG2/ DI ...

Page 15

Table 3. Pin Assignments and Signal Descriptions - Analog Interface Pin # 1 Symbol I/O LQFP Transmit Tip. Transmit Ring. 27 TTIP0 AO These pins are differential line driver outputs. TTIP and TRING will be in high impedance 28 TRING0 ...

Page 16

LXT388 — Dual T1/E1/J1 Transceiver Table 5. Pin Assignments and Signal Descriptions - Microprocessor/Configuration Pin # 1 Symbol I/O LQFP MOT/INTL CODEN RD/ DI LEN1 DI DS SDI/ ...

Page 17

Table 5. Pin Assignments and Signal Descriptions - Microprocessor/Configuration Pin # 1 Symbol I/O LQFP Data Transfer acknowledge (Motorola Mode). Ready (Intel mode). Serial Data Output (Serial Mode). Motorola Mode A Low signal during a databus read operation indicates that ...

Page 18

LXT388 — Dual T1/E1/J1 Transceiver Table 5. Pin Assignments and Signal Descriptions - Microprocessor/Configuration Pin # 1 Symbol I/O LQFP DI: Digital Input; DO: ...

Page 19

Table 5. Pin Assignments and Signal Descriptions - Microprocessor/Configuration Pin # 1 Symbol I/O LQFP Loopback Mode Select/Parallel Data bus. Host Mode: When a non-multiplexed microprocessor interface is selected, these pins function as a bi- directional 8-bit data port. When ...

Page 20

LXT388 — Dual T1/E1/J1 Transceiver Table 5. Pin Assignments and Signal Descriptions - Microprocessor/Configuration Pin # 1 Symbol I/O LQFP CS JASEL DI 1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: ...

Page 21

Functional Description The LXT388 is a fully integrated dual line interface unit designed for T1 1.544 Mbps and E1 2.048 Mbps short haul applications. It features two complete transceivers and two additional receiver and jitter attenuation blocks. These block ...

Page 22

LXT388 — Dual T1/E1/J1 Transceiver Figure 3. Pullup Resistor to RESET VCC 1K 100 2.2 Receiver The four receivers in the LXT388 are identical. The following paragraphs describe the operation of one. The twisted-pair input is received via a 1:2 ...

Page 23

Loss of Signal Detector The loss of signal detector in the LXT388 uses a dedicated analog and digital loss of signal detection circuit independent of its internal data slicer comparators and complies to the latest ITU G.775 ...

Page 24

LXT388 — Dual T1/E1/J1 Transceiver 2.2.2.1 E1 Mode One detection mode suitable for both ETSI and ITU is available when the cleared to zero. If the LACS register bit is set to one, see errata 10.3 to implement this. ETSI ...

Page 25

Figure 4. 50% AMI Encoding TTIP Bit Cell 1 TRING Each output driver is supplied by a separate power supply (TVCC and TGND). The transmit pulse shaper is bypassed if no MCLK is supplied while TCLK is pulled high. In ...

Page 26

LXT388 — Dual T1/E1/J1 Transceiver Table 6. Line Length Equalizer Inputs LEN2 LEN1 LEN0 Line length from LXT388 to DSX-1 cross-connect ...

Page 27

During a long string of spaces, a short-induced overcharge eventually bleeds off, clearing the DFM flag. Note: Unterminated lines of adequate length ...

Page 28

LXT388 — Dual T1/E1/J1 Transceiver Figure 5. External Transmit/Receive Line Circuitry TVCC 3.3V VCC 0.1 F GND 1 Common decoupling capacitor for all TVCC and TGND pins. 2 Typical value. Adjust for actual board parasitics to obtain ...

Page 29

Driver Performance Monitoring Figure 6. TRANSMITTER # 0/1 LXT388 RECEIVER # 2/3 LOS / DPM 2.6 Driver Performance Monitor The two additional receiver blocks in the LXT388 can be used to monitor the transmitter performance in channels 0 and 1 ...

Page 30

LXT388 — Dual T1/E1/J1 Transceiver Note: T1/E1 receiver operation in channels 2 and 3 is determined by the LEN settings as described in Table 6 on page 26. 2.7 Jitter Attenuation A digital Jitter Attenuation Loop (JAL) combined with a ...

Page 31

Figure 7. Jitter Attenuator Loop TPOS RPOSi TNEG RNEGi TCLK RCLKi JASEL0 MCLK In Host Mode, the Global Control Register (GCR) determines whether the JAL is positioned in the receive path, transmit path or disabled. In Hardware Mode, ...

Page 32

LXT388 — Dual T1/E1/J1 Transceiver Figure 8. Transmit and Receive Jitter Attenuation TCLK TPOS TNEG RCLK RPOS RNEG LOS 1 TCLK TPOS TNEG RCLK RPOS RNEG LOS/DPM * If Enabled Inverter not necessary if CLKE is high. However ...

Page 33

Figure 9. Analog Loopback TCLK TPOS TNEG RCLK RPOS RNEG * If Enabled 2.8.2 Digital Loopback The digital loopback function is available in software and Hardware mode. When selected, the transmit clock and data inputs (TCLK, TPOS & TNEG) are ...

Page 34

LXT388 — Dual T1/E1/J1 Transceiver Figure 11. Remote Loopback TCLK TPOS TNEG RCLK RPOS RNEG * If Enabled Note: In data recovery mode, the pulse template cannot be guaranteed while in a remote loopback. 2.8.4 Transmit All Ones (TAOS) In ...

Page 35

Figure 13. TAOS with Digital Loopback MCLK TCLK TPOS TNEG RCLK RPOS RNEG * If Enabled Figure 14. TAOS with Analog Loopback MCLK TCLK TPOS TNEG RCLK RPOS RNEG * If Enabled 2.9 Intel Hitless Protection Switching (Intel HPS) The ...

Page 36

LXT388 — Dual T1/E1/J1 Transceiver Table 8. Operation Mode Summary (Continued) MCLK TCLK LOOP Clocked L Open Clocked L Clocked L Clocked H Open Clocked H Clocked H L Clocked Open L Clocked L Clocked L H Open L H ...

Page 37

Table 9. Microprocessor Parallel Interface Selection MUX MOT/INTL Low Low Low High High Low High High The interface includes an address bus (A4 - A0) and a data bus (D7 - D0) for non-multiplexed operation and an 8-bit address/data bus ...

Page 38

LXT388 — Dual T1/E1/J1 Transceiver 2.12.2 Intel Interface The Intel interface is selected by asserting the MOT/INTL pin High. The LXT388 supports non- multiplexed interfaces with separate address and data pins when MUX is asserted Low, and multiplexed interfaces when ...

Page 39

AIS (013H). Reading either status monitors register will clear its corresponding interrupts on the rising edge of the read or data strobe. When all pending interrupts are cleared, the INT pin goes High. 2.14 Serial Host Mode ...

Page 40

LXT388 — Dual T1/E1/J1 Transceiver 3.0 Register Descriptions Table 10. Serial and Parallel Port Register Addresses Name Symbol ID Register Analog Loopback ALOOP Remote Loopback RLOOP TAOS Enable TAOS LOS Status Monitor LOS DFM Status Monitor DFM LOS Interrupt Enable ...

Page 41

Table 11. Register Bit Names (Continued) Register Name Sym RW TAOS Enable TAOS R/W LOS Status Monitor LOS R DFM Status Monitor DFM R LOS Interrupt Enable LIE R/W DFM Interrupt Enable DIE R/W LOS Interrupt Status LIS R DFM ...

Page 42

LXT388 — Dual T1/E1/J1 Transceiver Table 13. Analog Loopback Register, ALOOP (01H) Bit Name 1-0 AL1-AL0 Setting a bit to “1” enables analog local loopback for transceivers 1- 0 respectively. 7-2 - Write “0” to these positions for normal operation. ...

Page 43

Table 18. LOS Interrupt Enable Register, LIE (06H) 1 Bit Name 3-0 LIE1-LIE0 Receiver 3-0 LOS interrupts are enabled by writing a “1” to the respective bit. 7-4 - Write “0” to these positions for normal operation power-up ...

Page 44

LXT388 — Dual T1/E1/J1 Transceiver Table 24. Digital Loopback Register, DL (0CH) 1 Bit Name 3-0 DL3-DL0 Setting a bit to “1” enables digital loopback for the respective channel power up all register bits are set to “0”. ...

Page 45

Table 27. Global Control Register, GCR (0FH) (Continued) 1 Bit Name This bit selects the zero suppression code for unipolar operation mode: 4 CODEN 0 = B8ZS/HDB3 (T1/E1 respectively AMI This bit controls enables/disables the short circuit protection ...

Page 46

LXT388 — Dual T1/E1/J1 Transceiver Table 30. Output Enable Register, OER (12H) 1 Bit Name 1-0 OE1 - OE0 Setting a bit to “1” tristates the output driver of the corresponding transceiver. 7-2 - Write “0” to these positions for ...

Page 47

JTAG Boundary Scan 4.1 Overview The LXT388 supports IEEE 1149.1 compliant JTAG boundary scan. Boundary scan allows easy access to the interface pins for board testing purposes. In addition to the traditional IEE1149.1 digital boundary scan capabilities, the LXT388 ...

Page 48

LXT388 — Dual T1/E1/J1 Transceiver Table 34. TAP State Description State Test Logic Reset Run -Test/Idle Capture - DR Shift - DR Update - DR Capture - IR Shift - IR Update - IR Pause - IR Pause - DR ...

Page 49

Figure 17. JTAG State Diagram 1 TEST-LOGIC RESET RUN TEST/IDLE 4.4 JTAG Register Description The following paragraphs describe each of the registers represented in Datasheet Dual T1/E1/J1 Transceiver — LXT388 1 SELECT- CAPTURE- ...

Page 50

LXT388 — Dual T1/E1/J1 Transceiver 4.4.1 Boundary Scan Register (BSR) The BSR is a shift register that provides access to all the digital I/O pins. The BSR is used to apply and read test patterns to/from the board. Each pin ...

Page 51

Table 35. Boundary Scan Register (BSR) (Continued) Pin I/O Bit # Signal Type Symbol LOOP0 I/O LOOP0 I/O LOOP1 I/O LOOP1 I/O LOOP2 I/O LOOP2 I/O LOOP3 I/O LOOP3 I/O 1 LOOP4 I/O 1 LOOP4 I/O ...

Page 52

LXT388 — Dual T1/E1/J1 Transceiver Table 35. Boundary Scan Register (BSR) (Continued) Pin I/O Bit # Signal Type RNEG1 O LOS1 O TCLK0 I TPOS0 I TNEG0 I RCLK0 O RPOS0 O N/A - RNEG0 O LOS0 O 1. LOOP4 ...

Page 53

Table 37 shows the 8 possible control codes and the corresponding operation on the analog port. The Analog Test Port can be used to verify continuity across the coupling transformers primary winding. The Analog Test Port can be used to ...

Page 54

LXT388 — Dual T1/E1/J1 Transceiver Figure 18. Analog Test Port Application RTIP3 RRING3 n/c n/c RTIP2 RRING2 n/c n/c RTIP1 RRING1 TTIP1 TRING1 RTIP0 1K RRING0 1K TTIP0 TRING0 AT2 AT1 54 JTAG Port ASR Register Receiver w/JA 3 Receiver ...

Page 55

Test Specifications Table 39 through Table 58 specifications of the LXT388 and are guaranteed by test except, where noted, by design. The minimum and maximum values listed in recommended operating conditions specified in Table Table 39. Absolute Maximum Ratings ...

Page 56

LXT388 — Dual T1/E1/J1 Transceiver Table 40. Recommended Operating Conditions (Continued) Parameter Average Transmitter Power Supply Current Mode Output load at TTIP and TRING Mode TVCC Load 75 E1 3.3V 120 3 T1 3.3V 100 75 ...

Page 57

Table 41. DC Characteristics (Continued) Parameter Tri state output current Line short circuit current Input Leakage (TMS, TDI, TRST) Table 42. E1 Transmit Transmission Characteristics Parameter 75 Output pulse amplitude 120 75 Peak voltage of a space 120 Transmit amplitude ...

Page 58

LXT388 — Dual T1/E1/J1 Transceiver Table 43. E1 Receive Transmission Characteristics (Continued) Parameter Loss of signal threshold LOS hysteresis Consecutive zeros before loss of signal LOS reset Low limit 1Hz to 20Hz input jitter 20Hz to 2.4kHz 1 tolerance 18kHz ...

Page 59

Table 44. T1 Transmit Transmission Characteristics (Continued) Parameter 51kHz to 102 kHz Transmit return 102 kHz to 2.048 MHz 1 loss 2.048 MHz to 3.072 MHz Bipolar mode Transmit path delay Unipolar mode 1. Guaranteed by design and other correlation ...

Page 60

LXT388 — Dual T1/E1/J1 Transceiver Table 46. Jitter Attenuator Characteristics Parameter JACF = 0 E1 jitter attenuator 3dB corner frequency, host 1 mode JACF = 1 JACF = 0 T1 jitter attenuator 3dB corner frequency, host 1 mode JACF = ...

Page 61

Table 47. Analog Test Port Characteristics Parameter Sym 3 dB bandwidth At13db Input voltage range At1iv Output voltage range At2ov Figure 19. Transmit Clock Timing Diagram TCLK TPOS TNEG Table 48. Transmit Timing Characteristics Parameter Master clock frequency Master clock ...

Page 62

LXT388 — Dual T1/E1/J1 Transceiver Table 49. Receive Timing Characteristics Parameter Clock recovery capture range 1 Receive clock duty cycle 1 Receive clock pulse width Receive clock pulse width Low time Receive clock pulse width High time 4 Rise/fall time ...

Page 63

Table 50. Intel Mode Read Timing Characteristics 2 Parameter Address setup time to latch Valid address latch pulse width Latch active to active read setup time Chip select setup time to active read Chip select hold time from inactive read ...

Page 64

LXT388 — Dual T1/E1/J1 Transceiver Figure 22. Non-Multiplexed Intel Mode Read Timing ALE (pulled High INT Tristate RDY 64 tSAR ADDRESS tSCSR tVRD tPRD tDRDY tVRDY tHAR tHCSR tZRD DATA OUT tINT ...

Page 65

Figure 23. Multiplexed Intel Read Timing tVL ALE CS RD tSALR ADDRESS AD7-AD0 INT tDRDY Tristate RDY Table 52. Intel Mode Write Timing Characteristics 2 Parameter Address setup time to latch Valid address latch pulse width Latch active to active ...

Page 66

LXT388 — Dual T1/E1/J1 Transceiver Table 52. Intel Mode Write Timing Characteristics (Continued) 2 Parameter Valid write signal pulse width Inactive write to inactive INT delay time 3 Chip select to RDY delay time Active ready Low time 3 Inactive ...

Page 67

Figure 25. Multiplexed Intel Mode Write Timing ALE tVL CS WR tSALW AD7-AD0 ADDRESS INT tDRDY Tristate RDY Table 53. Motorola Bus Read Timing Characteristics 2 Parameter Address setup time to address or data strobe Address hold time from address ...

Page 68

LXT388 — Dual T1/E1/J1 Transceiver Figure 26. Non-Multiplexed Motorola Mode Read Timing A4-A0 ADDRESS tSAR AS (pulled High) tSRW R D7-D0 INT ACK 68 tHAR tSCS tVDS tPDS DATA OUT tDACKP tPACK tHRW tHCS tDZ tINT tDACK Datasheet ...

Page 69

Figure 27. Multiplexed Motorola Mode Read Timing AS tSRW R/W CS tASDS DS tSAR D7-D0 ADDRESS INT ACK Table 54. Motorola Mode Write Timing Characteristics 2 Parameter Address setup time to address strobe Address hold time to address strobe Valid ...

Page 70

LXT388 — Dual T1/E1/J1 Transceiver Table 54. Motorola Mode Write Timing Characteristics (Continued) 2 Parameter Data strobe inactive to address strobe inactive delay Active data strobe to ACK output enable time DS asserted to ACK asserted delay 1. Typical figures ...

Page 71

Figure 29. Multiplexed Motorola Mode Write Timing AS tSRW R/W CS tASDS DS tSAS D7-D0 ADDRESS INT ACK Table 55. Serial I/O Timing Characteristics Parameter Rise/fall time any pin SDI to SCLK setup time SCLK to SDI hold time SCLK ...

Page 72

LXT388 — Dual T1/E1/J1 Transceiver Figure 30. Serial Input Timing SCLK t DC SDI Figure 31. Serial Output Timing CLKE = SCLK CS SDO CLKE = SCLK ...

Page 73

Table 57. G.703 2.048 Mbit/s Pulse Mask Specifications Parameter Test load impedance Nominal peak mark voltage Nominal peak space voltage Nominal pulse width Ratio of positive and negative pulse amplitudes at center of pulse Ratio of positive and negative pulse ...

Page 74

LXT388 — Dual T1/E1/J1 Transceiver Figure 33. T1, T1.102 Mask Templates -0.80 -0.60 -0.40 74 1.20 1.00 0.80 0.60 0.40 0.20 0.00 -0.20 0.00 0.20 0.40 -0.20 -0.40 -0.60 Tim e [UI] 0.60 0.80 1.00 1.20 Datasheet ...

Page 75

Figure 34. Jitter Tolerance Performance 1000 UI 100 4.9 Hz AT&T 62411, Dec 1990 (T1 1 Datasheet Dual T1/E1/J1 Transceiver — LXT388 ...

Page 76

LXT388 — Dual T1/E1/J1 Transceiver Figure 35. Jitter Transfer Performance -10 dB -20 dB -30 dB -40 dB - 3Hz 0 40Hz =2.5 Hz ...

Page 77

Figure 36. Output Jitter for CTR12/13 applications 0.2 0.15 0.1 0. 100 Hz 5.1 Recommendations and Specifications AT&T Pub 62411 ANSI T1.102 - 199X Digital Hierarchy Electrical Interface ANSI T1.231 - 1993 Digital Hierarchy Layer ...

Page 78

... LXT388 — Dual T1/E1/J1 Transceiver 6.0 Mechanical Specifications Figure 37. Low Quad Flat Package (LQFP) Dimensions 100 Pin LQFP • Part Number LXT388LE • Extended Temperature Range (- 16.00 BSC 14.00 BSC 12.00 BSC 1.60 0.05 min max 1.40 ±0.05 0.15 max 78 ALL DIMENSIONS IN MILLIMETERS All dimensions and tolerances conform to ANSI Y14 ...

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