MC68HC912B32 Motorola, MC68HC912B32 Datasheet
MC68HC912B32
Specifications of MC68HC912B32
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MC68HC912B32 Summary of contents
Page 1
... EEPROM on the same device. System resource mapping, clock generation, interrupt control and bus interfacing are managed by the Lite integration module (LIM). The MC68HC912B32 has full 16-bit data paths throughout, however, the multiplexed external bus can operate in an 8-bit narrow mode so single 8-bit wide memory can be interfaced for lower cost systems ...
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... On-Chip Hardware Breakpoints 1.2 Ordering Information The MC68HC912B32 is packaged in 80-pin quad flat pack (QFP) packaging and is shipped in two-piece sample packs, 50-piece trays, or 250-piece bricks. Operating temperature range and voltage require- ments are specified when ordering the MC68HC912B32 device. Refer to Table 1 for part numbers. ...
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... Section 1 Introduction 1.1 Features ......................................................................................................................................1 1.2 Ordering Information ...................................................................................................................2 1.3 MC68HC912B32 Block Diagram .................................................................................................5 2 Central Processing Unit 2.1 Programming Model ....................................................................................................................6 2.2 Data Types ..................................................................................................................................7 2.3 Addressing Modes .......................................................................................................................7 2.4 Indexed Addressing Modes .........................................................................................................8 2.5 Opcodes and Operands ..............................................................................................................8 3 Pinout and Signal Descriptions 3.1 MC68HC912B32 Pin Assignments .............................................................................................9 3 ...
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... J1850 Bus Errors .....................................................................................................................106 15 Analog-To-Digital Converter 15.1 Functional Description .............................................................................................................108 15.2 ATD Registers .........................................................................................................................108 15.3 ATD Mode Operation ..............................................................................................................114 16 Development Support 16.1 Instruction Queue ....................................................................................................................115 16.2 Background Debug Mode ........................................................................................................115 16.3 Breakpoints .............................................................................................................................123 16.4 Instruction Tagging ..................................................................................................................127 MOTOROLA 4 Page 108 115 MC68HC912B32 MC68HC912B32TS/D ...
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... PE4 ECLK PE5 IPIPE0 / MODA PE6 IPIPE1 / MODB PE7 DBE MULTIPLEXED ADDRESS/DATA BUS DDRA PORT A WIDE BUS NARROW BUS Figure 1 MC68HC912B32 Block Diagram MC68HC912B32 MC68HC912B32TS/D ATD CONVERTER COP WATCHDOG CLOCK MONITOR BREAK POINTS TIMER AND PULSE ACCUMULATOR LITE SCI INTEGRATION MODULE ...
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... The half-carry flag is used only for BCD arithmetic operations. The and C status bits allow for branching based on the results of a previous operation. MOTOROLA 8-BIT ACCUMULATORS A & 16-BIT DOUBLE ACCUMULATOR INDEX REGISTER INDEX REGISTER STACK POINTER PC 0 PROGRAM COUNTER CONDITION CODE REGISTER Figure 2 Programming Model HC12 PROG MODEL MC68HC912B32 MC68HC912B32TS/D ...
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... Indexed-Indirect INST [ oprx16 , xysp ] (16-bit offset) Indexed-Indirect (D accumulator INST [D, xysp ] offset) MC68HC912B32 MC68HC912B32TS/D Abbreviation Description INH Operands (if any) are in CPU registers Operand is included in instruction stream IMM 8- or 16-bit size implied by context Operand is the lower 8-bits of an address in the DIR range $0000 – ...
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... Extension bytes contain additional program information such as addresses, offsets, and immedi- ate data. MOTOROLA 8 Comments rr SP 9-bit with sign in LSB of postbyte( 16-bit +8 = 0111 … 0000 -1 = 1111 … 1000 (16-bit see accumulator D offset indexed-indirect -256 < n < 255 0 < n < 65,535 0 < n < 65,535 MC68HC912B32 MC68HC912B32TS/D ...
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... Pinout and Signal Descriptions 3.1 MC68HC912B32 Pin Assignments The MC68HC912B32 is available in a 80-pin quad flat pack (QFP). Most pins perform two or more func- tions, as described in the 3.3 Signal Descriptions. Figure 3 shows pin assignments. Shaded pins are power and ground. PORT P PP5 ...
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... Power Supply Pins MC68HC912B32 power and ground pins are described below and summarized in Table 4. 3.2.1 Internal Power (V ) and Ground (V DD Power is supplied to the MCU through V duration current demands on the power supply, use bypass capacitors with high-frequency character- istics and place them as close to the MCU as possible. Bypass requirements depend on how heavily the MCU pins are loaded ...
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... RFI. In special peripheral mode the E clock is an input to the MCU. All clocks, including the E-clock, are halted when the MCU is in STOP mode possible to configure the MCU to interface to slow external memory. ECLK can be stretched for such accesses. MC68HC912B32 MC68HC912B32TS CRYSTAL ...
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... The BKGD pin receives and transmits serial background debugging commands. A special self-timing protocol is used. The BKGD pin has an active pull-up when configured as input; BKGD has no pull-up control. Refer to 16 Development Support. MOTOROLA 12 is not needed for normal EEPROM program PP MC68HC912B32 MC68HC912B32TS/D ...
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... In expanded modes this pin is used to enable the drive control of external buses during ex- ternal reads. Use of the DBE is controlled by the NDBE bit in the PEAR register. DBE is enabled out of reset in expanded modes. This pin has an active pull-up during and after reset in single-chip modes. MC68HC912B32 MC68HC912B32TS/D MOTOROLA 13 ...
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... Table 5 MC68HC912B32 Signal Description Summary Pin Name Pin Number PW[3:0] 3–6 ADDR[7:0] 25–18 DATA[7:0] ADDR[15:8] 46–39 DATA[15:8] IOC[7:0] 16–12, 9–7 PAI 16 AN[7:0] 58–51 DBE 26 MODB, MODA 27, 28 IPIPE1, IPIPE0 27, 28 ECLK 29 RESET 32 EXTAL 33 XTAL 34 LSTRB 35 TAGLO 35 R/W 36 IRQ 37 XIRQ 38 BKGD 17 TAGHI ...
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... Port Signals The MC68HC912B32 incorporates eight ports which are used to control and access the various device subsystems. When not used for these purposes, port pins may be used for general-purpose I/O. In ad- dition to the pins described below, each port consists of a data register which can be read and written at any time, and, with the exception of port AD and PE[1:0], a data direction register which controls the direction of each pin ...
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... This port provides eight general-purpose I/O pins when not enabled for input capture and output com- pare in the timer and pulse accumulator subsystem. The TEN bit in the TSCR register enables the timer function. The pulse accumulator subsystem is enabled with the PAEN bit in the PACTL register. MOTOROLA 16 MC68HC912B32 MC68HC912B32TS/D ...
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... If PUPSx bits in the PURDS register are set, the appropriate pull-up de- vice is connected to each port S pin which is programmed as a general-purpose input . If the pin is pro- grammed as a general-purpose output, the pull-up is disconnected from the pin regardless of the state of the individual PUPSx bits. See 13 Serial Interface. MC68HC912B32 MC68HC912B32TS/D MOTOROLA 17 ...
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... Table 6 MC68HC912B32 Port Description Summary Pin Data Direction Port Name Numbers DD Register (Address) Port A 46–39 PA[7:0] DDRA ($0002) Port B 25–18 DDRB ($0003) PB[7:0] Port AD 58–51 PAD[7:0] Port DLC 70–76 PDLC[6:0] DDRDLC ($00FF) PE[1:0] In Port E 26–29, 35–38 PE[7:2] In/Out ...
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... PURDS ($00DB) Port T Pull-up TMSK2 ($008D) Port DLC Pull-up DLCSCR ($00FD) DLCPUE Port AD None BKGD Pull-up — MC68HC912B32 MC68HC912B32TS/D Enable Bit Bit Name Reset State PUPA Disabled RDRIV ($000D) PUPB Disabled RDRIV ($000D) PUPE Enabled RDRIV ($000D) Always Enabled RDRIV ($000D) — ...
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... The register block occupies the first 512 bytes of the 2-Kbyte block. De- fault addressing (after reset) is indicated in the table below. For additional information refer to 5 Oper- ating Modes and Resource Mapping. Table 8 MC68HC912B32 Register Map (Sheet Address Bit 7 ...
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... Table 8 MC68HC912B32 Register Map (Sheet Address Bit 7 6 $0023 Bit 7 6 $0024 Bit 15 14 $0025 Bit 7 6 $0026– $003F $0040 CON23 CON01 PCKA2 $0041 PCLK3 PCLK2 PCLK1 $0042 0 0 $0043 Bit 7 6 $0044 Bit 7 6 $0045 Bit 7 6 $0046 Bit 7 ...
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... Table 8 MC68HC912B32 Register Map (Sheet Address Bit 7 6 $006F PAD7 PAD6 PAD5 $0070 Bit 7 6 $0071 0 0 $0072 Bit 7 6 $0073 0 0 $0074 Bit 7 6 $0075 0 0 $0076 Bit 7 6 $0077 0 0 $0078 Bit 7 6 $0079 0 0 $007A Bit 7 6 $007B ...
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... Table 8 MC68HC912B32 Register Map (Sheet Address Bit 7 6 $0099 Bit 7 6 $009A Bit 15 14 $009B Bit 7 6 $009C Bit 15 14 $009D Bit 7 6 $009E Bit 15 14 $009F Bit 7 6 $00A0 0 PAEN PAMOD $00A1 0 0 $00A2 Bit 15 14 $00A3 Bit 7 6 $00A4– ...
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... Table 8 MC68HC912B32 Register Map (Sheet Address Bit 7 6 $00F2 EEODD EEVEN MARG $00F3 BULKP 0 $00F4 0 0 $00F5 0 0 $00F6 FSTE GADR $00F7 0 0 $00F8 IMSG CLKS $00F9 0 0 $00FA ALOOP DLOOP RX4XE $00FB D7 D6 $00FC ATE RXPOL $00FD 0 0 $00FE 0 PDLC6 ...
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... Operating Modes and Resource Mapping Eight possible operating modes determine the operating configuration of the MC68HC912B32. Each mode has an associated default memory map and external bus configuration. After reset, most system resources can be mapped to other addresses by writing to the appropriate control registers. 5.1 Operating Modes The operating mode out of reset is determined by the states of the BKGD, MODB, and MODA pins dur- ing reset ...
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... EEPROM and Flash EEPROM without interrupting the application code executing in the CPU. This non- intrusive mode uses dead bus cycles to access the memory and in most cases will remain cycle deter- ministic. Refer to 16 Development Support for more details on BDM. MOTOROLA 26 MC68HC912B32 MC68HC912B32TS/D ...
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... This bit controls access to the external bus interface when in wait mode. The module will delay before shutting down in wait mode to allow for final bus activity to complete External bus and registers continue functioning during wait mode External bus is shut down during wait mode. MC68HC912B32 MC68HC912B32TS ...
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... These bits specify the upper five bits of the 16-bit registers address. Write once in normal modes or anytime in special modes. Read anytime. MOTOROLA 28 Table 10 Mapping Precedence Resource 1 BDM ROM (if active) 2 Register Space 3 RAM 4 EEPROM 5 Flash EEPROM 6 External Memory REG13 REG12 REG11 $0011 2 1 Bit MMSWAI MC68HC912B32 MC68HC912B32TS/D ...
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... These bits specify the upper five bits of the 16-bit RAM address. Write once in normal modes or anytime in special modes. Read anytime. 5.3.3 EEPROM Mapping The MC68HC912B32 has 768 bytes of EEPROM which is activated by the EEON bit in the INITEE reg- ister. Mapping of internal EEPROM is controlled by four bits in the INITEE register. After reset EEPROM ad- dress space begins at location $0D00 but can be mapped to any 4-Kbyte boundary within the standard 64-Kbyte address space ...
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... This bit determines the location of the on-chip Flash EEPROM. In expanded modes it is reset to zero. In single-chip modes it is reset to one. If ROMON is zero, this bit has no meaning or effect Flash EEPROM is located from $0000 to $7FFF 1 = Flash EEPROM is located from $8000 to $FFFF MOTOROLA RFSTR0 EXSTR1 EXSTR0 MAPROM ROMON $0013 1 Bit MC68HC912B32 MC68HC912B32TS/D ...
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... The following diagrams illustrate the memory map for each mode of operation immediately after reset. $0000 $0800 $0D00 $8000 $F000 $FF00 $FFC0 VECTORS VECTORS $FFFF EXPANDED SINGLE CHIP NORMAL Figure 6 MC68HC912B32 Memory Map MC68HC912B32 MC68HC912B32TS/D $0000 REGISTERS 512 BYTES RAM MAP TO ANY 2K SPACE $01FF $0200 REGISTER FOLLOWING SPACE 512 BYTES RAM $03FF $0800 ...
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... Bus Control and Input/Output Internally the MC68HC912B32 has full 16-bit data paths, but depending upon the operating mode and control registers, the external bus may be eight or sixteen bits. There are cases where 8-bit and 16-bit accesses can appear on adjacent cycles using the LSTRB signal to indicate 8- or 16-bit data. ...
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... This register determines the primary direction for each port B pin when functioning as a general-purpose I/O port. DDRB is not in the on-chip map in expanded and peripheral modes. Read and write anytime Associated pin is a high-impedance input 1 = Associated pin is an output MC68HC912B32 MC68HC912B32TS PA5 ...
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... Bit 0 PE2 PE1 PE0 – – – R/W IRQ XIRQ $0009 2 1 Bit – – $000A 2 1 Bit Normal 0 – – Expanded Special 1 – – Expanded 0 – – Peripheral Normal 0 – – Single Chip Special 1 – – Single Chip MC68HC912B32 MC68HC912B32TS/D ...
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... PE2 is a general-purpose I/O pin PE2 is configured as the R/W pin. In single-chip modes, RDWE has no effect and PE2 is a gen- eral-purpose I/O pin. R/W is used for external writes. After reset in normal expanded mode disabled. If needed it should be enabled before any external writes. MC68HC912B32 MC68HC912B32TS/D MOTOROLA 35 ...
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... All port B output pins have reduced drive capability. RDPA — Reduced Drive of Port All port A output pins have full drive enabled All port A output pins have reduced drive capability. MOTOROLA PUPE RDPE $000C 1 Bit 0 PUPB PUPA 0 0 $000D 1 Bit 0 RDPB RDPA 0 0 MC68HC912B32 MC68HC912B32TS/D ...
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... Flash EEPROM The 32-Kbyte Flash EEPROM module for the MC68HC912B32 serves as electrically erasable and pro- grammable, non-volatile ROM emulation memory. The module can be used for program code that must either execute at high speed or is frequently executed, such as operating system kernels and standard subroutines can be used for static data which is read frequently ...
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... T MOTOROLA HVT FENLV FDISVFP VTCK pin low FP is low FP pin to control the control gate voltage; the FP (breakdown voltage) the control gate will equal the V 0. ZBRK FP ZBRK $00F5 1 Bit 0 0 BOOTP 0 1 $00F6 1 Bit 0 STRE MWPR 0 0 voltage. FP MC68HC912B32 MC68HC912B32TS/D ...
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... See Table 14 for the effects of LAT on array reads. A high volt- age detect circuit on the V pin will prevent assertion of the LAT bit when the programming voltage normal levels Programming latches disabled 1 = Programming latches enabled MC68HC912B32 MC68HC912B32TS FEESWAI SVFP ...
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... Program/Erase Verification — When programming or erasing the Flash EEPROM array, a special verification method is required to ensure that the program/erase process is reliable, and also to provide MOTOROLA 40 ERAS Result of Read – Normal read of location addressed 0 Read of location being programmed 1 Normal read of location addressed – Read cycle is ignored MC68HC912B32 MC68HC912B32TS/D ...
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... V be accomplished by plugging the board into a special programming fixture which provides program/erase voltage to the V MC68HC912B32 MC68HC912B32TS/D ), the length of the program pulse ( the erase margin pulse or pulses, and EPULSE ...
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... Read the address location to verify that it remains programmed. 10. Clear LAT. 11. If there are more locations to program, repeat steps 2 through 10. 12. Turn off V (reduce voltage The flowchart in Figure 7 demonstrates the recommended programming sequence. MOTOROLA 42 pin PPULSE ). VPROG pin pin voltage MC68HC912B32 MC68HC912B32TS/D ...
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... GET NEXT ADDRESS/DATA MC68HC912B32 MC68HC912B32TS/D START PROG TURN CLEAR MARGIN FLAG CLEAR PROGRAM PULSE COUNTER (n PP CLEAR ERAS SET LAT WRITE DATA TO ADDRESS SET ENPE DELAY FOR DURATION OF PROGRAM PULSE (t ) PPULSE CLEAR ENPE DELAY BEFORE VERIFY (t ) VPROG IS MARGIN FLAG NO SET? YES ...
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... If all of the Flash EEPROM locations are erased, repeat the same number of pulses as re- quired to erase the array. This provides 100% erase margin. 9. Read the entire array to ensure that the Flash EEPROM is erased. 10. Clear LAT. 11. Turn off V (reduce voltage The flowchart in Figure 8 demonstrates the recommended erase sequence. MOTOROLA 44 pin EPULSE ). VERASE pin MC68HC912B32 MC68HC912B32TS/D ...
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... CLEAR ERASE PULSE COUNTER (n NO MC68HC912B32 MC68HC912B32TS/D START ERASE TURN CLEAR MARGIN FLAG ) EP SET ERAS SET LAT WRITE TO ARRAY SET ENPE DELAY FOR DURATION OF ERASE PULSE (t ) EPULSE CLEAR ENPE DELAY BEFORE VERIFY (t ) VERASE INCREMENT IS n COUNTER EP MARGIN FLAG READ NO SET? ARRAY ...
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... Note that the Flash EEPROM module will operate normally, even if SMOD is asserted, until a special test function is invoked. The test mode adds additional features over normal mode which allow the tests to be performed even after the device is installed in the final product. MOTOROLA supplied via an external pin CAUTION FP MC68HC912B32 MC68HC912B32TS/D ...
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... EEPROM The MC68HC912B32 EEPROM serves as a 768-byte nonvolatile memory which can be used for fre- quently accessed static data or as fast access program code. The MC68HC912B32 EEPROM is arranged in a 16-bit configuration. The EEPROM array may be read as either bytes, aligned words or misaligned words. Access times is one bus cycle for byte and aligned word access and two bus cycles for misaligned word operations ...
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... Prevents accidental writes to EEPROM. Read anytime. Write anytime if EEPGM = 0 and PROTLCK = 0. MOTOROLA 48 SINGLE CHIP VECTORS RESERVED (64 BYTES) VECTORS (64 BYTES EESWAI PROTLCK PROG BPROT4 BPROT3 BPROT2 $FF80 $FFBF $FFC0 $FFFF HC912B32 EEPROM BLOCK PROT $00F0 1 Bit 0 EERC 0 0 $00F1 1 Bit 0 BPROT1 BPROT0 1 1 MC68HC912B32 MC68HC912B32TS/D ...
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... Known to enhance write/erase endurance of EEPROM cells Charge pump is turned on progressively during program/erase Disable charge pump controlled ramp up. EECPM — Charge Pump Monitor Enable 0 = Normal operation Output the charge pump voltage on the IRQ/V MC68HC912B32 MC68HC912B32TS/D Block Protected Block Size $0D00 to $0DFF 256 Bytes $0E00 to $0EFF 256 Bytes ...
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... Latched address and data cannot be modified during program or erase. MOTOROLA BYTE ROW ERASE Table 16 Erase Selection ROW Block Size 0 Bulk erase entire EEPROM array 1 Row erase 32 bytes 0 Byte or aligned word erase 1 Byte or aligned word erase $00F3 2 1 Bit 0 EELAT EEPGM MC68HC912B32 MC68HC912B32TS/D ...
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... Write a byte or an aligned word to an EEPROM address 3. Write EEPGM = 1 4. Wait for programming ( 5. Write EEPGM = 0 6. Write EELAT = possible to program/erase more bytes or words without intermediate EEPROM reads, by jumping from step 5 to step 2. MC68HC912B32 MC68HC912B32TS erase ( ) delay time t t PROG ERASE MOTOROLA ...
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... COPCTL (CME, FCME) None COP rate selected None None X bit I bit INTCR (IRQEN) I bit RTICTL (RTIE) I bit TMSK1 (C0I) I bit TMSK1 (C1I) I bit TMSK1 (C2I) HPRIO Value to Elevate None – – – None – None – None – $F2 $F0 $EE $EC $EA MC68HC912B32 MC68HC912B32TS/D ...
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... No stabilization delay imposed on exit from STOP mode. A stable external oscillator must be supplied Stabilization delay is imposed before processing resumes after STOP. DLY can be read anytime and written once in normal modes. In special modes, DLY can be read and written anytime. MC68HC912B32 MC68HC912B32TS/D Table 17 Interrupt Vector Map CCR Local Enable Mask Register (Bit) ...
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... MODB pins during reset. The SMODN, MODA, and MODB bits in the MODE register reflect the status of the mode-select inputs at the rising edge of reset. Operating mode and default maps can subsequent changed according to strictly defined rules. MOTOROLA PSEL5 PSEL4 PSEL3 PSEL2 $001F 2 1 Bit 0 PSEL1 MC68HC912B32 MC68HC912B32TS/D ...
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... When the CPU begins to service an interrupt, the instruction queue is cleared, the return address is cal- culated, and then it and the contents of the CPU registers are stacked as shown in Table 18. Table 18 Stacking Order on Entry to Interrupts Memory Location MC68HC912B32 MC68HC912B32TS/D CPU Registers SP – 2 RTN : RTN ...
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... At the end of the interrupt service routine, an RTI instruction re- stores the content of all registers from information on the stack, and normal program execution re- sumes. If another interrupt is pending at the end of an interrupt service routine, the register unstacking and restacking is bypassed and the vector of the pending interrupt is fetched. MOTOROLA 56 MC68HC912B32 MC68HC912B32TS/D ...
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... Clock generation circuitry generates the internal and external E-clock signals as well as internal clock signals used by the CPU and on-chip peripherals. A clock monitor circuit, a computer operating properly (COP) watchdog circuit, and a periodic interrupt circuit are also incorporated into the MC68HC912B32. 10.1 Clock Sources A compatible external clock signal can be applied to the EXTAL pin or the MCU can generate a clock signal using an on-chip oscillator circuit and an external crystal or ceramic resonator ...
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... S 10 5-100 RSBCK 0 RTBYP RTR2 Table 20 Real-Time Interrupt Rates Time-Out Period E = 4.0 MHz OFF OFF 13 2.048 4.096 8.196 16.384 32.768 65.536 131. $0014 2 1 Bit 0 RTR1 RTR0 Time-Out Period E = 8.0 MHz OFF 1.024 ms 2.048 ms 4.096 ms 8.196 ms 16.384 ms 32.768 ms 65.536 ms MC68HC912B32 MC68HC912B32TS ...
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... These bits specify an additional division factor to arrive at the COP time-out rate (the clock used for this module is the E clock). Write once in normal modes, anytime in special modes. Read anytime. MC68HC912B32 MC68HC912B32TS ...
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... Writing anything other than $55 or $AA causes a COP reset to occur. 10.6 Clock Divider Chains Figure 11, Figure 12, Figure 13, and Figure 14 summarize the clock divider chains for the various pe- ripherals on the MC68HC912B32. EXTAL OSCILLATOR AND ...
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... REGISTER: BCR1 BITS: R1, R0 SC0BD MODULUS DIVIDER ..., 8190, 8191 SCI0 RECEIVE BAUD RATE ((16x SCI0 TRANSMIT BAUD RATE (1x) Figure 12 Clock Chain for SCI, BDLC, RTI, COP MC68HC912B32 MC68HC912B32TS REGISTER: RTICTL BIT: RTBYP REGISTER: RTICTL BITS: RTR2, RTR1, RTR0 0:0 2 0:1 2 1:0 2 ...
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... E clocks while output is high impedance, drive out 1 E cycle pulse high, high imped- ance output again Transmit 0: Detect falling edge, drive out low, count 9 E clocks, drive out 1 E cycle pulse high, high impedance output HC12 CLOCK CHAIN SPI ATD BDM MC68HC912B32 MC68HC912B32TS/D ...
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... When PWM are not in use, the port pins may be used for discrete input/output. CLOCK SOURCE (PCLK) PWCNTx GATE (CLOCK EDGE SYNC) RESET PWENx PPOL = 0 PPOL = 1 Figure 15 Block Diagram of PWM Left-Aligned Output Channel MC68HC912B32 MC68HC912B32TS/D CENTR = 0 UP/DOWN 8-BIT COMPARE = S PWDTYx R 8-BIT COMPARE = PWPERx PWDTY PWPER FROM PORT P DATA REGISTER ...
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... EDGE SYNC) PWENx PPOL = 0 PPOL = 1 PWDTY Figure 16 Block Diagram of PWM Center-Aligned Output Channel MOTOROLA 64 CENTR = 1 RESET DATA REGISTER (DUTY CYCLE) 8-BIT COMPARE = PWDTYx T Q MUX (PERIOD) Q 8-BIT COMPARE = PWPERx PPOLx (PWPER PWDTY) 2 PWPER 2 FROM PORT P MUX TO PIN DRIVER PWDTY MC68HC912B32 MC68HC912B32TS/D ...
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... Channel 2 output pin is used as the output for this 16-bit PWM (bit 2 of port P). Channel 3 clock- select control bits determines the clock source Channels 2 and 3 are separate 8-bit PWMs Channels 2 and 3 are concatenated to create one 16-bit PWM channel. MC68HC912B32 MC68HC912B32TS/D CLOCK 8-BIT DOWN COUNTER PWSCNT0 ...
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... Clock S0 is the clock source for channel clock select is changed while a PWM signal is being generated, a truncated or stretched pulse may occur during the transition. MOTOROLA 66 PCKA1 PCKA0 Value of (PCKB1) (PCKB0) Clock A ( PCLK1 PCLK0 PPOL3 PPOL2 128 $0041 2 1 Bit 0 PPOL1 PPOL0 MC68HC912B32 MC68HC912B32TS/D ...
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... The pulse modulated signal will be available at port P, bit 1 when its clock source begins its next cycle Channel 1 is disabled Channel 1 is enabled. PWEN0 — PWM Channel 0 Enable The pulse modulated signal will be available at port P, bit 0 when its clock source begins its next cycle Channel 0 is disabled Channel 0 is enabled. MC68HC912B32 MC68HC912B32TS PWEN3 ...
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... Bit 7 6 Bit 7 6 RESET PWSCNT1 is a down-counter that, upon reaching $00, loads the value of PWSCAL1. Read any time. MOTOROLA $0043 1 Bit 0 1 Bit $0044 1 Bit 0 1 Bit $0045 1 Bit 0 1 Bit $0046 1 Bit 0 1 Bit $0047 1 Bit 0 1 Bit MC68HC912B32 MC68HC912B32TS/D ...
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... The new period is then latched and is used until a new period value is written. Reading this register returns the most recent value written. To start a new period immediately, write the new pe- riod value and then write the counter forcing a new period to start with the new period value. Period = Channel-Clock-Period (PWPER Period = Channel-Clock-Period (2 MC68HC912B32 MC68HC912B32TS ...
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... All port P pins have an active pull-up device disabled All port P pins have an active pull-up device enabled. MOTOROLA 1)] 100% 1)] 100% 1)] 100% 1)] 100 PSWAI CENTR RDPP Bit 0 1 Bit 0 $0050 1 Bit 0 $0051 1 Bit 0 $0052 1 Bit 0 $0053 0 0 (PPOLx = 1) (PPOLx = 0) (PPOLx = 1) (PPOLx = 0) $0054 1 Bit 0 PUPP PSBCK 0 0 MC68HC912B32 MC68HC912B32TS/D ...
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... DDRP — Port P Data Direction Register Bit 7 6 DDP7 DDP6 RESET DDRP determines pin direction of port P when used for general-purpose I/O. When cleared, I/O pin is configured for input. When set, I/O pin is configured for output. Read and write anytime. MC68HC912B32 MC68HC912B32TS ...
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... The boundary conditions for the PWM channel duty registers and the PWM channel period registers cause these results: PWDTYx PWPERx PWPERx MOTOROLA 72 Table 23 PWM Boundary Conditions PWPERx PPOLx $FF $00 1 $FF $00 0 – 1 – 0 – $00 1 – $00 0 Output High Low High Low High Low MC68HC912B32 MC68HC912B32TS/D ...
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... CLOCK PRESCALER PR2, PR1, PR0 INPUT CAPTURE/ OUTPUT COMPARE REGISTER PULSE ACCUMULATOR INT COUNTER BUFFER Figure 18 Timer Block Diagram: Input Capture, Output Compare, Pulse Accumulator MC68HC912B32 MC68HC912B32TS/D CONTROL REGISTERS TCRE (COUNTER RESET) TCNT TCNT RESET 16-BIT COUNTER OC7 BUFFER LATCH - TIOC ...
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... MOTOROLA IOS5 IOS4 IOS3 IOS2 FOC5 FOC4 FOC3 FOC2 OC7M5 OC7M4 OC7M3 OC7M2 OC7D5 OC7D4 OC7D3 OC7D2 $0080 2 1 Bit 0 IOS1 IOS0 $0081 2 1 Bit 0 FOC1 FOC0 $0082 2 1 Bit 0 OC7M1 OC7M0 $0083 2 1 Bit 0 OC7D1 OC7D0 MC68HC912B32 MC68HC912B32TS/D ...
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... TCNT register ($84, $85) clears the TOF flag. Any access to the PACNT register ($A2, $A3) clears the PAOVF and PAIF flags in the PAFLG register ($A1). This has the advantage of eliminating software overhead in a separate clear sequence. Extra care is required to avoid ac- cidental flag clearing due to unintended accesses. TQCR — Reserved Bit RESET MC68HC912B32 MC68HC912B32TS ...
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... EDG1B EDG1A EDGnA Configuration 0 Capture disabled 1 Capture on rising edges only 0 Capture on falling edges only 1 Capture on any edge (rising or falling) $0088 2 1 Bit 0 OM4 OL4 $0089 2 1 Bit 0 OM0 OL0 $008A 2 1 Bit 0 EDG4B EDG4A $008B 2 1 Bit 0 EDG0B EDG0A MC68HC912B32 MC68HC912B32TS/D ...
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... TOF will never get set even though TCNT will count from $0000 through $FFFF. PR2, PR1, PR0 — Timer Prescaler Select These three bits specify the number of 2 stages that are to be inserted between the module clock and the timer counter. PR2 MC68HC912B32 MC68HC912B32TS C5I ...
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... Bit 15 14 Bit 7 6 MOTOROLA C5F C4F C3F C2F $008E 1 Bit 0 C1F C0F 0 0 $008F 1 Bit $0090–$0091 1 Bit 0 9 Bit 8 1 Bit 0 $0092–$0093 1 Bit 0 9 Bit 8 1 Bit 0 $0094–$0095 1 Bit 0 9 Bit 8 1 Bit 0 MC68HC912B32 MC68HC912B32TS/D ...
Page 79
... PACTL — Pulse Accumulator Control Register Bit PAEN PAMOD RESET Read or write anytime. PAEN — Pulse Accumulator System Enable 0 = Pulse accumulator system disabled 1 = Pulse accumulator system enabled PAEN is independent from TEN. PAMOD — Pulse Accumulator Mode 0 = Event counter mode 1 = Gated time accumulation mode MC68HC912B32 MC68HC912B32TS ...
Page 80
... MOTOROLA 80 Table 27 Clock Selection Selected Clock Use timer prescaler clock as timer counter clock Use PACLK as input to timer counter clock Use PACLK/256 as timer counter clock frequency Use PACLK/65536 as timer counter clock frequency clock is generated $00A1 1 Bit 0 PAOVF PAIF 0 0 MC68HC912B32 MC68HC912B32TS/D ...
Page 81
... The minimum pulse width for the input capture should always be greater than the width of two module clocks due to input synchronizer circuitry. MC68HC912B32 MC68HC912B32TS ...
Page 82
... NORMAL: Timer keeps running, unless TEN = 0 TEN = 0: All timer operations are stopped, registers may be accessed. Gated pulse accumulator 64 clock is also disabled. PAEN = 0: All pulse accumulator operations are stopped, registers may be accessed. MOTOROLA DDT5 DDT4 DDT3 DDT2 $00AF 2 1 Bit 0 DDT1 DDT0 MC68HC912B32 MC68HC912B32TS/D ...
Page 83
... Figure 19 Serial Interface Block Diagram 13.2 Serial Communication Interface (SCI) The serial communication interface on the MC68HC912B32 is an NRZ format (one start, eight or nine data, and one stop bit) asynchronous communication system with independent internal baud rate gen- eration circuitry and an SCI transmitter and receiver. It can be configured for eight or nine data bits (one of which may be designated as a parity bit, odd or even) ...
Page 84
... SC0CR1/SCI CTL 1 TxMTR CONTROL SC0CR2/SCI CTL 2 SC0SR1/INT STATUS INT REQUEST LOGIC SCI RECEIVER DATA RECOVERY MSB 10-11 BIT SHIFT REG TxD BUFFER/SC0DRL WAKE-UP LOGIC SC0SR1/INT STATUS SC0CR2/SCI CTL 2 INT REQUEST LOGIC LSB TxD PS1 RxD PS0 LSB HC12B32 SCI BLOCK MC68HC912B32 MC68HC912B32TS/D ...
Page 85
... BR is the value written to bits SBR[12:0] to establish baud rate. The baud rate generator is disabled until the bit in SC0CR2 register is set for the first time after reset, and/or the baud rate generator is disabled when SBR[12: MC68HC912B32 MC68HC912B32TS/D Table 28 Baud Rate Generation BR Divisor for BR Divisor for P = 4.0 MHz ...
Page 86
... Single wire mode without TXD output x (the pin is used as receiver input only, TXD = High Impedance) Single wire mode with TXD output 0 (the output is also fed back to receiver input, CMOS) 1 Single wire mode for the receiving and transmitting (open-drain) $00C2 2 1 Bit MC68HC912B32 MC68HC912B32TS/D ...
Page 87
... TE — Transmitter Enable 0 = Transmitter disabled 1 = SCI transmit logic is enabled and the TXD pin (port S bit 1) is dedicated to the transmitter. The TE bit can be used to queue an idle preamble. RE — Receiver Enable 0 = Receiver disabled 1 = Enables the SCI receive circuitry MC68HC912B32 MC68HC912B32TS RIE ILIE TE RE ...
Page 88
... New byte is ready to be transferred from the receive shift register to the receive data register and the receive data register is already full (RDRF bit is set). Data transfer is inhibited until this bit is cleared overrun 1 = Overrun detected MOTOROLA RDRF IDLE $00C4 2 1 Bit MC68HC912B32 MC68HC912B32TS/D ...
Page 89
... This bit is the ninth serial data bit transmitted when the SCI system is configured for nine-data-bit oper- ation. When using 9-bit data format this bit does not have to be written for each data word. The same value will be transmitted as the ninth bit until this bit is rewritten. MC68HC912B32 MC68HC912B32TS ...
Page 90
... Serial Peripheral Interface (SPI) The serial peripheral interface allows the MC68HC912B32 to communicate synchronously with periph- eral devices and other microprocessors. The SPI system in the MC68HC912B32 can operate as a mas- ter slave. The SPI is also capable of interprocessor communications in a multiple master system. ...
Page 91
... SPI system. The CPOL bit simply selects non-in- verted or inverted clock. The CPHA bit is used to accommodate two fundamentally different protocols by shifting the clock by one half cycle or no phase shift. MC68HC912B32 MC68HC912B32TS/D 8-BIT SHIFT REGISTER READ DATA BUFFER SP0DR SPI DATA REGISTER ...
Page 92
... Bit 4 Bit 5 Begin Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 End Bit 1 LSB Minimum 1/2 SCK for Bit 6 MSB HC12 SPI CLOCK FORM 0 End Bit 1 LSB Minimum 1/2 SCK for Bit 6 MSB HC12 SPI CLOCK FORM 1 MC68HC912B32 MC68HC912B32TS/D ...
Page 93
... For more information refer to 5 Operating Modes and Resource Mapping. SP0CR1 — SPI Control Register 1 Bit 7 6 SPIE SPE SWOM RESET MC68HC912B32 MC68HC912B32TS/D Table 30 SS Output Selection Master Mode SS Input with MODF Feature Reserved General-Purpose Output SS Output MSTR=1 MO Serial In SPI DDS5 ...
Page 94
... Read or write anytime. SSWAI — SSI Stop in Wait Mode 0 = SSI clock operate normally 1 = Halt SSI clock generation when in wait mode SPC0 — Serial Pin Control 0 This bit decides serial pin configurations with MSTR control bit. MOTOROLA $00D1 1 Bit 0 SSWAI SPC0 0 0 MC68HC912B32 MC68HC912B32TS/D ...
Page 95
... The MCU write is disabled to avoid writing over the data being transferred. No interrupt is generated because the error status flag can be read upon completion of the transfer that was in progress at the time of the error. Automatically cleared by a read of the SP0SR (with WCOL set) followed by an access MC68HC912B32 MC68HC912B32TS MSTR ...
Page 96
... Configure the corresponding I/O pin for input only 1 = Configure the corresponding I/O pin for output MOTOROLA PS5 PS4 PS3 PS2 MOSI MISO I/O I/O MOMI SISO DDS5 DDS4 DDS3 DDS2 $00D5 2 1 Bit Bit $00D6 2 1 Bit 0 PS1 PS0 TXD0 RXD0 $00D7 2 1 Bit 0 DDS1 DDS0 MC68HC912B32 MC68HC912B32TS/D ...
Page 97
... Port S input pins for bits 3 and 2 have an active pull-up device pin is programmed as output, the pull-up device becomes inactive. PUPS0 — Pull-Up Port S Enable PS[1: internal pull-ups on port S bits 1 and Port S input pins for bits 1 and 0 have an active pull-up device pin is programmed as output, the pull-up device becomes inactive. MC68HC912B32 MC68HC912B32TS RDPS0 0 ...
Page 98
... In this mode, the BDLC internal clocks are stopped until network activity is sensed and a CPU interrupt request is generated. MOTOROLA 98 NOTE is supplied to the internal circuits, which are held in their DD drops below the min- DD rises above its min- DD MC68HC912B32 MC68HC912B32TS/D ...
Page 99
... Binary frequency (1.048576 MHz) R1, R0 — Rate Select Determines the divisor of the MCU system clock frequency (f quency (f ). These bits may be written only once after reset. BDLC The selected value depends upon the MCU system clock frequency according to Table 32 or Table 33. MC68HC912B32 MC68HC912B32TS ...
Page 100
... RxPD is connected to TxPD. The BDLC is now in digital loopback mode of operation. The an- alog transceiver’s transmit input is still driven by TxPD. MOTOROLA 100 (f = 1.048576 MHz) BDLC TCLKS 1.000000 MHz) BDLC TCLKS RX4XE NBFS TEOD TSIFR Division Division $00FA 2 1 Bit 0 TMIFR1 TMIFR0 MC68HC912B32 MC68HC912B32TS/D ...
Page 101
... TSIFR TMIFR1 Shaded cells indicate bits which do not affect internal interpretation. These bits will be read back as written. The BDLC supports the in-frame response (IFR) features of J1850. The four types of J1850 IFR are shown below. MC68HC912B32 MC68HC912B32TS/D Internal Interpretation TMIFR0 TSIFR TMIFR1 ...
Page 102
... BDLC will attempt to transmit the appropriate normalization bit followed by IFR bytes. After TEOD has been set by software and the last IFR byte has been transmitted, the CRC byte is transmitted. MOTOROLA 102 CRC CRC NB ID CRC NB ID1 CRC NB IFR DATA FIELD IDn CRC MC68HC912B32 MC68HC912B32TS/D ...
Page 103
... JMP NOP JMP NOP JMP NOP . . . JMP END NOP instructions are used to align the JMP instructions onto 4-byte boundaries so that the value in the BSVR may be used intact. Each of the service routines must end with an RTI instruction. MC68HC912B32 MC68HC912B32TS Table 35 Interrupt Sources ...
Page 104
... Table 36 Offset Bit Values and Transceiver Delay BARD Offset Bits (BO3, BO2, BO1, BO0) MOTOROLA 104 – – – – BO3 BO2 NOTE Expected Delay ( s) 0000 9 0001 10 0010 11 0011 12 0100 13 $00FB 1 Bit – – $00FC 1 Bit 0 BO1 BO0 1 1 MC68HC912B32 MC68HC912B32TS/D ...
Page 105
... PORTDLC can be read anytime. When configured as an input, a read will return the pin level. When configured as output, a read will return the latched output data. Writes will not change pin state when the pins are configured for BDLC output. Upon reset pins are configured for general-purpose high im- pedance inputs. MC68HC912B32 MC68HC912B32TS/D Expected Delay ( s) 0101 14 0110 ...
Page 106
... BREAK — Any BDLC transmitting at the time a BREAK is detected will treat the BREAK trans- mission error had occurred, and halt transmission. If while receiving a message the BDLC detects a BREAK symbol, it will treat the BREAK as a reception error. MOTOROLA 106 DDDLC4 DDDLC3 DDDLC2 $00FF 1 Bit 0 DDDLC1 DDDLC0 0 0 MC68HC912B32 MC68HC912B32TS/D ...
Page 107
... CRC Error BDLC receives BREAK symbol Invalid Symbol: BDLC sends an EOD but receives an active symbol MC68HC912B32 MC68HC912B32TS/D BDLC Function The BDLC will not transmit until the bus is idle. Thermal overload will shutdown physical interface. Fault condition is reflected in BSVR as invalid symbol. The BDLC will abort transmission immediately. ...
Page 108
... ANALOG MUX ATD 1 SAMPLE BUFFER AMP ATD 2 ATD 3 ATD 4 PORT AD DATA INPUT REGISTER ATD 5 ATD 6 CLOCK ATD 7 SELECT/PRESCALE INTERNAL BUS REFERENCE DDA SUPPLY V SSA AN7/PAD7 AN6/PAD6 AN5/PAD5 AN4/PAD4 AND AN3/PAD3 AN2/PAD2 AN1/PAD1 AN0/PAD0 HC12 ATD BLOCK $0060 2 1 Bit MC68HC912B32 MC68HC912B32TS/D ...
Page 109
... FRZ1, FRZ0 — Background Debug (Freeze) Enable (suspend module operation at breakpoint) When debugging an application useful in many cases to have the ATD pause when a breakpoint is encountered. These two bits determine how the ATD will respond when background debug mode be- comes active. MC68HC912B32 MC68HC912B32TS ...
Page 110
... PRS4 PRS3 PRS2 Final Sample Time Total 8-Bit Conversion Time 2 ATD clock periods 4 ATD clock periods 8 ATD clock periods 16 ATD clock periods $0064 2 1 Bit 0 PRS1 PRS0 ATD clock periods 18 ATD clock periods 22 ATD clock periods 30 ATD clock periods MC68HC912B32 MC68HC912B32TS/D ...
Page 111
... ATD sequencer runs all four or eight conversions on a single input channel selected via the CD, CC, CB, and CA bits ATD sequencer runs each of the four or eight conversions on sequential channels in a specific group. Refer to Table 41. CD, CC, CB, and CA — Channel Select for Conversion MC68HC912B32 MC68HC912B32TS/D Table 40 Clock Prescaler Values 1 Max P Clock 4 MHz 2 ...
Page 112
... Reserved Reserved )/ TEST/Reserved Result in ADRx if MULT = 1 ADR0 ADR1 ADR2 ADR3 ADR0 ADR1 ADR2 ADR3 ADR0 ADR1 ADR2 ADR3 ADR0 ADR1 ADR2 ADR3 ADR0 ADR1 ADR2 ADR3 ADR4 ADR5 ADR6 ADR7 ADR0 ADR1 ADR2 ADR3 ADR4 ADR5 ADR6 ADR7 MC68HC912B32 MC68HC912B32TS/D ...
Page 113
... Reads of this byte return the current value in the SAR. Writes to this byte change the SAR to the value written. Bits SAR[9:2] reflect the eight SAR bits used during the resolution process for an 8-bit result. SAR1 and SAR0 are reserved to allow future derivatives to increase ATD resolution to ten bits. MC68HC912B32 MC68HC912B32TS ...
Page 114
... PAD5 PAD4 PAD3 PAD2 – – – – – – ) before initiating a new ATD conversion sequence. SR $006F 2 1 Bit 0 PAD1 PAD0 – – – specifi $0070 $0072 $0074 $0076 $0078 $007A $007C $007E 2 1 Bit Bit 0 – – – MC68HC912B32 MC68HC912B32TS/D ...
Page 115
... Development Support Development support involves complex interactions between MC68HC912B32 resources and external development systems. The following section concerns instruction queue and queue tracking signals, background debug mode, and instruction tagging. 16.1 Instruction Queue The CPU12 instruction queue provides at least three bytes of program information to the CPU when instruction execution begins ...
Page 116
... Figure 27 shows an external host transmitting a logic one or zero to the BKGD pin of a target MC68HC912B32 MCU. The host is asynchronous to the target so there is a 0-to-1 cycle delay from the host-generated falling edge to where the target perceives the beginning of the bit time. Nine target E cycles later, the target senses the bit level on the BKGD pin ...
Page 117
... BKGD PIN Figure 28 BDM Target to Host Serial Bit Timing (Logic 1) Figure 28 shows the host receiving a logic one from the target MC68HC912B32 MCU. Since the host is asynchronous to the target MCU, there is a 0-to-1 cycle delay from the host-generated falling edge on BKGD to the perceived start of the bit time in the target MCU. The host holds the BKGD pin low long enough for the target to recognize it (at least two target E cycles) ...
Page 118
... BKGD to the start of the bit time as perceived by the target MCU. The host initiates the bit time but the target MC68HC912B32 finishes it. Since the target wants the host to receive a logic zero, it drives the BKGD pin low for 13 E-clock cycles, then briefly drives it high to speed up the rising edge. The host samples the bit level about ten cycles after starting the bit time ...
Page 119
... The BDM ROM is located at $FF20 to $FFFF while BDM is active. There are also seven bytes of BDM registers which are located at $FF00 to $FF06 while BDM is active. The CPU executes code from this ROM to perform the requested operation. These commands are shown in Table 44. MC68HC912B32 MC68HC912B32TS/D Data None Enter background mode (if firmware enabled). ...
Page 120
... Write X index register 16-bit data in Write Y index register 16-bit data in Write stack pointer None Go to user program None Execute one user instruction then return to BDM None Enable tagging and go to user program R/W BKGND W/B BD/U Description (BDM) $FF00 2 1 Bit MC68HC912B32 MC68HC912B32TS/D ...
Page 121
... Read TTAGO — Trace, Tag, Go Field REGN — Register/Next Field Indicates which register is being affected by a command. In the case of a READ_NEXT or WRITE_NEXT command, index register X is pre-incremented by two and the word pointed then read or written. MC68HC912B32 MC68HC912B32TS R/W TTAGO Table 45 TTAGO Decoding ...
Page 122
... MOTOROLA 122 ENTAG SDV TRACE S13 S12 S11 A13 A12 A11 CCR5 CCR4 CCR3 CCR2 (BDM) $FF01 2 1 Bit (BDM) $FF02, $FF03 10 9 Bit 8 S10 Bit (BDM) $FF04, $FF05 10 9 Bit 8 A10 Bit (BDM) $FF06 2 1 Bit 0 CCR1 CCR0 MC68HC912B32 MC68HC912B32TS/D ...
Page 123
... Breakpoints Hardware breakpoints are used to debug software on the MC68HC912B32 by comparing actual ad- dress and data values to predetermined data in setup registers. A successful comparison will place the CPU in background debug mode (BDM) or initiate a software interrupt (SWI). Breakpoint features de- signed into the MC68HC912B32 include: • ...
Page 124
... MOTOROLA 124 BKPM 0 BK1ALE BK0ALE Table 47 Breakpoint Mode Control BRKAH/L Usage BRKDH/L Usage — Address Match Address Match Address Match $0020 2 1 Bit R/W Range — — — Address Match No Yes Data Match Yes Yes Address Match Yes Yes MC68HC912B32 MC68HC912B32TS/D ...
Page 125
... When BK0RWE = 1, this bit determines the type of bus cycle to match on Write cycle will be matched 1 = Read cycle will be matched MC68HC912B32 MC68HC912B32TS/D Address Range Selected Upper 8-bit address only for full mode or dual mode BKP0 Full 16-bit address for full mode or dual mode BKP0 ...
Page 126
... R/W is don’t care for dual mode BKP1 – – – – R/W is write for dual mode BKP1 – – R/W is read for dual mode BKP1 $0022 1 Bit 0 9 Bit $0023 1 Bit 0 1 Bit $0024 1 Bit 0 9 Bit $0025 1 Bit 0 1 Bit MC68HC912B32 MC68HC912B32TS/D ...
Page 127
... The tag follows the information in the queue as the queue is advanced. When a tagged instruction reaches the head of the queue, the CPU enters active background debugging mode rather than exe- cuting the instruction. This is the mechanism by which a development system initiates hardware break- points. MC68HC912B32 MC68HC912B32TS/D MOTOROLA 127 ...
Page 128
... JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 81-3-3521-8315 ASIA PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 Mfax is a trademark of Motorola, Inc. are registered trademarks of Motorola, Inc. Motorola, Inc Equal ! MC68HC912B32TS/D ...