ADE3700SX STMicroelectronics, ADE3700SX Datasheet
ADE3700SX
Available stocks
Related parts for ADE3700SX
ADE3700SX Summary of contents
Page 1
... Product Package ADE3700X 128 LQFP ADE3700XT 128 LQFP ADE3700SX 128 LQFP October 2003 This is preliminary information on a new product forseen to be developed. Details are subject to change without notice. General Description ADE3700 devices are a family of highly-integrated display engine ICs, enabling the most advanced, flexible, and cost-effective system-on-chip solutions for analog-only input LCD display applications ...
Page 2
Third Generation Context Sensitive™ Scaler Sharper text with Edge Enhancement RAM based coefficients for unique customization 5:1 Upscale and 2:1 Downscale Independent axis zoom and shrink Analog RGB input 140 MHz 9-bit ADC Ultra low jitter digital ...
Page 3
ADE3700 Chapter 1 General Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 4
Gamma ...............................................................................................................................70 2.18 APC ....................................................................................................................................71 2.19 Output Multiplexer ..............................................................................................................72 2.19.1 Sub Block Function ........................................................................................................................... 73 2.19.2 RSDS ................................................................................................................................................ 76 2.19.3 Per Pin Delay .................................................................................................................................... 77 2.20 Pulse Width Modulation (PWM) ..........................................................................................80 2.21 DFT Block ...........................................................................................................................81 2.22 I²C RAM Addresses ...
Page 5
ADE3700 1 General Information The ADE3700 family of devices is capable of implementing all of the advanced features of today’s LCD monitor products. For maximum flexibility, an external microcontroller (MCU) is used for controlling the ADE3700 and other monitor functions. ...
Page 6
Feature Sync / Timing Once an input source is selected, all available information on frequencies and Measurement line/pixel counts is measured for the selected source and made available to the MCU. Mode Set Once the MCU has determined the matching ...
Page 7
ADE3700 1.1 Pin Descriptions LQFP128 Name 32 XVDD18 31 XTAL_OUT 30 XTAL_IN 29 XGND 19 XCLK_EN 18 XCLK 34 VSYNC 21 TSTCLK 65 TST_SCAN 8 TCON7 9 TCON6/OVS 10 TCON5/OHS 11 TCON4/ODE 12 TCON3 13 TCON2 14 TCON1 15 TCON0 ...
Page 8
Pin Descriptions LQFP128 Name 128 ORB5 1 ORB4 2 ORB3 3 ORB2 4 ORB1 5 ORB0 86 ORA7 87 ORA6 88 ORA5 89 ORA4 90 ORA3 95 ORA2 96 ORA1 97 ORA0 103 AHS 112 OGB7 113 OGB6 114 OGB5 ...
Page 9
ADE3700 LQFP128 Name 108 OBB3 109 OBB2 110 OBB1 111 OBB0 66 OBA7 67 OBA6 68 OBA5 69 OBA4 70 OBA3 71 OBA2 72 OBA1 73 OBA0 56 INR 49 ING 42 INB 35 HSYNC 7 DVDD33 64 DVDD33 80 ...
Page 10
Pin Descriptions LQFP128 Name 116 DGND 118 DGND 125 DGND 33 CSYNC 36 AVDD33 43 AVDD33 50 AVDD33 57 AVDD33 46 AVDD18 53 AVDD18 60 AVDD18 37 AGND 39 AGND 45 AGND 52 AGND 59 AGND 61 AGND 38 ADVDD18 ...
Page 11
ADE3700 2 Functional Description 2.1 Global Control The global control block is responsible for: selecting clock sources power control I²C control SCLK frequency synthesizer control block by block synchronous reset generation The global control block runs on the XCLK clock ...
Page 12
Global Control Table 3: SCLK Frequency Synthesizer Programmable Values (Sheet INT(f XCLK INT(( ( where f is the external crystal frequency in MHz (typically 27). The ...
Page 13
ADE3700 Register Name GLBL_NULL_ADDR GLBL_CLK_SRC_SEL_0 GLBL_CLK_SRC_SEL_2 Table 4: Global Registers (Sheet Addr. mode Bits Default 0x0000 Read [7:0] 0x0001 [7] 0x0 R/W [6:4] 0x5 R/W [3:0] 0xA 0x0002 [7] 0x0 R/W [6:4] 0x4 [3] R/W [2:0] 0x4 ...
Page 14
Global Control Register Name GLBL_CLK_INV GLBL_CLK_ENABLE_0 GLBL_ANA_PWR GLBL_XK_SRST GLBL_I2C_CTRL GLBL_XTAL_CTRL GLBL_SCLK_SYNTH_CTRL 14/89 Table 4: Global Registers (Sheet Addr. mode Bits Default 0x0003 [7:5] 0x0 R/W [4] 0x0 R/W [3] 0x0 R/W [2] 0x0 R/W [1] 0x0 R/W ...
Page 15
ADE3700 Register Name GLBL_SCLK_MD_SD GLBL_SCLK_PE_L GLBL_SCLK_PE_H GLBL_TST_CTRL GLBL_COMP_PAD_CTRL GLBL_SCLK_CTRL GLBL_BPAD_EN GLBL_IK_SRST GLBL_SHADOW_EN Table 4: Global Registers (Sheet Addr. mode Bits Default 0x000A R/W [7:3] 0x0 R/W [2:0] 0x0 0x000B R/W [7:0] 0x0 0x000C R/W [7:0] 0x000D [7:1] ...
Page 16
FM Frequency Synthesizer Register Name GLBL_INCLK_GATE_CTRL GLBL_DK_SRST GLBL_OSD_POWER_CTRL GLBL_DOTCLK_GATE_CTRL 2.2 FM Frequency Synthesizer The FM Frequency Synthesizer can create a clock up to eight times the crystal input clock using a digital frequency synthesizer. The modulation period and amplitude are ...
Page 17
ADE3700 Register Name FM_FS_CTRL FM_FS_PR_0 FM_FS_PR_1 FM_FS_PR_2 FM_FS_PR_3 FM_FS_AMPLITUDE FM_FS_PERIODX64 FM_FS_PULSE_EXT 2.3 Analog-to-Digital Converter (ADC) The analog port consists of three 9-bit RGB ADCs with preamp, gain/offset adjustment and digital filtering. The I2C interface for the ADC block is in ...
Page 18
Line Lock PLL Register ADC_OFFSET_B ADC_GAIN_R ADC_GAIN_G ADC_GAIN_B 2.4 Line Lock PLL The Line Lock PLL recovers a sample clock from an incoming hsync source. The response characteristics of the line lock PLL can be adjusted for optimum response time ...
Page 19
ADE3700 Register Name LLK_PLL_CLEAR LLK_PLL_CTRL LLK_PLL_MFACTOR_L LLK_PLL_MFACTOR_H LLK_PLL_HPERIOD_L LLK_PLL_HPERIOD_H LLK_PLL_PHASE_RATE_INIT_0 LLK_PLL_PHASE_RATE_INIT_1 LLK_PLL_PHASE_RATE_INIT_2 LLK_PLL_PHASE_RATE_INIT_3 LLK_PLL_PHASE_RATE_INIT_WR Table 7: Line Lock PLL Registers (Sheet Addr Mode Bits 0x0800 [7:6] R/W [5] R/W [4] R/W [3] R/W [2] R/W [1] R/W ...
Page 20
Line Lock PLL Register Name LLK_PLL_TC_AEF LLK_PLL_TC_BEF LLK_PLL_TC_ALF LLK_PLL_TC_BLF LLK_PLL_TC_AES LLK_PLL_TC_BES LLK_PLL_TC_ALS LLK_PLL_TC_BLS LLK_PLL_TC_AEK LLK_PLL_TC_BEK LLK_PLL_TC_ALK LLK_PLL_TC_BLK LLK_PLL_TC_SLOW_TOL LLK_PLL_TC_SLOW_LINE_NB 20/89 Table 7: Line Lock PLL Registers (Sheet Addr Mode Bits 0x080B [7:4] R/W [3:0] 0x080C [7:4] R/W ...
Page 21
ADE3700 Register Name LLK_PLL_LOCK_TOL LLK_PLL_LOCK_LINE_NB LLK_PLL_PH_OFFSET LLK_PLL_PH_OFFSET_EN LLK_PLL_PULSE_HIGH_EXT LLK_PLL_STAT_LINES_L LLK_PLL_STAT_LINES_H LLK_PLL_STAT_ERROR_INC_LO W LLK_PLL_FINE_ERROR_WAIT LLK_PLL_STAT_ON_VSYNC LLK_PLL_MFACTOR_SHADOW_L LLK_PLL_MFACTOR_SHADOW_U Table 7: Line Lock PLL Registers (Sheet Addr Mode Bits 0x0819 R/W [7:0] 0x081A R/W [7:0] 0x081B R/W [7:0] 0x081C R/W ...
Page 22
Line Lock PLL Register Name LLK_PLL_UPDATE LLK_PLL_STATUS LLK_PLL_PH_ERROR_L LLK_PLL_PH_ERROR_H LLK_PLL_PHASE_RATE_0 LLK_PLL_PHASE_RATE_1 LLK_PLL_PHASE_RATE_2 LLK_PLL_PHASE_RATE_3 LLK_PLL_PHASE_RATE_I_0 LLK_PLL_PHASE_RATE_I_1 LLK_PLL_PHASE_RATE_I_2 LLK_PLL_PHASE_RATE_I_3 LLK_PLL_STAT_ERROR_MEAN LLK_PLL_STAT_ERROR_PP_L LLK_PLL_STAT_ERROR_PP_H LLK_PLL_STAT_ERROR_ABS_L LLK_PLL_STAT_ERROR_ABS_H LLK_PLL_STAT_ERROR_GTX 22/89 Table 7: Line Lock PLL Registers (Sheet Addr Mode Bits 0x0840 R [7] ...
Page 23
ADE3700 2.5 Sync Retiming (SRT) The Sync Retiming (SRT) block retimes incoming synchronization signals (H Sync, V Sync, etc) into the XCLK and INCLK domains. For the XCLK domain, the SRT has the following functions: Retimes all sync signals going ...
Page 24
Sync Retiming (SRT) Register Name SRTXK_COAST_VS_SEL SRTXK_COAST_RISE_L SRTXK_COAST_RISE_M SRTXK_COAST_RISE_H SRTXK_COAST_FALL_L SRTXK_COAST_FALL_M SRTXK_COAST_FALL_H SRTIK_HS_CTRL SRTIK_VS_SEL 24/89 Table 8: Sync Retiming Registers (Sheet Addr Mode Bits 0x01E8 [7:4] R/W [3] R/W [2:0] 0x01E9 R/W [7:0] 0x01EA R/W [7:0] 0x01EB ...
Page 25
ADE3700 2.6 Sync Measurement The Input Sync Measurement (SMEAS) block continuously detects activity from all video sources. The module can measure the characteristics of the sync signals on any input port. The sync measurement module reports the results of the ...
Page 26
Sync Measurement Register Name SMEAS_V_TMOT_L SMEAS_V_TMOT_H SMEAS_CLEAR SMEAS_H_CTRL 26/89 Table 9: Sync Measurement (Sheet Addr Mode Bits Default 0x0109 R/W [7:0] 0x1600 0x010A R/W [7:0] 0x0110 [7:3] R/W [2] 0x0 R/W [1] 0x0 R/W [0] 0x0 0x0111 ...
Page 27
ADE3700 Register Name SMEAS_V_CTRL SMEAS_H_SEL Table 9: Sync Measurement (Sheet Addr Mode Bits Default 0x0112 [7:5] R/W [4] 0x0 R/W [3] 0x0 R/W [2] 0x0 R/W [1] 0x0 R/W [0] 0x0 0x0113 [7:4] R/W [3:0] 0x0 Sync ...
Page 28
Sync Measurement Register Name SMEAS_V_SEL SMEAS_STATUS_MASK SMEAS_H_NUM_LINES SMEAS_H_SKIP_L 28/89 Table 9: Sync Measurement (Sheet Addr Mode Bits Default 0x0114 R/W [7:4] 0x0 R/W [3:0] 0x0 0x0119 R/W [7] 0x0 R/W [6] 0x0 [5:4] R/W [3] 0x0 R/W ...
Page 29
ADE3700 Register Name SMEAS_H_SKIP_H SMEAS_SKEW_CTRL SMEAS_SKEW_THRES SMEAS_DELAY_VSYNC SMEAS_REF_XK_PER_H_L SMEAS_REF_XK_PER_H_M SMEAS_REF_XK_PER_H_H SMEAS_REF_XK_PER_V_L SMEAS_REF_XK_PER_V_M SMEAS_REF_XK_PER_V_H SMEAS_REF_H_PER_V_L SMEAS_REF_H_PER_V_H SMEAS_REF_XK_V_PER_HI_L SMEAS_REF_XK_V_PER_HI_M SMEAS_REF_XK_V_PER_HI_H SMEAS_REF_POLARITY SMEAS_XK_HTOL_EXP SMEAS_XK_VTOL_EXP Table 9: Sync Measurement (Sheet Addr Mode Bits Default 0x011C R/W [7:4] [3:0] 0x011D [7:3] 0x0 ...
Page 30
Sync Measurement Register Name SMEAS_HSYNC_VTOL SMEAS_FILTR_HS_WIDTH SMEAS_ACT_POLLING SMEAS_ANA_ACT SMEAS_ANA_STUCK SMEAS_XK_PER_H_L SMEAS_XK_PER_H_M SMEAS_XK_PER_H_H SMEAS_XK_PER_V_L SMEAS_XK_PER_V_M SMEAS_XK_PER_V_H SMEAS_H_PER_V_L SMEAS_H_PER_V_H SMEAS_SK_V_HI_L SMEAS_SK_V_HI_M SMEAS_SK_V_HI_H SMEAS_TIMEOUT_STATUS 30/89 Table 9: Sync Measurement (Sheet Addr Mode Bits Default 0x012E [7:4] 0x0 R/W [3:0] 0x0 ...
Page 31
ADE3700 Register Name SMEAS_STATUS_RANGE SMEAS_MEAS_POLLING SMEAS_SKEW_STATUS Table 9: Sync Measurement (Sheet Addr Mode Bits Default 0x0152 R [7] 0x0 R [6] 0x0 R [5] 0x0 R [4] 0x0 R [3] 0x0 R [2] 0x0 R [1] 0x0 ...
Page 32
Sync Multiplexer (SMUX) Register Name SMEAS_V_OUTOF_RNG SMEAS_H_OUTOF_RNG SMEAS_HV_OUTOF_RNG SMEAS_VHI_OUTOF_RNG SMEAS_HPOL_OUTOF_RNG SMEAS_VPOL_OUTOF_RNG 2.7 Sync Multiplexer (SMUX) The Synchronization Multiplexer (SMUX) selects a set of sync signals from the input sources and provides them to the scaler. It generates signals that are ...
Page 33
ADE3700 2.7.1 Functional Description The internal signal selector selects which of the input sources are to be used for the internal hsync, vsync and enab signals and is controlled by I2C register SMUX_CTRL0. The signal generator contains a horizontal and ...
Page 34
Sync Multiplexer (SMUX) When hsync and/or vsync is generated (e.g. when enab is the only input), the relative position of the generated pulse can be set either before or after the reference edge between -128 and +127 pixels per line. ...
Page 35
ADE3700 Register Name SMUX_CTRL1 SMUX_CTRL2 Table 11: Sync Multiplexer Registers (Sheet Addr Mode Bits Default 0x0201 R/W [7] 0x0 R/W [6] 0x0 R/W [5] 0x0 R/W [4] 0x0 R/W [3] 0x0 R/W [2] 0x0 R/W [1] 0x0 ...
Page 36
Sync Multiplexer (SMUX) Register Name SMUX_CTRL3 SMUX_CLAMP_SET_L SMUX_CLAMP_SET_U SMUX_CLAMP_RST_L SMUX_CLAMP_RST_U SMUX_HENAB_SET_L HENAB _SET_U HENAB _RST_L HENAB _RST_U VENAB_SET_L VENAB _SET_U VENAB _RST_L VENAB _RST_U 36/89 Table 11: Sync Multiplexer Registers (Sheet Addr Mode Bits Default 0x0203 R ...
Page 37
ADE3700 Register Name HSYNC_PHASE VSYNC_PHASE HENAB_SET_HW_L HENAB _SET_HW _U HENAB _RST_HW _L HENAB _RST_HW _U VENAB_SET_HW _L VENAB _SET_HW _U VENAB _RST_HW _L VENAB _RST_HW _U 2.8 Data Multiplexer The Data Multiplexer provides the following functions: Debug modes (e.g. bit ...
Page 38
Data Measurement (DMEAS) 2.9 Data Measurement (DMEAS) The Data Measurement (DMEAS) module measures several characteristics of the data and sync signals. Data measurements are taken over a programmable window as defined by an upper left (mix_x, min_y) and a lower ...
Page 39
ADE3700 2.9.4 Pixel Cumulative Distribution (PCD) The Pixel Cumulative Distribution (PCD) function reports the total number of pixels greater than (or less than) a programmable threshold. To switch between pixels greater than or pixels less than the threshold, a control ...
Page 40
Data Measurement (DMEAS) 2.9.7 DE Size The DE Size measures the number of INCLKS clock cycles per data enable useful for DVI inputs to exactly measure the input image horizontal size. At the end of the measurement (DE ...
Page 41
ADE3700 Table 14: Data Measurement Registers (Sheet Register Name DMEAS_MODE_CTRL DMEAS_THRESHOLD DMEAS_WIN_MIN_X_L DMEAS_WIN_MIN_X_H DMEAS_WIN_MAX_X_L DMEAS_WIN_MAX_X_H DMEAS_WIN_MIN_Y_L DMEAS_WIN_MIN_Y_H DMEAS_WIN_MAX_Y_L DMEAS_WIN_MAX_Y_H DMEAS_DE_REF_L DMEAS_DE_REF_L DMEAS_DE_TOL DMEAS_DATA_0 DMEAS_DATA_1 DMEAS_DATA_2 DMEAS_DATA_3 DMEAS_DATA_4 DMEAS_DATA_5 DMEAS_DATA_6 DMEAS_DATA_7 Addr Mode Bits Default 0x0901 R/W [7] ...
Page 42
LCD Scaler Table 14: Data Measurement Registers (Sheet Register Name DMEAS_SCR_PAD_0 DMEAS_SCR_PAD_1 DMEAS_SCR_PAD_2 DMEAS_SCR_PAD_3 DMEAS_SCR_PAD_4 DMEAS_SCR_PAD_5 DMEAS_SCR_PAD_6 DMEAS_SCR_PAD_7 DMEAS_SCR_PAD_8 DMEAS_SCR_PAD_9 DMEAS_SCR_PAD_10 DMEAS_SCR_PAD_11 DMEAS_SCR_PAD_12 DMEAS_SCR_PAD_13 DMEAS_SCR_PAD_14 DMEAS_SCR_PAD_15 2.10 LCD Scaler The LCD Scaler module resizes images from one ...
Page 43
ADE3700 Register Name SCL_ORIGHPOS_0 SCL_ORIGHPOS_1 SCL_ORIGHPOS_2 SCL_ORIGHPOS_3 SCL_ORIGVPOS_E_0 SCL_ORIGVPOS_E_1 SCL_ORIGVPOS_E_2 SCL_ORIGVPOS_E_3 SCL_THRES_SLOPE SCL_THRES_OFFSET_L SCL_THRES_OFFSET_H SCL_CBBYPASS SCL_CON_CAL_SEL SCL_TESTCON SCL_LUT1 SCL_LUT2 SCL_LUT3 SCL_LUT4 SCL_LUT5 SCL_LUT6 Table 15: LCD Scaler Registers (Sheet Addr Mode Bits 0x0A0A R/W [7:0] 0x0A0B R/W ...
Page 44
LCD Scaler Register Name SCL_LUT7 SCL_LUT8 SCL_LUT9 SCL_LUT10 SCL_LUT11 SCL_LUT12 SCL_LUT13 SCL_LUT14 SCL_LUT15 SCL_BGCOLOR_R SCL_BGCOLOR_G SCL_BGCOLOR_B SCL_BCOLOR_CTRL 44/89 Table 15: LCD Scaler Registers (Sheet Addr Mode Bits 0x0A22 R/W [7:0] 0x17 0x0A23 R/W [7:0] 0x21 0x0A24 R/W ...
Page 45
ADE3700 2.11 Output Sequencer The Output Sequencer module synchronizes timing for the output video interface. It allows sufficient flexibility to support a broad range of Smart Panel applications as well using the Output Timing Controller (TCON) module, refer to horizontal ...
Page 46
Output Sequencer alternate output sync pins (AHS, AUS, ADE) for applications that do not require the more sophisticated timing control provided by the programmable TCON module. Table 16: Output Sequencer Registers (Sheet Register Name OSQ_CONTROL OSQ_CLOCK_FRAC OSQ_OUT_HTOTAL_L ...
Page 47
ADE3700 Table 16: Output Sequencer Registers (Sheet Register Name OSQ_VERTEN_DLY_O_L OSQ_VERTEN_DLY_O_M OSQ_VERTEN_DLY_O_H OSQ_VSYNC_SET_L OSQ_VSYNC_SET_H OSQ_VSYNC_RST_L OSQ_VSYNC_RST_H OSQ_HSYNC_SET_L OSQ_HSYNC_SET_H OSQ_HSYNC_RST_L OSQ_HSYNC_RST_H OSQ_HENAB_SET_L OSQ_HENAB_SET_H OSQ_HENAB_RST_L OSQ_HENAB_RST_H OSQ_VENAB_SET_L OSQ_VENAB_SET_H OSQ_VENAB_RST_L OSQ_VENAB_RST_H OSQ_OUT_VCOUNT Addr Mode Bits Default 0x0BCC R/W [7:0] 0x0 ...
Page 48
Timing Controller (TCON) 2.12 Timing Controller (TCON) The Output Timing Controller module provides timing for Smart Panel applications and other applications that are sensitive to output synchronization timing. The timing unit is based on horizontal and vertical counters, which are ...
Page 49
ADE3700 Register Name TCON_COMP_10_L TCON_COMP_10_H TCON_COMP_11_L TCON_COMP_11_H TCON_COMP_12_L TCON_COMP_12_H TCON_COMP_13_L TCON_COMP_13_H TCON_COMP_14_L TCON_COMP_14_H TCON_COMP_15_L TCON_COMP_15_H TCON_COMP_16_L TCON_COMP_16_H TCON_COMP_17_L TCON_COMP_17_H TCON_COMP_18_L TCON_COMP_18_H TCON_COMP_19_L TCON_COMP_19_H TCON_COMP_20_L TCON_COMP_20_H TCON_COMP_21_L TCON_COMP_21_H TCON_COMP_22_L TCON_COMP_22_H TCON_COMP_23_L TCON_COMP_23_H TCON_COMP_24_L TCON_COMP_24_H TCON_COMP_25_L TCON_COMP_25_H TCON_COMP_26_L TCON_COMP_26_H Table 17: TCON ...
Page 50
Timing Controller (TCON) Register Name TCON_COMP_27_L TCON_COMP_27_H TCON_SRTD_0 TCON_SRTD_1 TCON_SRTD_2 TCON_SRTD_3 TCON_SRTD_4 TCON_SRTD_5 TCON_SRTD_6 TCON_SRTD_7 TCON_SRTD_8 TCON_SRTD_9 TCON_SRTD_10 TCON_SRTD_11 TCON_SRTD_12 TCON_SRTD_13 TCON_SRTD_14 TCON_SRTD_15 TCON_SRTD_16 TCON_SRTD_17 TCON_SRTD_18 TCON_SRTD_19 TCON_SRTD_20 TCON_SRTD_21 TCON_SRTD_22 TCON_SRTD_23 TCON_SRTD_24 TCON_SRTD_25 50/89 Table 17: TCON Registers (Sheet 3 ...
Page 51
ADE3700 Register Name TCON_SRTD_26 TCON_SRTD_27 TCON_SRTD_28 TCON_SRTD_29 TCON_SRTD_30 TCON_SRTD_31 TCON_X_0 TCON_X_1 TCON_X_2 TCON_X_3 TCON_X_4 TCON_X_5 TCON_X_6 TCON_X_7 TCON_X_8 TCON_X_9 TCON_X_10 TCON_X_11 TCON_X_12 TCON_X_13 TCON_X_14 TCON_X_15 TCON_X_16 TCON_X_17 Table 17: TCON Registers (Sheet Addr. Mode Bits Default 0x0B6A ...
Page 52
Timing Controller (TCON) Register Name TCON_X_18 TCON_X_19 TCON_X_20 TCON_X_21 TCON_X_22 TCON_X_23 TCON_X_24 TCON_X_25 TCON_X_26 TCON_X_27 TCON_X_28 TCON_X_29 TCON_X_30 TCON_X_31 TCON_X_32 TCON_X_33 TCON_X_34 TCON_X_35 TCON_X_36 TCON_X_37 TCON_X_38 TCON_X_39 52/89 Table 17: TCON Registers (Sheet Addr. Mode Bits Default ...
Page 53
ADE3700 Register Name TCON_X_40 TCON_X_41 TCON_X_42 TCON_X_43 TCON_X_44 TCON_X_45 TCON_X_46 TCON_X_47 TCON_X_48 TCON_X_49 TCON_X_50 TCON_X_51 TCON_X_52 TCON_X_53 TCON_X_54 TCON_X_55 TCON_X_56 TCON_X_57 TCON_X_58 TCON_X_59 TCON_X_60 TCON_X_61 Table 17: TCON Registers (Sheet Addr. Mode Bits Default 0x0BA8 R/W [7:0] ...
Page 54
Pattern Generator Register Name TCON_X_62 TCON_X_63 Value 0x00 0 0x01 1 0x02 External TCON input pin 0x03 I2C SRTD init bit 0x04 - 0x1F comp0 - comp27 0x20 - 0x37 SRTD8 - SRTD31 0x38 2 frame + 1 line + ...
Page 55
ADE3700 When the programmed block size is such that the complete 8x8 grid is smaller than the total screen area, the part of the screen area which is outside the 8x8 grid is forced to black. 2.13.2 Pattern Engine In ...
Page 56
Pattern Generator Register Name PGEN_GRID3 PGEN_GRID4 PGEN_GRID5 PGEN_GRID6 PGEN_GRID7 PGEN_GRID_X_L PGEN_GRID_X_H PGEN_GRID_Y_L PGEN_GRID_Y_H PGEN_GRID_X_OFFSET_X_L PGEN_GRID_X_OFFSET_X_H PGEN_GRID_Y_OFFSET_Y_L PGEN_GRID_Y_OFFSET_Y_H PGEN_P0_MODE PGEN_P1_MODE PGEN_P0_WIDTH_X_L PGEN_P0_WIDTH_X_H PGEN_P0_WIDTH_X_OFFSET_L 56/89 Table 19: PGEN Registers (Sheet Addr Mode Bits Default 0x0604 R/W [7:0] 0x0 0x0605 ...
Page 57
ADE3700 Register Name PGEN_P0_WIDTH_X_OFFSET_H PGEN_P0_HEIGHT_Y_L PGEN_P0_HEIGHT_Y_H PGEN_P0_HEIGHT_Y_OFFSET_L PGEN_P0_HEIGHT_Y_OFFSET_H PGEN_P1_WIDTH_X_L PGEN_P1_WIDTH_X_H PGEN_P1_WIDTH_X_OFFSET_L PGEN_P1_WIDTH_X_OFFSET_H PGEN_P1_HEIGHT_Y_L PGEN_P1_HEIGHT_Y_H PGEN_P1_HEIGHT_Y_OFFSET_L PGEN_P1_HEIGHT_Y_OFFSET_H PGEN_P0_COLOR_R_C0 PGEN_P0_COLOR_G_C0 PGEN_P0_COLOR_B_C0 PGEN_P0_COLOR_R_C1 PGEN_P0_COLOR_G_C1 PGEN_P0_COLOR_B_C1 PGEN_P1_COLOR_R_C0 PGEN_P1_COLOR_G_C0 PGEN_P1_COLOR_B_C0 PGEN_P1_COLOR_R_C1 PGEN_P1_COLOR_G_C1 PGEN_P1_COLOR_B_C1 PGEN_P0_GRADDELTA_R PGEN_P0_GRADDELTA_G PGEN_P0_GRADDELTA_B Table 19: PGEN Registers (Sheet Addr ...
Page 58
Pattern Generator Register Name PGEN_P0_GRADSTEP_X PGEN_P0_GRADSTEP_Y PGEN_P1_GRADDELTA_R PGEN_P1_GRADDELTA_G PGEN_P1_GRADDELTA_B PGEN_P1_GRADSTEP_X PGEN_P1_GRADSTEP_Y PGEN_P0_SEQ_COL0_COL1 PGEN_P0_SEQ_COL2_COL3 PGEN_P0_SEQ_COL4_COL5 PGEN_P0_SEQ_COL6_COL7 PGEN_P1_SEQ_COL0_COL1 PGEN_P1_SEQ_COL2_COL3 PGEN_P1_SEQ_COL4_COL5 58/89 Table 19: PGEN Registers (Sheet Addr Mode Bits Default 0x0632 R/W [7:0] 0x0 0x0633 R/W [7:0] 0x0 0x0634 ...
Page 59
ADE3700 Register Name PGEN_P1_SEQ_COL6_COL7 PGEN_B_TOP_BOTTOM PGEN_B_LEFT_RIGHT PGEN_X_TOTAL_L PGEN_X_TOTAL_H PGEN_Y_TOTAL_L PGEN_Y_TOTAL_H Table 19: PGEN Registers (Sheet Addr Mode Bits Default 0x0640 [7] R/W [6:4] 0x0 [3] R/W [2:0] 0x0 0x0641 R/W [7] 0x0 R/W [6] 0x0 R/W [5] ...
Page 60
The sRGB block performs two primary functions: 1. Parametric gamma correction on multiple windows or full screen, used for video enhancement in a window and digital contrast/brightness control. The window coordinates are set by TCON registers. 2. ...
Page 61
ADE3700 Register Name SRGB_BLACK_G SRGB_BLACK_B SRGB_RED_R SRGB_RED_G SRGB_RED_B SRGB_GREEN_R SRGB_GREEN_G SRGB_GREEN_B SRGB_BLUE_R SRGB_BLUE_G SRGB_BLUE_B SRGB_YELLOW_R SRGB_YELLOW_G SRGB_YELLOW_B SRGB_CYAN_R SRGB_CYAN_G SRGB_CYAN_B SRGB_MAGENTA_R SRGB_MAGENTA_G SRGB_MAGENTA_B SRGB_WHITE_R SRGB_WHITE_G SRGB_WHITE_B SRGB_GAMMA_A_RED_A SRGB_GAMMA_A_RED_B SRGB_GAMMA_A_RED_C SRGB_GAMMA_A_GREEN_A SRGB_GAMMA_A_GREEN_B SRGB_GAMMA_A_GREEN_C SRGB_GAMMA_A_BLUE_A SRGB_GAMMA_A_BLUE_B SRGB_GAMMA_A_BLUE_C SRGB_GAMMA_B_RED_A SRGB_GAMMA_B_RED_B SRGB_GAMMA_B_RED_C Table 20: ...
Page 62
On-Screen Display (OSD) Register Name SRGB_GAMMA_B_GREEN_A SRGB_GAMMA_B_GREEN_B SRGB_GAMMA_B_GREEN_C SRGB_GAMMA_B_BLUE_A SRGB_GAMMA_B_BLUE_B SRGB_GAMMA_B_BLUE_C 2.15 On-Screen Display (OSD) The integrated On-Screen Display (OSD) controller is a character-based overlay with a high level of features and over 100 kbits of on-board dedicated RAM storage. ...
Page 63
ADE3700 Character Display There are two 96-character monochrome fonts and two 32-character four-bit color fonts, a total of 256 characters. The four bits of color are an index into one of two 16 entry color lookup tables. Entries in the ...
Page 64
On-Screen Display (OSD) effects. An alpha value of 255 makes the OSD opaque, while a value of 0 makes the OSD invisible, with a linear ramp of transparency between these two endpoints. Separate registers control alpha for foreground and background ...
Page 65
ADE3700 Header Byte Bits Description First [7:4] Type of data transfer. Valid values are: 0x8: screen map 0x9: color LUT 0xA: attribute map 0xC: font data all others: Reserved [3:0] For screen map or attribute map access, this is the ...
Page 66
On-Screen Display (OSD) Table 22: OSD Attribute Map Definition (Sheet Row Column 66/89 Bits 15 [7] 0: OSD off 1: OSD on [6:5] 0x0: plain characters 0x1: border ...
Page 67
ADE3700 Table 22: OSD Attribute Map Definition (Sheet Row Column Bits 7 [7:3] Window 2 Column Start [2] Window 2 Visibility 0: Off 1: On [1] Reserved [0] ...
Page 68
Flicker Table 22: OSD Attribute Map Definition (Sheet Row Column Register Name OSD_PORT 2.16 Flicker The Flicker block computes correlations of the image data with potential inversion patterns ...
Page 69
ADE3700 Refer to the Flicker Programming Guide for more details. Register Name FLK_CTRL FLK_HBLOCK_SIZE FLK_FRAME_CNT_MAX FLK_MEAS0_0 FLK_MEAS0_1 FLK_MEAS0_2 FLK_MEAS0_3 FLK_MEAS1_0 FLK_MEAS1_1 FLK_MEAS1_2 FLK_MEAS1_3 FLK_MEAS2_0 FLK_MEAS2_1 FLK_MEAS2_2 Table 24: Flicker Registers (Sheet Addr Mode Bits Default 0x0CA1 R/W ...
Page 70
Gamma Register Name FLK_MEAS2_3 FLK_MEAS3_0 FLK_MEAS3_1 FLK_MEAS3_2 FLK_MEAS3_3 FLK_MEAS4_0 FLK_MEAS4_1 FLK_MEAS4_2 FLK_MEAS4_3 FLK_MEAS5_0 FLK_MEAS5_1 FLK_MEAS5_2 FLK_MEAS5_3 FLK_MEAS6_1 FLK_MEAS6_2 FLK_MEAS6_3 FLK_MEAS6_4 FLK_MEAS7_0 FLK_MEAS7_1 FLK_MEAS7_2 FLK_MEAS7_3 2.17 Gamma The Gamma block performs an 8-bit to 10-bit lookup table on the 3 x ...
Page 71
ADE3700 Register Name GAMMA_CTRL 2.18 APC APC (formerly known as Arithmos Perfect Color) dithers an input 10 bit video stream down to 4-8 output bits. The dithering is done in space and time in such a way that the eye ...
Page 72
Output Multiplexer 2.19 Output Multiplexer The Output Multiplexer formats the single wide data stream from the output of the APC block into a single or double wide data path for the flat panel. The architecture is shown in 8 Right ...
Page 73
ADE3700 2.19.1 Sub Block Function 2.19.1.1 Right Shift shifts right from positions, fills from the top with zeroes out_mux_ctrl1[2:0] 2.19.1.2 Byte Flip flips data bits in a byte from LSB to MSB, i.e. out[7:0] = in[0:7] out_mux_ctrl0[4] ...
Page 74
Output Multiplexer last point the data is flopped with DCLK before the pins gated clock available from tcon_srtd[12] in tcon mode see tables 2.2 - 2.5 for configurations. Enable Data OUT_MUX_CTRL0[0] Enable OUT_MUX_CTRL1[3] TCON OUT_MUX_CTRL0[2] Double OUT_MUX_CTRL0[1] ...
Page 75
ADE3700 ORA0 OBB7 OBB6 OBB5 OBB4 OBB3 OBB2 OBB1 OBB0 OGB7 OGB6 OGB5 OGB4 OGB3 OGB2 OGB1 OGB0 ORB7 ORB6 ORB5 ORB4 ORB3 ORB2 ORB1 ORB0 tci13 = tcon_in13, orb7 = output red B channel bit 7, rda3 = red ...
Page 76
Output Multiplexer enable data OUT_MUX_CTRL0[0] enable tcon OUT_MUX_CTRL1[3] ENAB_OUT HSYNC_OUT VSYNC_OUT eni = enab_in, hsi = hsync_in, vsi = vsync_in. enable tcon enable PWM PWM mux mode 2.19.2 RSDS In RSDS mode, clk and hsync outputs are the differential clock ...
Page 77
ADE3700 RSDS Time t+2 t+3 Note: hsync_o is the positive clock signal according to the RSDS definition. 2.19.3 Per Pin Delay Each of the 60 outputs has a per pin programmable delay. The delay is calibrated on the fly to ...
Page 78
Output Multiplexer Register Name OMUX_CTRL_2 OMUX_DLY_BA0 OMUX_ DLY_BA2 OMUX_ DLY_BA4 OMUX_ DLY_BA6 OMUX_ DLY_GA0 OMUX_ DLY_GA2 OMUX_ DLY_GA4 OMUX_ DLY_GA6 OMUX_ DLY_RA0 OMUX_ DLY_RA2 OMUX_ DLY_RA4 OMUX_ DLY_RA6 OMUX_ DLY_BB0 78/89 Table 32: Output Mux Registers (Sheet ...
Page 79
ADE3700 Register Name OMUX_ DLY_BB2 OMUX_ DLY_BB4 OMUX_ DLY_BB6 OMUX_ DLY_GB0 OMUX_ DLY_GB2 OMUX_ DLY_GB4 OMUX_ DLY_GB6 OMUX_ DLY_RB0 OMUX_ DLY_RB2 OMUX_ DLY_R_B4 OMUX_ DLY_R_B6 OMUX_ DLY_TCON_0 OMUX_ DLY_TCON_2 OMUX_ DLY_TCON_4 OMUX_ DLY_TCON_6 OMUX_ DLY_VS_ENAB OMUX_ DLY_CLK_HS Table 32: Output ...
Page 80
Pulse Width Modulation (PWM) Register Name OMUX_CTRL_3 OMUX_REFCOUNT 2.20 Pulse Width Modulation (PWM) The PWM block generates two signals that can be used to control backlight inverter switching power components directly derived from XCLK and can be powered ...
Page 81
ADE3700 Register Name PWM_CTRL1 PWM_PERIOD_L PWM_PERIOD_H PWM_DUTY_L PWM_DUTY_H PWM_OVERLAP_L PWM_OVERLAP_H PWM_STEP_DELAY PWM_CYCLES_PER_FRAME_L PWM_CYCLES_PER_FRAME_H 2.21 DFT Block Register Name DFT_TEST_MODE DFT_MUX_OUT_MODE DFT_FLOP_OUT_MODE DFT_CLK_0UT_MODE DFT_CLK_1_MODE Table 33: PWM Registers (Sheet Addr Mode Bits Default 0x01A1 R/W [7:4] 0x0 R/W ...
Page 82
DFT Block Register Name DFT_CLK_2_MODE DFT_OUT_DISAB_0 DFT_OUT_DISAB_1 DFT_OUT_DISAB_2 DFT_OUT_DISAB_3 DFT_OUT_DISAB_4 DFT_OUT_DISAB_5 DFT_OUT_DISAB_6 DFT_OUT_DISAB_7 DFT_STIM_CTRL DFT_STIM_EN_0 DFT_STIM_EN_1 DFT_BIST_STATUS 82/89 Table 34: DFT Registers (Sheet Addr Mode Bits Default 0x0F05 R/W [5:0] 0x0 0x0F06 R/W [7:0] 0x0 0x0F07 R/W ...
Page 83
ADE3700 Register Name DFT_BIST_RESULT_0 DFT_BIST_RESULT_1 DFT_MFSR_DONE DFT_MFSR_SIG_0 DFT_MFSR_SIG_1 DFT_MFSR_SIG_2 DFT_MFSR_SIG_3 2.22 I²C RAM Addresses Name GAM_RED GAM_GREEN GAM_BLUE OSD_MB OSD_CS OSD_DRB SCL_COEFF SCL_LINE1 SCL_LINE2 SCL_LINE3 SCL_LINE4 Table 34: DFT Registers (Sheet Addr Mode Bits Default 0x0F12 [7:6] ...
Page 84
Absolute Maximum Ratings 3 Electrical Specifications 3.1 Absolute Maximum Ratings Symbol AVDD18 Supply voltage DVDD18 XVDD18 LVDD18 AVDD33 Supply voltage DVDD33 VIN Max voltage on 5 volt tolerant input pins T Storage temperature STG 3.2 Power Consumption Matrices Symbol Supply ...
Page 85
ADE3700 3.3 Nominal Operating Conditions Symbol AVDD18 Supply Voltage DVDD18 XVDD18 LVDD18 AVDD33 Supply Voltage DVDD33 f Crystal Frequency XTAL T Ambient Operating Temperature OPER 3.4 Preliminary Thermal Data Symbol R Junction-to-Ambient Thermal Resistance, 144-pin package thJA R Junction-to-Ambient Thermal ...
Page 86
Preliminary AC Specifications 3.5.3 LVTTL 5 Volt Tolerant I/O With Hysteresis SDA Symbol Parameter V High Level Input Voltage IH V Low Level Input Voltage IL V Schmitt Trigger Hysteresis HYST 3.5.4 LVTTL Outputs OBA[0:7], OGA[0:7], ORA[0:7], OBB[0:7], OGB[0:7], ORB[0:7], ...
Page 87
ADE3700 4 Package Mechanical Data Min 1.400 b 0.220 D 22.000 D1 20.000 D2 E 16.000 E1 14.000 E2 e 0.500 L 0.600 L1 1.000 Pin 1 Identification ...
Page 88
Preliminary AC Specifications 5 Revision History Date Version 12 August 2002 0.1 First Draft 23 August 2002 0.2 Addition of diagram on Cover. Modification of Description and Product Selector info on 1st page. Modification of Registers. Modification of Registers, 17 ...
Page 89
... This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States ...