ADM7008 ADMtek, ADM7008 Datasheet
ADM7008
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ADM7008 Summary of contents
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... ADM7008 Octal Ethernet 10/100M PHY ADMtek com.tw . Information in this document is provided in connection with ADMtek products. ADMtek may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined”. ADMtek ...
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... Chapter 6. Packaging Revision History Date 23 January 2003 28 October 2003 Customer Support ADMtek Incorporated, 2F, No.2, Li-Hsin Rd., Science-based Industrial Park, Hsinchu, 300, Taiwan, R.O.C. Sales Information Tel + 886-3-5788879 Fax + 886-3-5788871 ADM7008 Version Change 1.0 First release of ADM7008 1.1 Updated Chapters 2, 3, & 4 V1.1 ...
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... Jabber Function ..................................................................................... 3-10 3.1.14 Link Test Function ................................................................................. 3-10 3.1.15 Automatic Link Polarity Detection ........................................................ 3-11 3.1.16 Clock Synthesizer ................................................................................... 3-11 3.1.17 Auto Negotiation .................................................................................... 3-11 3.1.18 Auto Negotiation and Speed Configuration........................................... 3-12 3.2 MAC Interface ............................................................................................... 3-13 3.2.1 Reduced Media Independent Interface (RMII) ...................................... 3-13 ADM7008 V1.1 i ...
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... Register #19h – Interrupt Status Register................................................ 4-3 4.2.18 Register #1dh – Receive Error Counter .................................................. 4-4 4.2.19 Register #1eh – Chip ID (8888 4.2.20 Register #1fh –Total Interrupt Status (only For Port 0).......................... 4-4 4.3 Register Description......................................................................................... 4-4 4.3.1 Control (Register 0h) ............................................................................... 4-4 4.3.2 Status (Register 1h).................................................................................. 4-6 ADM7008 ............................................................... 4-4 ) V1.1 ii ...
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... REFCLK Input Timing (When REFCLK_SEL is set ..................... 5-7 5.4.2 REFCLK Output Timing (When REFCLK_SEL is set to 1)..................... 5-8 5.4.3 SMII/SS_SMII Transmit Timing............................................................... 5-9 5.4.4 SMII/SS_SMII Receive Timing............................................................... 5-10 5.5 Serial Management Interface (MDC/MDIO) Timing.................................... 5-11 5.6 Power On Configuration Timing ................................................................... 5-12 Chapter 6 Packaging...................................................................................................... 6-1 ADM7008 V1.1 iii ...
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... ADMtek Inc. Figure 1-1 ADM7008 Block Diagram............................................................................. 1-2 Figure 2-1 ADM7008 Pin Assignment ............................................................................ 2-1 Figure 3-1 ADM7008 Switch Application (10/100M TP Mode) .................................... 3-1 Figure 3-2 100Base-X Block Diagram and Data Path..................................................... 3-3 Figure 3-3 10Base-T Block Diagram and Data Path ..................................................... 3-10 Figure 3-4 RMII Signal Diagram................................................................................... 3-13 Figure 3-5 RMII Reception Without Error ...
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... Table 5-9 REFCLK Input Timing.................................................................................... 5-7 Table 5-10 SMII/SS_SMII REFCLK Output Timing ..................................................... 5-8 Table 5-11 SMII/SS_SMII Transmit Timing .................................................................. 5-9 Table 5-12 SMII/SS_SMII Receive Timing .................................................................. 5-10 Table 5-13 Serial Management Interface (MDC/MDIO) Timing ................................. 5-11 Table 5-14 Power On Configuration Timing................................................................. 5-12 ADM7008 List of Tables V1.1 v ...
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... Product Overview 1.1 Overview The ADM7008 is a single chip eight port 10/100M PHY, which is designed for today’s low cost and low power dual speed application. It supports eight auto sensing 10/100 Mbps ports with on-chip clock recovery and base line wander correction including integrated MLT-3 functionality for 100 Mbps operation. ...
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... SS_SMII MAC Interf ace MII RMII MII SS_SMII MII Auto Negotiation 10M Module Cable Broken Detector Driv er Twisted Pair Interface Figure 1-1 ADM7008 Block Diagram Product Review Serial / LED Parallel Display LED MDC/MDIO SMI Power Management CLOCK GENERATOR Voltage Regulator 1-2 ...
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... ADM7008 1.4 Abbreviations ANSI BER COL CRS CRSDV CTL DSP DUPCOL ESD FEFI FIFO FLP FX IA LFSR LLP LNKACT LVTTL MAC MD MDC MDIO MII NRZ NRZI OP PCS PECL PHY PHYADDR PMA PMD PNP PQFP REFCLK RF RMII RSMODE RXC RXD RXDV RXER RXN ADMtek Inc ...
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... ADM7008 RXP RX_SYNC SDN SDP SELFX SMI SMII SOHO SQE SSD SS_SMII SYNC TA TDR TP TP-PMD TTL TXC TXCLK TXD TXEN TXER TXN TXP /J/K /T/R 1.5 Conventions 1.5.1 Data Lengths qword dword word byte nibble 1.5.2 Register Type Descriptions Register Type ...
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... ADM7008 LH COR 1.5.3 Pin Type Descriptions Pin Type I: O: I/O: OD: SCHE: PU: PD: ADMtek Inc. Latching high, unlatch on read Clear On Read Description Input Output Bi-directional Open drain Schmitt Trigger Pull Up Pull Down Product Review 1-5 ...
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... TXP6 3 2 TXN6 3 3 GNDRT 3 4 RXP6 3 5 RXN6 3 6 VCCAD 3 7 RXN7 3 8 RXP7 ADMtek Inc. Figure 2-1 ADM7008 Pin Assignment Interface Description 102 MDC 101 MDIO 100 TXEN_P1/ TXD0_P1/TXD_P1 9 8 TXD1_P1/LNKACT_P1 9 7 CRSDV_P1/NA (SELFX1 RXD0_P1/RXD_P1 (TESTSEL1 RXD1_P1/SPDLED_P1 (REC_10M_P1) ...
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... Power used by I/O Power Digital 1.8V Power used by Core Power Type Description I, PD RMII and SMII/SS_SMII mode select signal. Dedicated input provided by ADM7008 to determine the interface: 0: SMII or SS_SMII interface (See CRSDV_P6 power on setting for more detail) 1: RMII interface Interface Description 2-2 ...
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... In this mode, REFCLK (pin 112) will output 50M clock in RMII mode (RSMODE1 is set to 1) and 125M clock in either SMII or SS_SMII mode (RSMODE1 is set ADM7008 will use the input of REFCLK (pin 112) as the clock source for internal clock generator. Note: that when RSMODE1 is set to 1 (RMII mode), the input of REFCLK should be 50M ...
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... I, LVTTL, Fiber PAUSE Recommend Value. Value on this pin will be PD latched by ADM7008 during power on reset as Fiber port (See SELFX power on setting for more detail) pause capability control signal. 0: Pause off for all fiber ports 1: Pause on for all fiber ports O, 8mA Port 7 Carrier Sense/Receive Data Valid ...
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... RXD0 must repeat each 10 bits segment 10 times. RXD1 for the designated port is acted as Speed Status LED for port 6. I, RMII/SMII/SS_SMII Configuration bit 0. Value on this pin will LVTTL, be latched by ADM7008 during power on reset as interface PD configuration bit 0. Combined with RSMODE1 (pin 43), three possible interfaces are provided by ADM7008 RSMODE[1:0] Interface 00 ...
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... Recommend Port 5 to operate in 100M Mode (Default) 1: Recommend Port 5 to operate in 10M Mode Lower power Link Pulse Function (Power Saving, LLP) Disable. Value on RXD1 will be latched by ADM7008 during power on reset as power saving disable signal. (See Lower Power Link Pulse Function description for more detail) ...
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... RXD1 for the designated port is acted as Speed Status LED for port 5. I, Twisted Pair PAUSE Recommend Value. Value on this pin will LVTTL, be latched by ADM7008 during power on reset as twisted pair PU port (See SELFX power on setting for more detail) pause capability control signal. 0: Pause off for all twisted pair ports ...
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... Recommend Port 4 to operate in 100M Mode 1: Recommend Port 4 to operate in 10M Mode Twisted Pair Duplex Recommend Value. Value on RXD1 will be latched by ADM7008 during power on reset as duplex recommend value for twisted pair interface. 0: Half Duplex for all twisted pair ports 1: Full Duplex for all twisted pair ports Port 4 RMII Receive Data ...
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... Not Used. Not used in SMII Mode 125M Receive Clock. This pin acts as 125M receive clock when ADM7008 is programmed to SS_SMII mode. All SSS_SMII_RXD are synchronous to the rising edge of this clock. Note: that clock on this pin will not be active during power on reset due to power on setting ...
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... RXD1 for the designated port is acted as Speed Status LED for port 3. I, Industrial Test Mode Select 2. Value on this pin will be latched PD by ADM7008 during power on reset as industrial test mode select bit 2. Pull down for normal operation. For Test Mode, Interface Description 2-10 ...
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... SMII_TXD and SMII_RXD for all ports. SS_SMII Transmit Synchronization Signal. In SS_SMII Mode, this pin sets the bit stream alignment of SSS_SMII_TXD for all ports. I, REC_10M: Value on RXD1_P2 will be latched by ADM7008 PD, during power on reset as Port 2 10M Re-command value Recommend Port 2 to operate in 100M Mode (100M) ...
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... RXD1 for the designated port is acted as Speed Status LED for port 2. I/O, Duplex Recommend Value for Fiber Port. Value on this pin will 8mA be latched by ADM7008 during power on reset as duplex PU recommend value for all fiber ports. 0: Half duplex for all fiber ports. 1: Full duplex for all fiber ports. ...
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... Recommend Port 1 to operate in 10M Mode PD Industrial Test Mode Select 1. Value on RXD0_P1 will be latched by ADM7008 during power on reset as industrial test mode select bit 1. Pull down for normal operation. For Test Mode, See test select 0 for more detail Port 1 RMII Receive Data. RXD[1:0] are the port 1 output di- bits synchronously to REFCLK ...
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... ADM7008 during power on reset as fiber/twisted pair PD interface configuration bit 1. Combined with SELFX0 (Power On setting value on RXD0_P0) to program ADM7008 into 4 different modes. 00: all ports are twisted ports 01: only port 7 is fiber port, and all the other ports are twisted ports. ...
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... RXD1 for the designated port is acted as Speed Status LED for port 0. I/O, Fiber/Twisted Pair Configuration bit 0. Value on RXD1 will be 8mA latched by ADM7008 during power on reset as fiber/twisted pair PD interface configuration bit 1. Combined with SELFX1 (Power On setting value on RXD0_P1) to program ADM7008 into 4 different modes. See SELFX1 for more detail Interface Description 2-15 ...
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... ADM7008 Pin # Pin Name RMII Mode CRSDV_P0 SMII/SS_SMII Mode N/A RMII Mode 108, 109 TXD[1:0]_P0 SMII Mode LNKACT_P0, SMII_TXD_P0 SS_SMII Mode LNKACT_P0, SSSMII_TXD_P0 RMII Mode 110 TXEN_P0 SMII/SS_SMII LOW 2.2.7 ATPG Signals, 2 pins Pin # Pin Name 114 SCAN_EN 113 SCAN_MODE ADMtek Inc. ...
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... I, PHY Address Bit 1. Pure input of ADM7008. Combined with LVTTL PHYADDR0 to form the Most Significant 2 bits of PHY address for ADM7008. The LSB 3 bits will be assigned by ADM7008 automatically according to port number 000 Port 0 001 Port 1 010 Port 2 011 Port 3 ...
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... ADM7008 2.2.11 Regulator Control, 2 pins Pin # Pin Name 117 CONTROL 119 RTX ADMtek Inc. Type Description O, Regulator Control. Analog Voltage Control to external 1.8V Regulator. See 4.2.9 for more function description. I, Constant Voltage Reference. Analog External 1.1kΩ1% resistor connection to ground. Interface Description ...
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... ADM7008 Chapter 3 Function Description ADM7008 integrates eight 100Base-X physical sublayer (PHY), 100Base-TX physical medium dependent (PMD) transceivers, eight complete 10Base-T modules into a single chip for both 10 Mbits/s and 100 Mbits/s Ethernet operation. It also supports 100Base- FX operation through external fiber-optic transceivers. operating in either full-duplex mode or half-duplex mode in either 10 Mbits/s or 100 Mbits/s operation ...
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... The 100Base-X receiver consists of functional blocks required to recover and condition the 125 Mbps receive data stream. The ADM7008 implements the 100Base-X receiving state machine diagram as given in ANSI/IEEE Standard 802.3u, Clause 24. The 125 Mbps receive data stream may originate from the on-chip twisted-pair transceiver in a ADMtek Inc ...
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... ADM7008 100Base-TX application. Alternatively, the receive data stream may be generated by an external optical receiver 100Base-FX application. The receiver block consists of the following functional sub-blocks : • A/D Converter • Adaptive Equalizer and Timing Recovery Module • NRZI/NRZ and Serial/Parallel Decoder Descrambler • ...
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... Symbol Alignment The symbol alignment circuit in the ADM7008 determines code word alignment by recognizing the /J/K delimiter pair. This circuit operates on unaligned data from the descrambler. Once the /J/K symbol pair (11000 10001) is detected, subsequent data is aligned on a fixed boundary ...
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... ADM7008 PCS code-group [4:0] 11110 01001 10100 10101 01010 01011 01110 01111 10010 10011 10110 10111 11010 11011 11100 11101 11111 11000 10001 01101 0111 00100 00000 00001 00010 00011 00101 00110 01000 01100 10000 11001 Table 3-1 Look-up Table for translating 5B Symbols into 4B Nibbles. ...
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... If this condition is detected, then the ADM7008 will assert RXER and present RXD[3:0] = 1110 to the internal MII for the cycles hat correspond to received 5B code-groups until ADMtek Inc. ...
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... FOSD signal is generated internally from the internal signal detect circuit. Transmission of the FEFI idle pattern will continue until link up signal is asserted. If three or more FEFI idle patterns are detected by the ADM7008, then bit 4 of the Basic mode status register (address 1h) is set to one until read by management. Additionally, upon detection of far end fault, all receive and transmit MII activity is disabled/ignored ...
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... Automatic “Signal_Detect” Function Block Due to pin limitation, ADM7008 doesn’t support SDP/SDN in fiber mode, which is used to connect to fiber transceiver to indicate there is signal on the fiber. Instead, ADM7008 use the data on RXP/RXN to detect consecutive 65 “1” on the receive data (Recovered from RXP/RXN) to determine whether “Signal” is detected or not. When the detect condition is true (Consecutive 65 bits “ ...
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... Transmit Driver and Receiver The ADM7008 integrates all the required signal conditioning functions in its 10Base-T block such that external filters are not required. Only one isolation transformer and impedance matching resistors are needed for the 10Base-T transmit and receive interface ...
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... AMC via the SMII. 3.1.13 Jabber Function The jabber function monitors the ADM7008 output and disables the transmitter if it attempts to transmit a longer than legal sized packet. If TXEN is high for greater than 24ms, the 10Base-T transmitter will be disabled. Once disabled by the jabber function, the transmitter stays disabled for the entire time that the TXEN signal is asserted ...
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... Ethernet protocols, so the inclusion of auto negotiation ensures that the highest performance protocol will be selected based on the ability of the link partner. The auto negotiation function within the ADM7008 can be controlled either by internal register access or by the use of configuration pins are sampled. negotiation will not occur until software enables bit 12 in register 0. If auto negotiation is enabled, the negotiation process will commence immediately ...
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... Auto Negotiation and Speed Configuration The twelve sets of four pins listed in Table 3-2 configure the speed capability of each channel of ADM7008. The logic state of these pins is latched into the advertisement register (register address 4h) for auto negotiation purpose. These pins are also used for evaluating the default value in the base mode control register (register 0h) according to Table 3-2 ...
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... The reduced media Independent interface (RMII) is compliant to the RMII consortium’s RMII Rev. 1.2 specification. The REFCLK pin that supplies the 50 MHz reference clock to the ADM7008 is used as the RMII REFCLK signal. All RMII signals with the exception of the assertion of CRSDV_P are synchronous to REFCLK. See figure 3-4 3 ...
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... ADM7008 REFCLK CRSDV RXD RXER Carrier Sense Detected 3.2.3 Receive Path for 10M REFCLK CRSDV 00 00 RXD Preamble/SFD Transition once every 10 cycles In 10M Mode, RXER_P will maintain low all the time due to False Carrier and symbol error is not supported by 10M Mode. ...
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... ADM7008 3.2.4 Transmit Path for 100M Figure 3-7 shows the relationship among REFCLK, TXEN_P and TXD[1:0]_P during a transmit event. TXEN_P and TXD[1:0]_P are synchronous to REFCLK. When TXEN_P is asserted, it indicates that TXD[1:0]_P contains valid data to be transmitted. When TXEN_P is de-asserted, value on TXD[1:0]_P should be ignored odd number of di-bits are presented onto TXD[1:0]_P and TXEN_P, the final di-bit will be discarded by AD2106 ...
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... All signals output from ADM7008 are synchronous to RXCLK. In this mode, REFCLK will be divided generate 25M clock before it is fed into ADM7008 internal PLL block. SS_SMII mode is enabled by setting RSMODE1 (pin 43) to low and placing a pull up resistor on CRSDV_P6. In this mode, CRSDV_P[3] becomes RX_SYNC, CRSDV_P4 becomes RXCLK and TXEN_P4 acts as TX_SYNC ...
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... ADM7008 MAC Figure 3-9 SMII Signal Diagram 3.2.7 100M Receive Path Received data and control information is grouped in 10-bit segments that are delimited by the SYNC signal in SMII mode (or SYNC_RX in SS_SMII mode) as shown in figure 15. Each segment represents a new byte of data. REFCLK SYNC RXD7 CRS RXDV RXD0 RXD1 RXD2 RXD3 RXD4 ...
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... ADM7008 CRS RXDV RXD0 X 0 RXER From Previous Frame X 1 Table 3-3 Receive Data Encoding for SMII/SS_SMII mode 3.2.8 10M Receive Path Similar to 100M Receive path except that each segment is repeated 10 times. The MAC can sample any one of every 10 segments in 10BASE-T mode. The MAC also has to generate a SYNC pulse once every 10 clock cycles ...
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... TXD7 TXER TXEN TXD0 TXD1 TXD2 TXD3 TXD4 TXD_P 3.2.10 10M Transmit Path In 10BASE-T mode, each segment must be repeated 10 times by the MAC. In this mode, the MAC must generate the same data in each of the 10 segments. ADM7008 will sample the incoming data at the 5 REFCLK SYNC ...
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... ADM7008 at the falling edge of LED_CLK. Before describing the serial LED output data format, we tend to describe the meaning of internal parallel LEDs. There are three types of LED supported by ADM7008 internally. The first is LNKACT, which represents the status of Link and Transmit/Receive Activity; the second is SPDLED, which indicates the speed status and the last is DUPCOL, which shows pure duplex status in full duplex and duplex/collision combined status in half duplex ...
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... LED wire connection on PCB board is correct or not. After LED self-test, Table 3-7 and Table 3-8 show the On/Off polarity according to different speed detected by ADM7008. DUPCOL is always set to single color mode display no matter the value of DUALLED is. SPEED ...
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... The high duration for LED_CLK is 40ns and the low duration is 600ns to form 640ns period clock. ADM7008 will burst 24 bit status in one time in order to display internal LINK/Activity, Duplex/Collision and Speed status. When a burst is completed, LED_CLK will keep low for 40 ms and system can use it to distinguish between two bursts ...
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... ADM7008 3.4.1 Preamble Suppression The ADM7008 supports a preamble suppression mode as indicated bit 6 of the basic mode status register (Register 1h). If the station management entity (i.e. MAC or other management controller) determines that all PHYs in the system support preamble suppression by reading this bit, then the station management entity needs not generate preamble for each management transaction ...
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... DETECT” will not be ON. Whenever cable is attached to ADM7008 and the voltage threshold is above +/- 50mV, then SD will be asserted HIGH to indicate that there is cable attached to ADM7008. All internal blocks except Management block will be disabled (reset) before SD is asserted. ...
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... When setting to “1”, ADM7008 transmit Low-power Link Pulse (LLP) to the cable. The waveform of LLP is the same as NLP and FLP, the difference is the period of LLP is around 100ms. Besides the longer period, ADM7008 also lower the transmit-driving current between sending a pulse and a pulse. The TX Power Saving Feature is activated by setting ADM7008 of N-way or 10M capabilities ...
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... Voltage Regulator ADM7008 requires two different levels, 3.3V and 1.8V, of voltage supply to provide the power to different parts of circuitry inside the chip. ADM7008 has a build-in voltage regulator circuitry to generate the 1.8V voltage from 3.3V power source. Therefore, an external PNP power transistor is also needed and the block diagram of voltage regulator is shown as below ...
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... ADM7008 Band-gap Reference Voltage generator V R2 ref V R1+R2 1.8v Internal Circuit of Regulator ADMtek Inc. V ref Control R1 R2 Figure 3-24 External PNP Power Transistor Diagram Function Description V 3.3v PNP Power Transistor V 1.8v 3-27 ...
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... ADM7008 Chapter 4 Register Description Note: Please refer to section ‘1.5.2 Register Type Descriptions’ for an explanation of pin abbreviations. 4.1 Register Mapping Address 0h Control Register 1h Status Register 2h – 3h PHY Identifier Register 2h=002E, 3h=CC23 4h Auto Negotiation Advertisement Register 5h Auto Negotiation Link Partner Ability Register ...
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... ADM7008 4.2 Register Bit Mapping 4.2.1 Register #0h -- Control Register RST LPBK SPD_L ANEN PDN R/W R/W R/W R/W 4.2.2 Register #1h – Status Register CAPT4 TXFUL TXHALF TFUL THALF CAPT2 4.2.3 Register #2h – PHY ID Register (002E) 4.2.4 Register #3h – PHY ID Register (CC11) 4.2.5 Register #4h – ...
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... ADM7008 4.2.10 Register #11h – 10M Configuration Register 4.2.11 Register #12h – 100M Configuration Register 4.2.12 Register #13h – LED Configuration Register LNKC3 LNKC2 LNKC1 LNKC0 DUPC3 DUPC2 DUPC1 DUPC0 4.2.13 Register #14h – Interrupt Enable Register 4.2.14 Register #16h – PHY Generic Status Register ...
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... ADM7008 4.2.18 Register #1dh – Receive Error Counter ERB15 ERB14 ERB13 ERB12 ERB11 4.2.19 Register #1eh – Chip ID (8888 CID33 CID32 CID31 CID30 CID23 4.2.20 Register #1fh –Total Interrupt Status (only For Port INT7 INT6 INT5 INT4 INT3 4.3 Register Description 4 ...
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... ADM7008 Bit # Name Description disabled (bit12 = 0). The specific PHY (10Base-T or 100Base-X) used for this operation is determined by bits 12 and 13. 13 SPEED_LS Speed Selection LSB B 0.60. Link speed is selected by this bit or by auto negotiation if bit 12 of this register is set (in which case, the value of this bit is ignored) ...
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... ADM7008 Bit # Name Description 9 ANEN_RS Restart Auto Negotiation T 1: Restart Auto Negotiation Process 0: Normal Operation Setting this bit while auto negotiation is enabled forces a new auto negotiation process to start. This bit is self-clearing and returns to 0 after the auto negotiation process has commenced. ...
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... ADM7008 Bit # Name Description Duplex mode FX : Set to 0 all the time to indicate that the PHY841F does not support 10M Full Duplex mode 11 CAP_TH 10M Half Duplex Capable TP : Set to 1 all the time to indicate that the PHY841F does support 10M Half Duplex mode ...
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... ADM7008 Bit # Name Description 1: Link Link is down This bit reflects the current state of the link -test-fail state machine. Loss of a valid link causes a 0 latched into this bit. It remains 0 until this register is read by the serial management interface. Whenever Linkup, this bit should be read ...
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... ADM7008 Bit # Name Description 0 This bit is written by serial management interface for the purpose of communicating the remote fault condition to the auto negotiation link partner. 12 Reserved Not Applicable 11 ASM_DIR Asymmetric Pause Direction Bit[11:10] Capability PAUSE Pause Operation for Full Duplex Value on PAUREC will be stored in this bit during power on reset ...
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... ADM7008 Bit # Name Description 4:0 Selector These 5 bits are hardwired to 00001b, Field indicating that the PHY841F supports IEEE 802.3 CSMA/CD. 4.3.6 Auto Negotiation Link Partner Ability (Register 5h) Bit # Name Description 15 NPAGE Next Page 1: Capable of next page function 0: Not capable of next page function ...
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... ADM7008 Bit # Name Description 0: Not capable of 10M operation 4:0 Selector Encoding Definitions. Field 4.3.7 Auto Negotiation Expansion Register (Register 6h) Bit # Name Description 15:5 Reserved Not Applicable 4 PFAULT Parallel Detection Fault 1: Fault has been detected 0: No Fault Detect 3 LPNPABL Link Partner Next Page Able ...
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... ADM7008 Bit # Name Description Function. 1: Disable. Medium_On is high all the time. 4.3.10 PHY 10M Module Configuration Register (Register 11h) Bit # Name Description 15:6 Reserved Not Applicable 5 DRV62MA Reduce 10M Driver to 62mA. 1: 62mA 0: Normal 4 APDIS Auto Polarity Disable 1: Auto Polarity Function Disabled ...
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... ADM7008 Bit # Name Description 6:5 Reserved Not Applicable 4 DISSCR Disable Scrambler 1: Disable Scrambler 0: Enable Scrambler When set to fiber mode, this bit will be forced to 1 automatically. Write 0 to this bit in Fiber Mode has no effect. 3 ENFEFI Enable FEFI 1: Enable FEFI 0: Disable FEFI 2 Reserved Not Applicable ...
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... ADM7008 Bit # Name Description 0011: Duplex/Collision 0100: Speed 0101: Link 0110: Transmit Activity 0111: Receive Activity 1000: TX/RX Activity 1001: Link/Receive Activity 1010: Link and TX/RX Activity 1011: 100M False Carrier Error/10M Receive Jabber 1100: 100M Error End of Stream/10M Transmit Jabber ...
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... ADM7008 Bit # Name Description 0: Interrupt Disable 8 SPDCHG Speed Changed Interrupt Enable 1: Interrupt Enable 0: Interrupt Disable 7 DUPCHG Duplex Changed Interrupt Enable 1: Interrupt Enable 0: Interrupt Disable 6 PGRCHG Page Received Interrupt Enable 1: Interrupt Enable 0: Interrupt Disable 5 LNKCHG Link Status Changed Interrupt Enable 1: Interrupt Enable ...
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... ADM7008 Bit # Name Reset mode OR’ed result of PI_SELFX and 17.9 (SELFX) 8 XOVER Cross Over status. 0: MDI mode 1: MDIX mode 7:0 Reserved Not Applicable 4.3.15 PHY Specific Status Register (Register 17h) Bit # Name Description 15:12 Reserved Not Applicable 11 JAB-RX Real Time 10M Receive Jabber Status ...
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... ADM7008 Bit # Name Description 1: Link Up 0: Link Down 3 RECPAU Pause Recommend Value. Only Changed when PHY Reset. This bit is disabled automatically when RECDUP Pause Disable 1: Pause Enable 2 RECDUP Duplex Recommended Value. Only Changed when PHY Reset 1: Full Duplex 0: Half Duplex 1 RECSPD Speed Recommend Value. Only Changed ...
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... ADM7008 Bit # Name Description 6 RMII_SMII RMII_SMII Interface 1: RMII or SMII Interface used 0: Non RMII_SMII Interface 5 Reserved Not Applicable 4:0 PHYA PHY Address 4.3.17 Interrupt Status Register (Register 19h) Bit # Name Description 15:10 Reserved Not Applicable 9 XOVCHG Cross Over mode Changed 1: Cross Over mode Changed ...
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... ADM7008 Bit # Name Description 15:0 ERB[15:0] Error Counter. Includes 1.100M False Carrier 2.100M Symbol Error 3.10M Transmit Jabber 4.10M Receive Jabber 5.Error Start of Stream 6.Error End of Stream 4.3.19 Chip ID Register (Register 1Fh) Bit(s) Name 15:0 CHIPID[15: ADMtek CHIP ID 0] 4.3.20 Per port Interrupt and Revision ID Register (Register 1Eh) ...
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... ADM7008 Chapter 5 Electrical Specification 5.1 DC Characterization 5.1.1 Absolute Maximum Rating Symbol Parameter V 3.3V Power Supply CC33 V 1.8V Power Supply CC18 V Input Voltage IN Vout Output Voltage TSTG Storage Temperature PD Power Dissipation ESD ESD Rating 5.1.2 Recommended Operating Conditions Symbol Parameter Vcc Power Supply ...
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... ADM7008 5.2 AC Characterization 5.2.1 XI/OSCI (Crystal/Oscillator) Timing V IL_XI t_XI_RISE Symbol Description t_XI_PER XI/OSCI Clock Period T_XI_HI XI/OSCI Clock High T_XI_LO XI/OSCI Clock Low T_XI_RISE XI/OSCI Clock Rise Time , V (min) T_XI_FALL XI/OSCI Clock Fall Time , V (max) ADMtek Inc. t_XI_PER t_XI_HI V IH_XI Figure 5-1 Crystal/Oscillator Timing ...
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... ADM7008 5.3 RMII Timing 5.3.1 REFCLK Input Timing (When REFCLK_SEL is set IL_RMII t_IN50_RISE Symbol Description t_IN50_PER REFCLK Clock Period t_IN50_HI REFCLK Clock High t_IN50_LO REFCLK Clock Low t_IN50_RISE REFCLK Clock Rise Time , V (min) t_IN50_FALL REFCLK Clock Fall Time , V (max) ADMtek Inc. ...
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... ADM7008 5.3.2 REFCLK Output Timing (When REFCLK_SEL is set to 0) t_OUT50_RISE Symbol Description t_OUT50_PER REFCLK Clock Period t_OUT50_HI REFCLK Clock High t_OUT50_LO REFCLK Clock Low t_OUT50_RISE REFCLK Clock Rise Time , V (min) t_OUT50_FALL REFCLK Clock Fall Time , V (max) t_OUT50_JIT REFCLK Clock Jittering (p-p) ADMtek Inc ...
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... ADM7008 5.3.3 RMII Transmit Timing REFCLK TXEN TXD PREAM DATA On Medium Symbol Description t_RT_DSETUP TXD to REFCLK Rising Setup Time t_RT_DHOLD TXD to REFCLK Rising Hold Time t_RT_TXE2MH TXEN asserts to data transmit to medium 1 00 t_RT_TXE2MH TXEN asserts to data transmit to medium 1 0 t_RT_TXE2ML TXEN de-asserts to finish transmitting ...
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... ADM7008 5.3.4 RMII Receive Timing REFCLK NON_IDLE t_RR_MH2CSH (Internal) CRSDV t_RR_CSH2DAT RXD Symbol Description t_RR_MH2CSH Signal Detected on Medium to CRSDV High 1 00 t_RR_MH2CSH Signal Detected on Medium to CRSDV High 1 0 t_RR_ML2CSL IDLE Detected on Medium to CRSDV low 10 0 t_RR_ML2CSL IDLE Detected on Medium to CRSDV low ...
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... ADM7008 5.4 SMII Clock Timing 5.4.1 REFCLK Input Timing (When REFCLK_SEL is set Also apply to TX_CLK REFCLK Symbol Description t_IN125_PER REFCLK/TXCLK Clock Period t_IN125_HI REFCLK/TXCLK Clock High t_IN125_LO REFCLK/TXCLK Clock Low t_IN125_RISE REFCLK/TXCLK Clock Rise Time , t_IN125_FALL REFCLK/TXCLK Clock Fall Time , ADMtek Inc. ...
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... ADM7008 5.4.2 REFCLK Output Timing (When REFCLK_SEL is set to 1) Also apply to RXCLK in SS_SMII Mode REFCLK t_OUT125_RISE Symbol Description t_OUT125_PER REFCLK Clock Period t_OUT125_HI REFCLK Clock High t_OUT125_LO REFCLK Clock Low t_OUT125_RISE REFCLK Clock Rise Time , V (min) t_OUT125_FAL REFCLK Clock Fall Time , V ...
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... ADM7008 5.4.3 SMII/SS_SMII Transmit Timing TXCLK SYNC (SMII) TX_SYNC (SSMII) TXD Transmit To Medium Symbol Description t_ST_DSETUP TXD to REFCLK Rising Setup Time t_ST_DHOLD TXD to REFCLK Rising Hold Time t_ST_TXE2MH TXEN asserts to data transmit to medium 10 (100M) 0 t_ST_TXE2MH TXEN asserts to data transmit to medium 10 (10M) ...
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... ADM7008 5.4.4 SMII/SS_SMII Receive Timing TXCLK (SMII) RXCLK(SS_SMII) NON_IDLE (Internal) SYNC (SMII) RX_SYNC (SS_SMII) RXD Symbol Description t_SR_MH2CSH Signal Detected on Medium to CRS High 10 (100M) 0 t_SR_MH2CSH Signal Detected on Medium to CRS High 10 (10M) t_SR_ML2CSL IDLE Detected on Medium to CRS low (100M t_SR_ML2CSL IDLE Detected on Medium to CRS low (10M) ...
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... ADM7008 5.5 Serial Management Interface (MDC/MDIO) Timing MDC MDIO(Output) MDC MDIO(Input) Figure 5-10 Serial Management Interface (MDC/MDIO) Timing Symbol Description t_MDC_PER MDC Period t_MDC_HI MDC High t_MDC_LO MDC High t_MDIO_DLY MDC to MDIO Delay Time t_MDIO_SETUP MDIO Input to MDC Setup Time t_MDIO_HOLD MDIO Input to MDC Hold Time Table 5-13 Serial Management Interface (MDC/MDIO) Timing ADMtek Inc ...
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... ADM7008 5.6 Power On Configuration Timing VCC3.3 VCC1.8 RST_N REFCLK PWR ON LATCH Symbol Description t_V33_V18 3.3V Power Good to 1.8V Power Good t_V18_RST Hardware Reset With Device Powered up t_RST_PW Hardware Reset With Clock Running t_PL_DSETUP Reset High to Configuration Setup Time t_PL_DHOLD Reset High to Configuration Hold Time ADMtek Inc ...
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... ADM7008 Chapter 6 Packaging ADMtek Inc. 17.2 +/- 0.2 mm 14.0 +/- 0.1 mm 12.5 mm 0.5 mm Packaging 6-1 ...