CY7C1351B Cypress Semiconductor Corporation., CY7C1351B Datasheet
CY7C1351B
Specifications of CY7C1351B
Available stocks
Related parts for CY7C1351B
CY7C1351B Summary of contents
Page 1
... The CY7C1351B is a 3.3V, 128K by 36 Synchronous Flow-Through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1351B is equipped with the advanced No Bus Latency™ (NoBL™) logic required to en- able consecutive Read/Write operations with data being trans- ferred on every clock cycle ...
Page 2
... Pin Configuration DDQ DDQ DDQ DDQ Document #: 38-05208 Rev. ** PRELIMINARY 100-Pin TQFP CY7C1351B CY7C1351B DDQ DDQ DDQ DDQ Page ...
Page 3
... Pin Configuration Document #: 38-05208 Rev. ** PRELIMINARY 119-Ball Bump BGA CY7C1351B (128K x 36 BGA 16M DDQ ADV/ DDQ BWS DDQ DD SS( CLK BWS CEN DDQ MODE 64M TMS TDI TCK DDQ CY7C1351B DDQ DDQ BWS SS(1) DD DDQ BWS DDQ 32M NC TDO DNU ...
Page 4
... The direction of the pins is [16:0] are placed in a three-state condition. The outputs are auto- [31:0] is controlled by BWS 0 , and DP is controlled by BWS . CY7C1351B controls DQ and DP , BWS controls DQ 0 [7: BWS controls DQ and ...
Page 5
... Burst Read Accesses The CY7C1351B has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four Reads without reasserting the address inputs. ADV/LD must be driven LOW in order to load a new address into the SRAM, as described in the Single Read Access section above ...
Page 6
... Valid Valid CY7C1351B CLK Comments x X L-H I/Os three-state following next recognized clock. X L-H Clock ignored, all operations suspended. X L-H Address latched. L-H Address latched, data presented two valid clocks later. X L-H Burst Read operation. Previous ac- cess was a Read operation. Ad- dresses incremented internally in conjunction with the state of MODE ...
Page 7
... Write Bytes 3, 0 Write Bytes 3, 1 Write Bytes Write Bytes 3, 2 Write Bytes Write Bytes Write All Bytes Document #: 38-05208 Rev. ** PRELIMINARY Linear Burst Sequence Fourth First Address Address Ax+1, Ax Ax+ BWS CY7C1351B Second Third Address Address Ax+1, Ax Ax+1, Ax Ax+ BWS BWS Page ...
Page 8
... Max Device Deselected, or 8.5-ns cycle, 117 MHz –0. DDQ 10-ns cycle, 100 MHz = 1 MAX CYC 15-ns cycle, 66 MHz 20-ns cycle, 50 MHz 25-ns cycle, 40 MHz CY7C1351B Ambient [8] Temperature DDQ 0°C to 70°C 3.3V 5% Min. Max. Unit 3.135 3.465 3.135 3.465 2.4 ...
Page 9
... Tested initially and after any design or process change that may affect these parameters. Document #: 38-05208 Rev. ** PRELIMINARY Test Conditions MHz 3. 3.3V DDQ R=317 3.3V OUTPUT 5 pF R=351 INCLUDING JIG AND SCOPE (b) Test Conditions CY7C1351B Max ALL INPUT PULSES 3.0V GND Symbol TQFP Typ. Units 28 C C/W JC Unit Notes 10 ...
Page 10
... SRAMs when sharing the same EOLZ CHZ CLZ , and t are specified with AC test conditions shown in part ( Test Loads. CHZ CLZ OEV EOLZ EOHZ CY7C1351B -66 -50 - 5.0 6.0 7.0 5.0 6.0 7.0 11.0 12 ...
Page 11
... Document #: 38-05208 Rev. ** PRELIMINARY CYC WA5 RA3 RA4 t DOH t CHZ Out In Out to define a write cycle (see Write Cycle Description table and CE . All chip selects need to be active in order to select DON’T CARE = UNDEFINED CY7C1351B t t CENH CENS RA6 RA7 t CHZ Out In Out Page ...
Page 12
... Q1+2 Q1+3 D2 Out Out In Out t DS defines a write cycle (see Write Cycle Description table). [3:0] , and CE . All chip enables need to be active in order to select DON’T CARE = UNDEFINED CY7C1351B RA3 t CLZ Q3 D2+2 D2+3 D2+1 Out input signals. [3:0] Page Q3+1 Out ...
Page 13
... Speed (MHz) Ordering Code 117 CY7C1351B-117AC 100 CY7C1351B-100AC 66 CY7C1351B-66AC 50 CY7C1351B-50AC 40 CY7C1351B-40AC 117 CY7C1351B-117BGC 100 CY7C1351B-100BGC 66 CY7C1351B-66BGC 50 CY7C1351B-50BGC 40 CY7C1351B-40BGC Document #: 38-05208 Rev. ** PRELIMINARY OE t EOHZ Three-state I/Os t EOLZ Package Name A101 100-Lead 1.4 mm Thin Quad Flat Pack 100-Lead 1.4 mm Thin Quad Flat Pack 100-Lead ...
Page 14
... Package Diagrams 100-Pin Thin Plastic Quad Flatpack ( 1.4 mm) A101 Document #: 38-05208 Rev. ** PRELIMINARY CY7C1351B 51-85050-*A Page ...
Page 15
... The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. PRELIMINARY 119-Lead BGA ( 2.4) BG119 CY7C1351B 51-85115-*A Page ...
Page 16
... Document Title: CY7C1351B 128K x 36 Flow-Through SRAM with NoBL™ Architecture Document Number: 38-05208 Issue REV. ECN NO. Date ** 115440 05/06/02 Document #: 38-05208 Rev. ** PRELIMINARY Orig. of Change DSG Change from Spec number: 38-00691 to 38-05208 CY7C1351B Description of Change Page ...