HDMP-1034 Agilent Technologies, Inc., HDMP-1034 Datasheet
HDMP-1034
Specifications of HDMP-1034
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HDMP-1034 Summary of contents
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... GBd Transmitter/Receiver Chip Set with CIMT Encoder/Decoder and Variable Data Rate. Description The HDMP-1032 transmitter and HDMP-1034 receiver are used together to build a high-speed data link for point-to-point communication. These silicon bipolar transmitter and receiver chips are housed in standard plastic 64 pin PQFP packages. ...
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... Tx Operation Principles – Encoding & Phase Lock Loop .................................... 24 Rx Operation Principles – Decoding & Phase Lock Loop.................................... 25 Integrator Capacitor & Power Supply Bypassing/Grounding ................................................................................................. 26 TTL and High Speed I/O ............................................................................................. 26 Data Bus Line/Broadcast Transmission ................................................................. 27 Nomenclature Changes between HDMP-1032/34 and HDMP-1022/24 .......................................................................... 30 Pin Cross Reference Table ........................................................................................ 31 Page ...
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... TXCLK C) 32 BIT SIMPLEX TRANSMISSION Tx Rx TXCLK Tx Rx TXCLK D) 32 BIT SIMPLEX TRANSMISSION Tx Rx TXCLK Rx Tx RXCLK0/1 REFCLK E) 16 BIT DUPLEX TRANSMISSION Figure 1. Various configurations using the HDMP-1032/1034 RXCLK0/1 REFCLK RXCLK0/1 REFCLK RXCLK0/1 REFCLK RXCLK0/1 REFCLK Rx DEMUX RXCLK0/1 REFCLK RXCLK0/1 REFCLK ...
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... According to the table only a setting of DIV1/0 = (0/0) allows a parallel input word rate MHz. This range setting easily accommodates the required 60 MHz word rate and HDMP-1032 (Tx), HDMP-1034 (Rx) 1,2 Typical Operating Rates Tc = – + 3.15V to 3.45V CC Parallel Word Rate ...
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... TXFLAG ENCODER TXDATA TXCNTL SIGN W-FIELD TX[0-15] ENCODER Figure 3. HDMP-1032 Transmitter Block Diagram setting TCLKENB high, the user may provide an external TTL high speed serial clock at TXCLK. This clock replaces the internal VCO clock and is in- tended for diagnostic purposes only. This uncharacterized signal ...
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... HDMP-1032 RXCAP1/0 + HSIN CDR REFCLK CLOCK GENERATOR RXCLK0/1 Figure 4. HDMP-1034 Receiver Block Diagram. 6 into either bit wide parallel data. The HDMP-1034 performs the following functions: • Frequency Lock • Phase Lock • Encoded Word Synchronization • De-multiplexing • ...
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Demultiplexer (DEMUX) This block takes the recovered serial data from the CDR block and demultiplexes it into a 20-bit parallel word comprised of a 16-bit word-field and 4-bit code-field. Decoder (DECODE) This block decodes the 4-bit code-field and determines whether ...
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REFCLK. By adjusting the phase of the data word rather than REFCLK, the optimal setup time is achieved for the input latches of the chip interfacing to the Rx. As the relative phase between the HSIN input and ...
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Multiple Channel Configuration The connections for a multiple channel configuration are shown in Figure 4.3. The daisy-chain signals SRQIN and SRQOUT are used to allow each receiver’s PASS system shift requests to propagate to the master, which is the last ...
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... TXFLAG Relative to Rising Edge of TXCLK. TXCLK TX[0-15] TXDATA TXCNTL TXFLAG t s HSOUT Figure 5. HDMP-1032 (Tx) Timing Diagram. 10 The setup and hold time param- eters, t and t , are referenced the rising edge of TXCLK. The start of a word, bit TX[0], in the high speed serial output ...
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... PASS system resets, PASSENB=1. WORD 1 W BIT 0 HSIN RXCLK1 RXCLK0 REFCLK Figure 6. HDMP-1034 (Rx) Timing Diagram. 11 RXDATA, RXCNTL and RXDSLIP are clocked out with the falling edge of RXCLK1 and appear after a delay RXCLK1 and its d complement RXCLK0 are both 50% duty cycle clocks. ...
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... HDMP-1032 (Tx), HDMP-1034 (Rx) DC Electrical Specifications Tc = – + 3.15V to 3.45V, Typical values are Symbol Parameter V TTL Input High Voltage Level, Guaranteed high signal IH,TTL for all inputs. V TTL Input Low Voltage Level, Guaranteed low signal IL,TTL for all inputs. V TTL Output High Voltage Level, I ...
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... Tc = – Symbol Parameter F TXCLK and REFCLK Frequency Tolerance tol (REFCLK is referenced to TXCLK) Symm Symmetry (Duty Cycle) HDMP-1032 (Tx), HDMP-1034 (Rx) Absolute Maximum Ratings except as specified. Operation in excess of any one of these conditions may result in permanent damage to A the device. Symbol Parameter V Supply Voltage CC ...
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... P ), where T is the case temperature measured on the top center of the package and 3 3 loads. All unused outputs resistor to ground. for the HDMP-1032 and HDMP-1034 is 50 C/W. jc Unit Typ. C 590 Unit Typ. C 660 is measured on a standard jc is the power being dissipated. ...
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... Figure 7. HDMP-1032 (Tx) Package Layout, Top View. GND_TTL 1 RX[1] 2 RX[0] 3 RXREADY 4 RXERROR 5 RXDSLIP 6 V _TTL 7 CC GND_TTL GND 10 REFCLK 11 TSTCLK 12 SHFIN 13 SHFOUT 14 SRQOUT 15 V _HS 16 CC Figure 8. HDMP-1034 (Rx) Package Layout, Top View GND 47 TX[1] 46 TX[ HDMP-1032 41 V LOT GND_TTL 39 NC DATE CODE TXCLK GND TXCAP1 ...
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... Bit encoding. The ESMPXENB pin on the Rx chip must be set to the same value. This mode should be enabled unless compatibility with previous versions of G-Link (i.e. HDMP-1024/1014) is desired desired which don’t have this feature. Transmit Data Word: This input tells the chip that the user has valid data to be transmitted ...
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... HDMP-1032 (Tx) Pin Definition (continued) PLL/Clock Generator Name Pin Type TXCAP0 32 C TXCAP1 33 TXCLK 37 I-TTL TXDIV0 26 I-TTL TXDIV1 27 LOCKED 12 O-TTL Power Supply/Ground _TTL _HS _A1 _A2 57 CC GND GND_TTL GND_HS 18 S GND_A1 30 S GND_A2 56 Test Mode/No Connect Pins TCLKENB 28 I-TTL Signal Loop Filter Capacitor: A 0.1 F min. loop filter capacitor, C2, must be connected across TXCAP0 and TXCAP1 for all combinations of TXDIV1/TXDIV0 ...
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... HDMP-1034 (Rx) Pin Definition User Mode Options/Status Name Pin Type RXFLGENB 22 I-TTL ESMPXENB 23 I-TTL PASSENB 26 I-TTL RXDATA 44 O-TTL RXCNTL 43 O-TTL High-Speed Serial/Parallel I/O HSIN+ 18 HS_IN HSIN- 19 RX[0] 3 O-TTL RX[1] 2 RX[2] 63 RX[3] 62 RX[4] 61 RX[5] 60 RX[6] 59 RX[7] 58 RX[8] 55 RX[9] 54 RX[10] 53 RX[11] 52 RX[12] 51 RX[13] 50 RX[14] ...
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... HDMP-1034 (Rx) Pin Definition (continued) CDR/Clock Generator Name Pin Type RXCAP0 32 C RXCAP1 33 REFCLK 11 I-TTL RXDIV0 28 I-TTL RXDIV1 29 RXCLK0 37 O-TTL RXCLK1 38 Power Supply/Ground _TTL _HS GND GND_TTL GND_HS GND_A Signal Loop Filter Capacitor: A 0.1 F min. loop filter capacitor, C2, must be connected across RXCAP0 and RXCAP1 for all combinations of RXDIV1/RXDIV0 ...
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... HDMP-1034 (Rx) Pin Definition (continued) Pass System RXDSLIP 6 O-TTL SHFIN 13 I-TTL SHFOUT 14 O-TTL SRQIN 34 I-TTL SRQOUT 15 O-TTL Test Mode/No Connect Pins TSTCLK 12 I-TTL #RESET 35 I-TTL WSYNCDSB 36 I-TTL Word Slip: This output is asserted whenever the phase of the parallel word relative to the reference clock has exceeded the range of the internal delay, which results in a slippage of one word ...
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... Package Material Lead Finish Material Lead Finish Thickness Lead Skew Lead Coplanarity (seating plane method) Mechanical Dimensions PIN # HDMP-103x 8 TOP VIEW Mechanical Dimensions of HDMP-1032/34 Dimensional Parameter D1/E1 (in millmeters) HDMP-103X 14.00 Tolerance 0.10 21 Details Plastic 85% Tin, 15% Lead 300–800 m 0.20 mm max 0.10 mm max ...
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... FIELD 16 BITS SERIAL BIT STREAM IDLE WORD WORD K Figure 9. HDMP-1032/1034 (Tx/Rx Pair) Line Code. 22 page. Note that the leftmost bit in each table is the first bit to be transmitted in time, while the rightmost bit is the last bit to be transmitted. Data Word Codes In Data Word mode, all 16 bits of the Tx are transmitted to the Rx, along with a flag bit ...
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... Coding with ESMPXENB=0 (Compatible with previous G-Link chips, HDMP-1012/14, HDMP-1022/24) Word Type Flag W-Field w10 w11 w12 w13 w14 w15 Data Word Structure Data = True X10 X11 X12 X13 X14 X15 1 Data = Inverted 0 #( X10 x11 X12 X13 X14 X15) 0 Data = True ...
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... TXCLK FREQUENCY DETECTOR INTERNAL CLOCKS CLOCK GENERATOR LOCK DETECT Figure 10. HDMP-1032 (Tx) Phase-Lock Loop. 24 all the internal clock signals required by the Tx chip. The data inputs, TX[0-15], as well as the control signals; TXDATA, TXCNTL and TXFLAG are latched in on the rising edge of an internally generated word rate clock ...
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... PHASE DETECTOR 1 INTERNAL CLOCKS 0 FREQUENCY DETECTOR REFCLK LOCK Figure 11. HDMP-1034 (Rx) Phase-Lock Loop. 25 • Word Decoding • Error Detection • Automatic Parallel Word Phase Adjustment Rx Data Path Figure 4 shows a simplified block diagram of the receiver. The data path consists of an Input Sampler, a Word Demultiplexer, a Coding Field (C-Field) Decoder, and a Word Field (W-Field) Decoder ...
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... HDMP-1032 BYPASS CAPACITOR C2 = PLL INTEGRATOR CAPACITOR NOTE PINS SUPPLY VOLTAGE SHOULD CC COME FROM A LOW NOISE SOURCE. Figure 12. HDMP-1032 (Tx) and HDMP-1034 (Rx) Power Supply Pins result, all of the separate power supplies ( _TTL, and _HS) can be connected onto CC this plane. The bypassing ground should be done with a ...
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For opti- mum performance, both outputs should see the same impedance necessary that all HS_OUT outputs be terminated into 50 . Figure 15 shows various methods of interfacing HS_OUT to ...
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... HSIN– 0.1 µ GENERIC PECL OUTPUT TO G-LINK Rx INPUT +5 V 0.1 µF 68 0.1 µF 50 HSOUT+ HSOUT– 50 0.1 µF 191 0.1 µF 50 HSIN+ HSIN– 50 0.1 µF 270 D) G-LINK INTERFACE TO OPTICAL TRANSCEIVER Rx HDMP-1034 OPTICAL TRANSCEIVER 68 (+5 V) TD+ TD– 191 RD+ RD– 270 ...
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... Figure 16. Data Bus Line Transmission HDMP-1034 HDMP-1034 Figure 17. Broadcast Transmission using a HDMP-0450 Port-Bypass Circuit Zstub 0.1 µF 0.1 µF 0.1 µ –5 V –5 V – HDMP-1034 OR HIGHER, AND NO LONGER THAN 2. INCH HDMP-1034 HDMP-1034 Zstub 0.1 µF 0.1 µ –5 V – HDMP-1034 HDMP-1034 HDMP-1032 HDMP-0450 100 ...
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... In addition with the HDMP-1032/ 34, fill frames have been changed to idle words following the custom used in Fibre Channel and Giga- bit Ethernet where idles are in- ...
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... D10 61 D11 62 D12 63 D13 64 HDMP-1034 (Rx) HDMP-1024 (Rx) Name Name GND_TTL RX[1] D1 RX[0] D0 RXREADY LINKRDY* RXERROR ERROR RXDSLIP VCC_TTL GND_TTL VCC GND REFCLK TSTCLK TCLK SHFIN SHFOUT SRQOUT VCC_HS GND_HS HSIN+ DIN HSIN- DIN* GND_HS NC RXFLGENB FLAGSEL ESMPXENB VCC GND PASSENB NC TCLKSEL RXDIV0 ...
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... Data subject to change. Copyright © 2000 Agilent Technologies, Inc. 5968-5909E (2/00) ...