PEB2084 Siemens Semiconductor Group, PEB2084 Datasheet

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PEB2084

Manufacturer Part Number
PEB2084
Description
ICs for Communications Extended PCM Interface Controller PEB2084Quadruple Transceiver for S/T Interface QUAT-S
Manufacturer
Siemens Semiconductor Group
Datasheet

Specifications of PEB2084

Case
QFP

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ICs for Communications
Quadruple Transceiver for S/T Interface
QUAT-S
PEB 2084 Version 1.2
Data Sheet 07.95
T2084-V12-D1-7600

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PEB2084 Summary of contents

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ICs for Communications Quadruple Transceiver for S/T Interface QUAT-S PEB 2084 Version 1.2 Data Sheet 07.95 T2084-V12-D1-7600 ...

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Ausgabe 07.95 Herausgegeben von Siemens AG, Bereich Halbleiter, Marketing- Kommunikation, Balanstraße 73, 81541 München © Siemens AG 1995. Alle Rechte vorbehalten. Wichtige Hinweise! Gewähr für die Freiheit von Rechten Dritter leisten wir nur für Bauelemente selbst, nicht für Anwendungen, Verfahren ...

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PEB 2084 Revision History: Previous Releases: Page Page (in previous (in current Version) Version Current Version: Data Sheet 07.95 Preliminary Technical Manual 2.94 Subjects (major changes ...

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Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Table of Contents 5 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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Overview The PEB 2084, Quadruple Transceiver for S/T Interfaces (QUAT-S), implements four- wire S/T interfaces used to link voice/data digital terminals to PBX subscriber lines and PBX trunk lines to the public ISDN. The QUAT optimized device ...

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SLIC 16 x t/r r SLIC Example for an Integrated Analog / Digital PBX Application Semiconductor Group ...

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Quadruple Transceiver for S/T Interface (QUAT-S) 1.1 Features • Four full duplex ( S/T interface transceivers, each equipped with the following functions: – Analog S/T interfaces fully according to the CCITT I.430, ETSI 300.012 and ANSI ...

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Logic Symbol Figure 1 QUAT-S Logic Symbol Semiconductor Group 9 PEB 2084 ...

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Pin Configuration (top view) Semiconductor Group P-MQFP-44-2 10 PEB 2084 ...

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Pin Description Pin No. Symbol Input (I) Output (O) 29, 30 SR0a,b I 32, 33 SX0a,b O 27, 26 SR1a,b I 24, 23 SX1a SR2a SX2a SR3a,b I 10, 11 ...

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Pin Description (cont’d) Pin No. Symbol Input (I) Output (O) 36 CLK1/ O/I IDS 35 CLK2 O 38 RST I 17 CEB / I/O / SSYNC I 18 DRDY 22, 28, 34, 44 ...

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Functional Description The PEB 2084, QUAT-S, performs the layer-1 functions of the ISDN basic access for four S/T interfaces. 2.1 Device Architecture The QUAT-S contains the following functional blocks: Refer to figure 2 • Four line transceivers with analog ...

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Interfaces PEB 2084, QUAT-S, provides four independent S/T interfaces, one IOM-2 interface and one JTAG boundary scan test interface. 2.2.1 S/T Interface Frame Structure One frame consists of 48 bits nominal bit rate of 192 kbit/s. Thus ...

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Coding The QUAT-S uses a pseudo-ternary coding technique on the S/T interface (with a 100% pulse width) according to CCITT I.430 recommendation. A binary ‘1’ corresponds to a neutral level (space = no current) on the S/T line, binary ‘0’s ...

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Interface Configurations The QUAT-S provides four S/T interfaces for different applications, see figure 5: • Subscriber’s connection to PBX (LT-S Mode) for different line configurations: – Point-to-point – Short passive bus – Extended passive bus • PBX connection to CO ...

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IOM ® -2 System Interface The PEB 2084, QUAT-S, is equipped with a digital ISDN Oriented Modular (IOM-2) interface, for interconnection with other telecommunication ICs, such as IDEC (PEB 2075), EPIC (PEB 2055) and ELIC (PEB 20550). EPIC and ...

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Thus, depending on the programmable QUAT-S mode, the data lines IDI and IDO get different meanings: IDI IDO (IOM-2 interface Data Output) = Data Upstream The data is clocked by Data Clock (DCL) that operates at single or double data ...

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FSC DCL R IOM CH0 CH1 DU R IOM DD CH0 CH1 B1 Figure 7 Multiplexed Frame Structure of the IOM-2 Interface in LT Mode with 2048 kbit/s Data Rate Each IOM ISDN channel consists of a total of 32 ...

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The monitor channel operates on an asynchronous basis. While data transfer on the bus takes place synchronized to the frame, the data flow is controlled by a handshake procedure using the monitor channel receive bit (MR) and the monitor channel ...

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JTAG Boundary Scan Test Interface The QUAT-S provides a boundary scan support for a cost effective board testing. It consists of: – Complete boundary scan for 11 signals (pins) according to IEEE Std. 1149.1 specification – Test access port ...

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TAP Controller The Test Access Port (TAP) controller implements the state machine defined in the JTAG standard IEEE Std. 1149.1. Transitions on the pin TMS cause the TAP controller to perform a state change. Following the standard definition five instructions ...

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IDCODE Register The 32-bit identification register is serially read out via TDO. It contains the version number (4 bits), the device code (16 bits) and the manufacture code (11 bits). The LSB is fixed to “1”. Version Device Code 0001 ...

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Individual Functions 2.3.1 Transceiver, Analog Connections The receiver input stages consist of a differential amplifier, followed by a peak detector and a set of comparators. Additional noise immunity is achieved by digital oversampling after the comparators, meaning that the ...

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Figure 10 Transmitter Functional Block External transformers of the ratio 2:1 are needed in receive and transmit directions to provide for isolation and transform voltage levels according to CCITT recommendations I.430. The QUAT-S also needs external circuitry for impedance ...

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Note: The actual values of the external resistors depend on the selected transformer. The resistor values are optimal for an ideal transformer ( R Line termination ( R The transmitter of the QUAT-S is identical to that of SBCX, hence ...

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In the receive direction two cases have to be distinguished depending on the bus configuration: – Short passive bus configuration (Configuration Register: C The 192 kHz receive bit clock is identical to the transmit bit clock. The sampling ...

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SR2 SR1 TR1 TR2 Figure 13 Receive Signal Oversampling on S and T Interfaces The PLL also provides a synchronous 1.536 MHz clock (adaptive timing ...

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Since the ELIC generates the IOM-2 clocks (FSC, DCL) for all connected layer-1 and layer-2 devices, the loop is closed. If several layer-1 devices are operated in LT-T mode, only one device (one channel in a QUAT-S) may be selected ...

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Multi-Frame Generation with a short FSC The QUAT-S synchronizes to a multi-frame structure according to CCITT recommendation I.430. In LT-S application mode the S interface multi-frame (20 generated by a master device (e.g. ELIC) by inserting a short FSC ...

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Super-Frame (M-bit) Generation using SSYNC (for DECT) A zero pulse on the SSYNC input pin forces the QUAT-S to send synchronously on all four S/T interfaces. (Useful with MFD = 1 only.) Figure 16 M-bit Generation ...

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Operational Description All procedures required for data transmission over the S/T interface are implemented. These comprise the activation/deactivation procedure, and timing requirements such as bit rate and jitter. For a correct functionality of the QUAT-S the following operational precautions ...

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Monitor Channel Before starting a data transmission to the QUAT-S, a microprocessor must verify that the transmitter of the QUAT-S is inactive, i.e. that a previous transmission has been terminated. The QUAT-S has a monitor transmitter time out function ...

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Figure 17 Monitor Channel Handling detailed description of the hand-shake procedure using MX and MR bits is shown in figure 18. Semiconductor Group ELIC QUAT-S 34 PEB 2084 ...

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Figure 18 Monitor Channel Handling: Hand-shake by the Use of MX and MR Bits (LT-S Mode) QUAT-S in LT-S Mode QUAT-S in LT-T Mode Semiconductor Group Data Downstream: MX-bit at ELIC Data Upstream: MX-bit at QUAT-S Data Downstream: MX-bit at ...

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D-Channel Handling Decentral D-channel handling in a PBX depends on QUAT-S application mode: LT-S or LT-T. LT-S Mode. Configuration Register, MODE = used in PBX applications with only one signalling controller (HDLC) used for up to ...

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The codes (C/I = 1100 H G3 activated (during INFO 4 transmission). Refer to chapter 3.6. For a detailed description of the D-Channel Arbiter refer to “ELIC, PEB 20550, Technical Manual 9.93”, page 54, chapter 2.2.8. D-Channel Access According to ...

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The ELIC D-channel arbiter doesn’t work in this application as an arbiter (all channels are permanently sent the C/I command “available” = 1000 D-channel on the IOM interface and controls the connected LABD controller (SACCO A). - LT-T Mode Configuration ...

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Single-Channel LT-T Applications QUAT-S can also be used in a mixed mode, e.g. by programming three channels in LT mode and one channel in LT-T mode. The Auxiliary Register of only one channel can be programmed to DCM(1: ...

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Clock generation for the above application is shown in figure 14. 3.3.4 Command/Indicate Channel The exchange of control information in the C/I channel is state oriented. This means that a code in the C/I channel is repeated in every IOM ...

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LT-S Mode Command / Indication Codes Commands (downstream) LT-S mode Deactivate request Reset Test mode 1 Test mode 2 Activate request Activate indication Activate request loop Deactivate confirmation (x) unconditional commands Indications (upstream) LT-S mode Timing Resynchronizing Activate request ...

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Figure 23 QUAT-S State Diagram of LT-S Mode Note: 1) ARD stands for AR or ARL 2) only if DCM (1: Semiconductor Group 42 PEB 2084 ...

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Figure 24 QUAT-S State Diagram in the LT-T Mode, Conditional States Note: 1) TM1 and TM2 and RES and ARL 2) Al stand for AI8 or Al10 TMI stands for AR8 or AR10 p 4) TMI stands ...

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LT-S Mode States • G1 deactivated The line interface is not transmitting. There is no signal detected on the S interface, and no activation command is received in the C/I channel. • G2 pending activation As a result of an ...

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LT-T Mode Command / Indication Codes, Conditional States Commands (upstream) LT-T Mode Timing Reset Test mode 1 Test mode 2 Activate request, priority 8 Activate request, priority 10 AR10 Active request loop Deactivate indication (x) unconditional commands Semiconductor Group ...

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Indications (downstream) LT-T Mode Deactivate request Reset Test mode 1 Test mode 2 Slip detected Resynchronization during level detect Power up Activate request Activate request loop Code violation received Activate indication loop Activate indication with priority class 8 Activate indication ...

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Figure 25 QUAT-S State Diagram in the LT-T Mode, Unconditional States (Transitions) Note state loop 3 activated the internal signal, the external signal is i0. Semiconductor Group 47 PEB 2084 ...

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LT-T Mode, Conditional States • F3 power down This is the deactivated state of the physical protocol. The receive line awake unit is active. • F3 power up This state is similar to “F3 power down”. The state is invoked ...

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LT-T Mode, Unconditional States The unconditional states should be left with the command TIM. • Loop 3 closed On Activate Request Loop command, INFO 3 is sent by the line transmitter internally to the line receiver (INFO 0 is transmitted ...

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Example of Activation/Deactivation An activation and deactivation procedure between a QUAT-S and an ISAC-S or SBCX in TE mode over the S/T interface line is shown in figure 26. It illustrates how the state machines of the respective modes ...

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Diagnostic Functions, Test Loop-backs Different test loops for B1, B2 and D-channels can be closed in the QUAT-S: – Transparent analog loops (the data are also sent forward). – Non transparent analog loops (the forward data path is blocked). ...

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S and Q Channel Access According to CCITT recommendation I.430 a multi-frame (= 20 consecutive S/T frames) provides an additional communication channel between TE and and CO via S and Q bits. Refer to figure 28. ...

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All other S and Q bit positions within the remaining 12 frames of the multi-frame carry the value ZERO. The S and Q bits are accessed by the ELIC or EPIC via IOM-2 interface monitor channel. The bits are handled ...

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Registers Description As the QUAT-S contains four PEB 2081, SBCX, cores, it contains four complete register sets. All registers programming is done via the four IOM monitor channels. Access to the registers of the QUAT-S are treated as local ...

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Configuration Register Read/Write, Address bit 7 Format: MFD RCLK Initial value Bit-name Description MFD Multi-Frame Disable (write): 0: All multi-frame functions active. 1: Multi-frame generation (LT-S) or synchronization (LT-T) prohibited monitor messages released. ...

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Bit-name Description RCVE Receive Code Violation Indication (C/I) Enable 0: Normal operation 1: A code violation detector is implemented to support the Far-end-code-violation (FECV) function according to ANSI T1.605. After each multi-frame the receipt of at least one illegal code ...

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Auxiliary Register Read/Write, Address bit 7 Format: CI3 Initial value: CI(3:0 Bit-name Description CI(3:0) C/I codes as in C/I channel The indication can be read via monitor channel CI (3:0). TOD Time-Out Disable 0: Monitor ...

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Other Registers Other registers are implemented at address locations 3 monitor addresses may cause unexpected behavior of the device. Semiconductor Group , 5 , and PEB 2084 . Access to those H ...

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Electrical Characteristics All characteristics given are valid under the following conditions unless otherwise indicated 5.1 Absolute Maximum Ratings Parameter Ambient temperature under bias Storage temperature Voltage on ...

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Line Overload Protection The maximum input current (under overvoltage conditions) is given as a function of the width of a rectangular input current pulse. For the destruction current limits refer to figure 29. 5000 mA 500 50 5 Figure 29 ...

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DC Characteristics Pin Parameter All pins Input voltage except Input high voltage SXna,b; SRna,b Output low voltage XTAL1, 2 DRDY, Output low voltage IDO All pins Output high voltage except SXna,b; SRna,b; Input leakage current XTAL1, 2 Output leakage ...

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DC Characteristics (cont’d) Pin Parameter Power supply current 5.3 Capacitances Pin All pins except SXn a, b SXn a, b XTAL1, 2 Semiconductor Group Symbol Limit Values Unit ...

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Recommended Oscillator Circuits Crystal nominal frequency: 7.68 MHz Figure 30 Recommended Oscillator Circuits 5.5 AC Characteristics testing: Set-up, Hold, Delays Inputs are driven at Timing measurements ...

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Clocks CLK1 Parameter High phase of clock Low phase of clock Clock period CLK2 Parameter High phase of clock Low phase of clock Clock period CLK2 is directly derived from the oscillator clock and can drive ...

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IOM ® -2 Interface Timing Figure 33 Timing of the IOM ® -2 Interface with Double Data Rate DCL Timing Characteristics of the IOM Parameter Frame sync hold Frame sync setup Frame sync high Frame sync low Data delay ...

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Figure 34 IOM ® -2 Interface Timing with Single Data Rate DCL Timing Characteristics of the IOM Parameter Frame sync. hold Frame sync. setup Frame sync. high Frame sync. low Data delay to clock Data delay to frame 1) Data ...

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Figure 35 SSYNC Timing Parameter Superframe sync. setup Superframe sync. hold Semiconductor Group Symbol Limit Values min. t 200 SSYS t 200 SSYH 67 PEB 2084 Unit max ...

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Timing of Boundary Scan Test Interface Figure 36 Boundary Scan Test Interface Timing Parameter Test clock period Test clock period low Test clock period high TMS setup time to TCK TMS hold time from TCK TDI setup time to ...

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Transceiver Characteristics The transceiver comprises the transmitter output stages, the differential-to-single ended receiver input stage, the loop switch, the peak detector, and the threshold comparators. Figure 37 Transceiver Architecture of one S/T-Channel When transmitting a binary ZERO, the transmitter ...

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Transmitter Performance Cable 0.6 mm, 120 nF/km Configuration Condition Point-to-point no noise 200 / 2000 kHz 100 mVpp Ext. passive bus no noise (Roundtrip < 200 / 2000 kHz 100 mVpp Cable 0.6 mm, 30 nF/km Configuration Condition ...

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Package Outlines Plastic Package, P-MQFP-44-2 (Plastic Metric Quad Flat Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Semiconductor Group 71 PEB 2084 Dimensions in ...

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Appendix List of Transformer Manufacturers and S The following list contains transformers recommended by different manufacturers for use with Siemens S transceivers. 0 Transformers marked with * have been tested in Siemens S evaluation boards and have shown positive ...

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