PEB24902H Infineon Technologies AG, PEB24902H Datasheet
PEB24902H
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PEB24902H Summary of contents
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... Edition 2001-01-23 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 München, Germany © Infineon Technologies AG 2001. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein ...
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PEB 24902 Revision History: Previous Version: Page Subjects (major changes since last revision) 17, 20, 21 Pin ADDR has to be clamped XDNx pins removed from Logic Symbol For questions on technology, delivery and prices please contact ...
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Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 1 Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Tables Table 1 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Overview The PEB 24902 Quad IEC AFE (Quadruple ISDN Echocancellation Circuit Analogue Front End) is part of a 2B1Q or 4B3T ISDN U-transceiver chip set four lines can be accessed simultaneously by the Quad IEC AFE. The ...
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Quad ISDN Echocancellation Circuit Analogue Front End Quad IEC AFE Version 2.1 1.1 Features • Digital to Analogue conversion (transmit pulse) • Output buffering • Analogue to digital conversion • Detection of signal on the line • Master clock generation ...
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Logic Symbol +5V VDD d1...2, a0...3 0V GND d1...2, a0...3 CODE ADDR Mode Settings PLLF RES V REF0 V REF1 V REF2 V REF3 Figure 1 Logic Symbol Data Sheet Analog Line Ports PEB 24902 Boundary Scan Pins 3 ...
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Functional Block Diagram DEE Digital Interface Interface Common PLL Figure 2 Block Diagram of the Quad IEC AFE Data Sheet D Buffer A A Level D D Buffer A A Level D Voltage Reference 4 PEB 24902 PEF 24902 ...
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Pin Configuration GND 49 a2 XDN2 REF2 AIN2 52 BIN2 53 N. TDI TDO 56 TCK 57 TMS ...
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Pin Definitions and Functions The following tables group the pins according to their functions. They include pin name, pin number, type, a brief description of the function and cross-references referring to the sections in which the pin functions are ...
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Table 1 Pin Definitions and Functions (cont’d) Pin No. Symbol Input (I) Output ( REF3 JTAG Boundary Scan 57 TCK I 58 TMS I 55 TDI I 56 TDO O 59 TDISS I Line Port Pins 29 ...
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Table 1 Pin Definitions and Functions (cont’d) Pin No. Symbol Input (I) Output (O) 53 BIN2 I 47 AOUT2 O 44 BOUT2 O 61 AIN3 I 60 BIN3 I 2 AOUT3 O 5 BOUT3 O Digital Interface 7 CL15 I/O ...
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Table 1 Pin Definitions and Functions (cont’d) Pin No. Symbol Input (I) Output (O) 40 PDM2 O 8 PDM3 O 31 XDN0 I 18 XDN1 I 50 XDN2 I 63 XDN3 I 24 SDX I 41 SDR O 27 ADDR ...
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Table 1 Pin Definitions and Functions (cont’d) Pin No. Symbol Input (I) Output (O) 26 CLOCK I 22 PLLF I Data Sheet Description 8 kHz or 2048 kHz clock as a time base of the 15.36 MHz clock.Connect to GND ...
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System Integration The Quad IEC AFE is optimized for line modules in the central office or access networks (LT function) together with the PEB 24901 Quad IEC DFE-T for 4B3T code or the PEB 24911 Quad IEC DFE-Q for ...
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Line Card Application The Quad IEC AFE is controlled via the signal at pin SDX. The transmit data is transferred the same way. The Quad IEC AFE can transmit either 2B1Q-data or 4B3T-data. Setting the pin CODE to low ...
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Figure 5 8 channel LT application (overview channel LT is built with two AFE/DFE sets. One Quad IEC AFE generates the master clock for all four devices. The PLL in the other Quad IEC AFE is passive. IOM ...
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Note: For linecards with 12 or more channels the 15.36 MHz Masterclock must not drive more than 3 inputs. The clocking scheme in Hybrid Hybrid 4x U Hybrid Hybrid Hybrid Hybrid 4x U Hybrid Hybrid Hybrid Hybrid 4x U Hybrid ...
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Technical Description 3.1 Clock Generation All timing signals are derived from a 15.36 MHz system clock. The 15.36 MHz clock can be provided by the Quad IEC AFE by a crystal-based PLL, which is synchronized to either an 8 ...
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H the complex jitter transfer factor = the angular resonance-frequency of the PLL the damping factor of the PLL The maximum phase difference between the external CLOCK and the internal reference, derived ...
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H1e 0.01 0.1 0.01 Figure 9 Maximum Phase Difference Due to Sinusoidal Input Jitter If the input signal at pin CLOCK disappears being stuck to high or low, the PLL continues ...
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Table 2 PLL Characteristcs (cont’d) Parameter Synchronization time of the PLL after power on and applying the reference at pin CLOCK, PLLF = low Synchronization time of the PLL after power on and applying the reference at pin CLOCK, PLLF ...
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Table 3 PLL Input Requirements Parameter Accuracy of the reference at CLOCK to enable synchronization Peak-to peak Jitter of the CLOCK signal during any 125 µsec period Peak-to-peak voltage of a sinusoidal external master clock provided at XIN Low time ...
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Specification of the Crystal A crystal (serial resonance) has to be connected to XIN and XOUT which shall meet the following specification: Table 4 Specification of the crystal Parameter Nominal frequency Total frequency range Operating frequency ...
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Analogue Line Port The Quad IEC AFE Chip gives access to four line ports. The signal to be transmitted is issued differentially at pins AOUT0..3 and BOUT0..3. The input is differentially sampled at AIN0..3 and BIN0..3. Each line port ...
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Table 5 Specified Data of the Analogue-to-Digital Converter Parameter Signal/Noise (sine wave 1.5 Vpp between AINx/BINx) Signal/(Noise+ Distortion) (sine wave 0.4 Vpp between AINx/BINx) Signal/(Noise+Distortion) (sine wave 1.5 Vpp between AINx/BINx) Signal/(Noise+Distortion) (sine wave 2.0 Vpp between AINx/BINx) Signal/(Noise + ...
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Table 5 Specified Data of the Analogue-to-Digital Converter (cont’d) Parameter Attenuation of the range function 5.45 Impedance between AINx and BINx Input capacitance at AINx and BINx Input voltage range at AINx and BINx Common Mode Rejection Ratio Power Supply ...
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The duration of each pulse is 24 steps, with t = 0.78 µsec per step for 2B1Q code and 0.52 µsec per step for 4B3T code. The pulse rate is one pulse per 16 steps, e.g. 80 kHz for 2B1Q ...
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The switch is closed during 1/3 of the sample period. Hence, during the time, the output signal does not change. This way, a settling behavior is achieved which is slowed down by a factor of three ...
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Table 6 Specified Data of the Digital-to-Analogue-Converter Parameter absolute peak voltage measured for a single + pulse between AOUTx and BOUTx absolute peak voltage measured for a single + pulse between AOUTx and BOUTx Common mode ...
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External Hybrid and Transformer Parameters For the 2B1Q-code and the 4B3T-code different external hybrids are suggested in figures 13 and 14. These hybrids will work correctly with an according transformer as described in table 7. Please note that table ...
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Figure 14 Example of External Hybrid Circuit for 4B3T Code Table 7 Transformer Parameters Parameter Transformation ratio; Device side : Line side Main inductance of windings on the line side Leakage inductance of windings on the line side Coupling capacitance ...
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Analogue Loop-back Function The loop-back bit (LOOP) set to ONE on SDX activates an internal analogue loop-back. This loop-back is closed near the U interface. Signals received on AINx / BINx will neither be evaluated nor recognized by the ...
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Table 8 Specified Data of the Level Detection Circuit Parameter Cut-off frequency of the input filter Threshold of level detect (2B1Q) Threshold of level detect (4B3T) DC level of level detect (common mode level) 3.2.7 Power down Transmit path, receive ...
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Figure 16 Power-on-reset behaviour of the AFE V1.2 after V Table 9 Parameters for POR activation Parameter Maximum V slope (rising or falling) DD POR enable threshold V -below-1V-time DD Data Sheet min 80ns Limit ...
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Reset The reset is activated by setting pin RES to low. The following functions are reset: – The reset activates the powerdown of all line ports. – The data on SDX is ignored during reset. – SDR is set ...
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Digital Interface On the digital interface transmit and receive data is exchanged as well as control information for the start-up procedure. The ADC output is transferred to the Quad IEC DFE T or Quad IEC DFE Q on the ...
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The status on SDR is synchronized to SDX. Each time slot on SDR carries the corresponding LD bit during the last 20 bits of the slot. 21 Bit 21 Bit 21 Bit Slot 0 Slot 1 Slot ...
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Figure 18 Frame Structure on SDX/SDR in 4B3T Mode The 4B3T data is coded with the bits TD1, TD0: Table 11 Coding of the 4B3T data pulse (AOUTx/BOUTx) 4B3T Data Pulse – 1 Data Sheet TD1 TD0 ...
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Propagation Delay in transmit direction The start of the transmit pulse is defined as given in Figure 19 Definition of Transmit Pulse Start The delay in transmit direction depends on the slot x on SDX. The pulses on the ...
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Boundary Scan Test Controller The Quad IEC AFE provides a boundary scan support for a cost effective board testing. It consists of: – Complete boundary scan for 11 signals (pins) according to IEEE Std. 1149.1 specification. – Test access ...
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Table 13 Sequence of Pins in the boundary scan (cont’d) Boundary Scan Pin Number Number TDI ––> TAP Controller The Test Access Port (TAP) controller implements the state machine defined in the ...
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SAMPLE/PRELOAD provides a snap-shot of the pin level during normal operation or is used to preload (TDI) / shift out (TDO) the boundary scan with a test vector. Both activities are transparent to the system functionality. IDCODE Register The 32-bit ...
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Digital Interface Unless otherwise specified, the static and dynamic limits apply over a supply voltage range from 4.75 to 5.25 V and over the temperature range as specified in section 7.2. 4.1 Static Requirements Table 15 Static Characteristics Parameter ...
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Boundary Scan Timing TCK TMS TDI TDO Figure 20 Boundary Scan Timing Parameter test clock period test clock period low test clock period high TMS set-up time to TCK TMS hold time from TCK TDI set-up time to TCK ...
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Power Supply 5.1 Supply Voltages VDD to GND d1 d1 VDD to GND d2 d2 VDD to GND a1 a1 VDD to GND a2 a2 VDD to GND a3 a3 VDD to GND a4 a4 The following blocking circuitry ...
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Power Consumption All measurements with random 2B+D data in active states, 5V (0°C - 70°C). Table 17 Power Consumption (2B1Q mode) Parameter Symbol 98 load at AOUTx/BOUTx 98 load at AOUTx/BOUTx All inputs are tied GND ...
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Maximum Ratings Stresses above those listed in table 19 may cause permanent damage to the device. Exposure to conditions beyond those indicated in affect device reliability. This is a stress rating only and functional operation of the device under ...
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Figure 22 Maximum Line input current Data Sheet 45 PEB 24902 PEF 24902 Maximum Ratings 2001-01-23 ...
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Environmental Requirements 7.1 Storage and Transportation The rated (limited capability) storage and transportation temperature range prior to printed board assembly shall be as follows +150°C (without supply voltage) 7.2 Operating Ambient The operating ambient temperature for ...
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Package Outlines Plastic Package, P-MQFP-64-1 (Plastic Metric Quad Flat Package) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information”. SMD = Surface Mounted Device Data Sheet 47 PEB 24902 PEF 24902 ...
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